[all-commits] [llvm/llvm-project] c44cf2: xxx - Add tests for coalescer bug report
Matt Arsenault via All-commits
all-commits at lists.llvm.org
Tue Mar 11 20:10:45 PDT 2025
Branch: refs/heads/users/arsenm/register-coalescer/inflate-source-reg-class-subreg-insert
Home: https://github.com/llvm/llvm-project
Commit: c44cf2c2c7f50bcb935b9e60d1c6259ed8a73f0b
https://github.com/llvm/llvm-project/commit/c44cf2c2c7f50bcb935b9e60d1c6259ed8a73f0b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/coalescer-better-job-with-av-32.mir
A llvm/test/CodeGen/AMDGPU/coalescer-worse-job-with-vgpr-32-instead-of-av-32.mir
Log Message:
-----------
xxx - Add tests for coalescer bug report
Commit: 08d99d001909aba3975ab2add8da42349729dd1e
https://github.com/llvm/llvm-project/commit/08d99d001909aba3975ab2add8da42349729dd1e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
A llvm/test/CodeGen/ARM/coalescer-inflate-subreg-insert-regclass-constraint.mir
Log Message:
-----------
Add ARM testcase
Commit: 9fdf6f9b868135eeb91c1caea9b48b2656e89025
https://github.com/llvm/llvm-project/commit/9fdf6f9b868135eeb91c1caea9b48b2656e89025
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
RegisterCoalescer: Expand source register class to coalesce subreg inserts
This fixes worse coalescing on AMDGPU in situations where VGPRs are copied
into AGPRs. E.g.
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
undef %2.sub0:areg_64 = COPY %0
%2.sub1:areg_64 = COPY %2
Commit: 45427e3c70236e9ab937af9024f4d70b692e144e
https://github.com/llvm/llvm-project/commit/45427e3c70236e9ab937af9024f4d70b692e144e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/X86/h-registers-1.ll
M llvm/test/CodeGen/X86/vec-strict-fptoint-512.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
Log Message:
-----------
test update
Commit: 93da7debe48ac401f0f45771b666da7da8da6812
https://github.com/llvm/llvm-project/commit/93da7debe48ac401f0f45771b666da7da8da6812
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
Hack up the class
Commit: 4a016b35a761a53601b011d74832a04ff85d745f
https://github.com/llvm/llvm-project/commit/4a016b35a761a53601b011d74832a04ff85d745f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
M llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
Log Message:
-----------
good test update
Commit: b67c8dc8e3ddd54e85a9e433e8b4619b2dc097a0
https://github.com/llvm/llvm-project/commit/b67c8dc8e3ddd54e85a9e433e8b4619b2dc097a0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
hack
Commit: 8ff1b922fe64eeade63b9afbd041a044d7c5f259
https://github.com/llvm/llvm-project/commit/8ff1b922fe64eeade63b9afbd041a044d7c5f259
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
Factor into func
Commit: e3b07171441aafac3549d98c6edf7a4daed8f326
https://github.com/llvm/llvm-project/commit/e3b07171441aafac3549d98c6edf7a4daed8f326
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
unbreak
Commit: 26624fce719963817870274bf0761971feb98bfa
https://github.com/llvm/llvm-project/commit/26624fce719963817870274bf0761971feb98bfa
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
Debug print
Commit: 16cc38eeb8ae030190d0b47e1cf911608c182dae
https://github.com/llvm/llvm-project/commit/16cc38eeb8ae030190d0b47e1cf911608c182dae
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
XXX get largest dstrc too
Commit: 4313086b9c3f97272e71b5db67f2ea14cb8de271
https://github.com/llvm/llvm-project/commit/4313086b9c3f97272e71b5db67f2ea14cb8de271
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
debug print
Commit: 4baac124914659bb962722d1551efcc5dddad0ed
https://github.com/llvm/llvm-project/commit/4baac124914659bb962722d1551efcc5dddad0ed
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
work on class adjustment
Commit: fa2db6b2f90dcf72250858d112d74ca772f4936b
https://github.com/llvm/llvm-project/commit/fa2db6b2f90dcf72250858d112d74ca772f4936b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
More debug
Commit: 7ecf43b25a44456bbef59863bf68ce304e2c3ff6
https://github.com/llvm/llvm-project/commit/7ecf43b25a44456bbef59863bf68ce304e2c3ff6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/test/CodeGen/PowerPC/pr47891.ll
M llvm/test/CodeGen/PowerPC/widen-vec-correctly-be.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
Log Message:
-----------
test updates
Commit: a04fdf9cbff687b1da01c0aa56e575dca398ae72
https://github.com/llvm/llvm-project/commit/a04fdf9cbff687b1da01c0aa56e575dca398ae72
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
find class work
Commit: 4fc92126963a3e457d08a67561b17f0f4bfcc530
https://github.com/llvm/llvm-project/commit/4fc92126963a3e457d08a67561b17f0f4bfcc530
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
comment
Commit: 59cfd65abd02beeea9cec75e6a77d77c270d187d
https://github.com/llvm/llvm-project/commit/59cfd65abd02beeea9cec75e6a77d77c270d187d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
M llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
M llvm/test/CodeGen/X86/vec-strict-fptoint-512.ll
Log Message:
-----------
test updates
Commit: df2e0ec746a2d699b3ebbf25e417b673afd2c0fb
https://github.com/llvm/llvm-project/commit/df2e0ec746a2d699b3ebbf25e417b673afd2c0fb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/test/CodeGen/PowerPC/pr47891.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
Log Message:
-----------
test update restore
Commit: e36f30c7e4d12dcabaab54ebea65220e7d8011c6
https://github.com/llvm/llvm-project/commit/e36f30c7e4d12dcabaab54ebea65220e7d8011c6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
one use
Commit: 803342fa9194d0d4358f7e7f2a13c98bd8aeccfc
https://github.com/llvm/llvm-project/commit/803342fa9194d0d4358f7e7f2a13c98bd8aeccfc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
Use TRI.getMatchingSuperRegClass in loop
Commit: 3af1561ecfa19fded69b3a8305e9c1918ad18727
https://github.com/llvm/llvm-project/commit/3af1561ecfa19fded69b3a8305e9c1918ad18727
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
junk
Commit: 34a866b294a5e9a7a0fefae142468b5bc0caa19c
https://github.com/llvm/llvm-project/commit/34a866b294a5e9a7a0fefae142468b5bc0caa19c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
Log Message:
-----------
test consistency
Compare: https://github.com/llvm/llvm-project/compare/4aa5ce7d2320...34a866b294a5
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list