[all-commits] [llvm/llvm-project] 07f730: xxx - Add tests for coalescer bug report
Matt Arsenault via All-commits
all-commits at lists.llvm.org
Tue Mar 11 19:33:44 PDT 2025
Branch: refs/heads/users/arsenm/register-coalescer/inflate-source-reg-class-subreg-insert
Home: https://github.com/llvm/llvm-project
Commit: 07f730c4d7a2639804bede6e88d4a930ac2d44b2
https://github.com/llvm/llvm-project/commit/07f730c4d7a2639804bede6e88d4a930ac2d44b2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/coalescer-better-job-with-av-32.mir
A llvm/test/CodeGen/AMDGPU/coalescer-worse-job-with-vgpr-32-instead-of-av-32.mir
Log Message:
-----------
xxx - Add tests for coalescer bug report
Commit: b75ad4a6ef1dd727816fec7fe8448c3687c55101
https://github.com/llvm/llvm-project/commit/b75ad4a6ef1dd727816fec7fe8448c3687c55101
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
A llvm/test/CodeGen/ARM/coalescer-inflate-subreg-insert-regclass-constraint.mir
Log Message:
-----------
Add ARM testcase
Commit: 0fd41d0e22010be79a701f0ee678a8a9f633a236
https://github.com/llvm/llvm-project/commit/0fd41d0e22010be79a701f0ee678a8a9f633a236
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
RegisterCoalescer: Expand source register class to coalesce subreg inserts
This fixes worse coalescing on AMDGPU in situations where VGPRs are copied
into AGPRs. E.g.
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
undef %2.sub0:areg_64 = COPY %0
%2.sub1:areg_64 = COPY %2
Commit: 042ae81a20c2e08120bb6bedafc7b3f3673bfa64
https://github.com/llvm/llvm-project/commit/042ae81a20c2e08120bb6bedafc7b3f3673bfa64
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/X86/h-registers-1.ll
M llvm/test/CodeGen/X86/vec-strict-fptoint-512.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
Log Message:
-----------
test update
Commit: 34f99676b2b40e42449ba472c60659422234bcc4
https://github.com/llvm/llvm-project/commit/34f99676b2b40e42449ba472c60659422234bcc4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
Hack up the class
Commit: 5999dbec43a63cbc4480bda8e1f33375c4853822
https://github.com/llvm/llvm-project/commit/5999dbec43a63cbc4480bda8e1f33375c4853822
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
M llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
Log Message:
-----------
good test update
Commit: 154c65bbd32ba321ebcca7ea907db2d32844646e
https://github.com/llvm/llvm-project/commit/154c65bbd32ba321ebcca7ea907db2d32844646e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
hack
Commit: 67bf5937e320dcb19d3c8dbc0ded0b5f7de3447e
https://github.com/llvm/llvm-project/commit/67bf5937e320dcb19d3c8dbc0ded0b5f7de3447e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
Factor into func
Commit: f33c411c1ec01b2b6be29cd21feb0057d12663e0
https://github.com/llvm/llvm-project/commit/f33c411c1ec01b2b6be29cd21feb0057d12663e0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
unbreak
Commit: b0b97d98b95f8e8d6926d3e938763a3702a6fedd
https://github.com/llvm/llvm-project/commit/b0b97d98b95f8e8d6926d3e938763a3702a6fedd
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
Debug print
Commit: 05b401e1cea7376974a96e7c5272340619765acd
https://github.com/llvm/llvm-project/commit/05b401e1cea7376974a96e7c5272340619765acd
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
XXX get largest dstrc too
Commit: 1bebaa2509ba652d9689fa78c945a4b527b24223
https://github.com/llvm/llvm-project/commit/1bebaa2509ba652d9689fa78c945a4b527b24223
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
debug print
Commit: 347151dd28bb1c895a54b30cde9e2f018a2f79e4
https://github.com/llvm/llvm-project/commit/347151dd28bb1c895a54b30cde9e2f018a2f79e4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
work on class adjustment
Commit: ecebe9a6a49e03725ca2d9cf137acc548601b7df
https://github.com/llvm/llvm-project/commit/ecebe9a6a49e03725ca2d9cf137acc548601b7df
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
More debug
Commit: 37e35b0fb9b4db73eb6e3fe6e5e25991f271e317
https://github.com/llvm/llvm-project/commit/37e35b0fb9b4db73eb6e3fe6e5e25991f271e317
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/test/CodeGen/PowerPC/pr47891.ll
M llvm/test/CodeGen/PowerPC/widen-vec-correctly-be.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
Log Message:
-----------
test updates
Commit: 511d947e53d6d4fe25ffa77a90ba0a575f769084
https://github.com/llvm/llvm-project/commit/511d947e53d6d4fe25ffa77a90ba0a575f769084
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
find class work
Commit: 61bd7f35a17398491e2fcaeb9f925e416ca2d3d7
https://github.com/llvm/llvm-project/commit/61bd7f35a17398491e2fcaeb9f925e416ca2d3d7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
comment
Commit: 30104b5854701419c7c87f79dfd2ac8530e025a7
https://github.com/llvm/llvm-project/commit/30104b5854701419c7c87f79dfd2ac8530e025a7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
M llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
M llvm/test/CodeGen/X86/vec-strict-fptoint-512.ll
Log Message:
-----------
test updates
Commit: 535a3d8ecb6b67ae8c9e265f9ce462a4b6687376
https://github.com/llvm/llvm-project/commit/535a3d8ecb6b67ae8c9e265f9ce462a4b6687376
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/test/CodeGen/PowerPC/pr47891.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
Log Message:
-----------
test update restore
Commit: 8ff39a1cb3a30b3ea40f42123979a2d37f8b401e
https://github.com/llvm/llvm-project/commit/8ff39a1cb3a30b3ea40f42123979a2d37f8b401e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
one use
Commit: c5bcaccd3c108904dd0a25f4a956cb17523236c8
https://github.com/llvm/llvm-project/commit/c5bcaccd3c108904dd0a25f4a956cb17523236c8
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
Use TRI.getMatchingSuperRegClass in loop
Commit: f5e413102e0e061388388ddde06beb8411d4571e
https://github.com/llvm/llvm-project/commit/f5e413102e0e061388388ddde06beb8411d4571e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
junk
Commit: 4aa5ce7d2320305d33c2a6b4fdcc327102058720
https://github.com/llvm/llvm-project/commit/4aa5ce7d2320305d33c2a6b4fdcc327102058720
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-12 (Wed, 12 Mar 2025)
Changed paths:
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
Log Message:
-----------
test consistency
Compare: https://github.com/llvm/llvm-project/compare/07f730c4d7a2%5E...4aa5ce7d2320
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