[all-commits] [llvm/llvm-project] 4d17ae: [MLIR][Affine] Fix affine-loop-tile zero cache siz...

[Uday Bondhugula via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4d17ae7776ef6ffe2dd04c146632282ac173cae6
      https://github.com/llvm/llvm-project/commit/4d17ae7776ef6ffe2dd04c146632282ac173cae6
  Author: Uday Bondhugula <uday at polymagelabs.com>
  Date:   2025-03-11 (Tue, 11 Mar 2025)

  Changed paths:
    M mlir/lib/Dialect/Affine/Transforms/LoopTiling.cpp
    M mlir/test/Dialect/Affine/loop-tiling.mlir

  Log Message:
  -----------
  [MLIR][Affine] Fix affine-loop-tile zero cache size corner case crash (#130526)

Fixes: https://github.com/llvm/llvm-project/issues/64979



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