[all-commits] [llvm/llvm-project] 148a7a: [X86] combineConcatVectorOps - add support for AVX...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 148a7ae328b431f07c0d1fca9e0e9e232c054967
      https://github.com/llvm/llvm-project/commit/148a7ae328b431f07c0d1fca9e0e9e232c054967
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2025-03-11 (Tue, 11 Mar 2025)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/avx-shift.ll
    M llvm/test/CodeGen/X86/gfni-shifts.ll
    M llvm/test/CodeGen/X86/known-bits-vector.ll
    M llvm/test/CodeGen/X86/pmul.ll
    M llvm/test/CodeGen/X86/vector-fshl-256.ll
    M llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
    M llvm/test/CodeGen/X86/vector-fshr-256.ll
    M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
    M llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
    M llvm/test/CodeGen/X86/vector-rotate-256.ll
    M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
    M llvm/test/CodeGen/X86/vector-shuffle-v192.ll

  Log Message:
  -----------
  [X86] combineConcatVectorOps - add support for AVX1 and/or/xor/andnp concatenation (#130645)

Limit AVX1-only targets to cases where at least one operand is
beneficial to concatenate, but avoid unnecessary 256-bit NOT patterns
unless it allows further folds.

There are still a large number of regressions when limiting AVX2+
targets to beneficial concatenation - so added a TODO for now.



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