[all-commits] [llvm/llvm-project] fa315e: [RISCV] Convert vsub.vx to vadd.vi if possible (#1...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fa315eceb7ab6106729c6b52495891c3f0f58478
      https://github.com/llvm/llvm-project/commit/fa315eceb7ab6106729c6b52495891c3f0f58478
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-03-10 (Mon, 10 Mar 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fold-binop-into-select.ll
    M llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
    M llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll

  Log Message:
  -----------
  [RISCV] Convert vsub.vx to vadd.vi if possible (#130669)

We'd already had this transform for the intrinsics, but hadn't added it
for either fixed length or scalable vectors coming from normal IR.

For the record, the fact we have three different sets of patterns here
really is quite ugly.



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