[all-commits] [llvm/llvm-project] fe544d: [lldb] Add more ARM checks in TestLldbGdbServer.py...

[David Spickett via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fe544d404d841ef44aebf4fc36948fd1e1d89685
      https://github.com/llvm/llvm-project/commit/fe544d404d841ef44aebf4fc36948fd1e1d89685
  Author: David Spickett <david.spickett at linaro.org>
  Date:   2025-03-10 (Mon, 10 Mar 2025)

  Changed paths:
    M lldb/packages/Python/lldbsuite/test/lldbtest.py
    M lldb/test/API/tools/lldb-server/TestLldbGdbServer.py

  Log Message:
  -----------
  [lldb] Add more ARM checks in TestLldbGdbServer.py (#130277)

When https://github.com/llvm/llvm-project/pull/130034 enabled RISC-V
here I noticed that these should run for ARM as well.

ARM only has 4 argument registers, which matches Arm's ABI for it:
https://github.com/ARM-software/abi-aa/blob/main/aapcs32/aapcs32.rst#core-registers

The ABI defines a link register LR, and I assume that's what becomes
'ra' in LLDB.

Tested on ARM and AArch64 Linux.



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