[all-commits] [llvm/llvm-project] ecec7d: DAG: Use phi in alloca constant case to create vir...
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Fri Mar 7 18:59:39 PST 2025
Branch: refs/heads/users/vitalybuka/spr/nfclto-move-guid-calculation-into-cfifunctionindex
Home: https://github.com/llvm/llvm-project
Commit: ecec7d15a7024dbeb81cb7e7be814750d6615d20
https://github.com/llvm/llvm-project/commit/ecec7d15a7024dbeb81cb7e7be814750d6615d20
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-08 (Sat, 08 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll
Log Message:
-----------
DAG: Use phi in alloca constant case to create virtual registers (#130254)
This is a follow up from 39bf765bb671fa7df3fe6c164cc9532fcb8653bd,
for the other case handled here. We would create CopyToReg marked
as uniform, even though the end phi would need to use VGPRs due
to another divergent input. There's no directly observable change in
the final output of the new test, but it does hit this case.
Commit: 8ce612ff702bf78137e3cea0544351d4826f9f69
https://github.com/llvm/llvm-project/commit/8ce612ff702bf78137e3cea0544351d4826f9f69
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-08 (Sat, 08 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-break-large-phis.ll
M llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll
M llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll
M llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
M llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/fold-fabs.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll
M llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll
M llvm/test/CodeGen/AMDGPU/madmk.ll
M llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/rewrite-undef-for-phi.ll
M llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-undef.ll
M llvm/test/CodeGen/AMDGPU/si-spill-cf.ll
M llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
M llvm/test/CodeGen/AMDGPU/switch-default-block-unreachable.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/uniform-phi-with-undef.ll
M llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
Log Message:
-----------
AMDGPU: Replace undef phi inputs with poison in tests (#130267)
I think the chance of this changing the tests in meaningful ways
is very low. This was perl with a few minor adjustments to a few
tests that produce new undefs. Only one test had a minor codegen
change with the switch, which I dropped from the change.
Commit: ab87206c4b95aa0b5047facffb5f78f7fe6ac269
https://github.com/llvm/llvm-project/commit/ab87206c4b95aa0b5047facffb5f78f7fe6ac269
Author: JaydeepChauhan14 <chauhan.jaydeep.ashwinbhai at intel.com>
Date: 2025-03-08 (Sat, 08 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
M llvm/test/CodeGen/X86/exp10-libcall-names.ll
M llvm/test/CodeGen/X86/finite-libcalls.ll
Log Message:
-----------
[X86][GlobalISel] Enable POW/EXP*/LOG* functions with libcall mapping (#130328)
Commit: 76393d3863bf7394edb69fb6a371b9a1c2c09ff6
https://github.com/llvm/llvm-project/commit/76393d3863bf7394edb69fb6a371b9a1c2c09ff6
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M clang/test/CodeGenCXX/wasm-eh.cpp
Log Message:
-----------
[WebAssembly] Rename functions in wasm-eh.cpp (#130220)
I think it is generally better for tests have some descriptive function
names so that we can insert new tests in the middle and don't have to
renumber all tests.
Also recently I added a (named) test to this file in #129020 so I think
it's consistent for other tests to be named.
Commit: 15869a861b598b06f3888dcc12882b8bb2325671
https://github.com/llvm/llvm-project/commit/15869a861b598b06f3888dcc12882b8bb2325671
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2025-03-08 (Sat, 08 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
Log Message:
-----------
[AMDGPU][MC] Don't crash on decoding invalid SOP1 ssrc0 operands. (#130302)
These are encoded as 8-bit fields.
Commit: a5588b6d20590a10db0f1a2046fba4d9f205ed68
https://github.com/llvm/llvm-project/commit/a5588b6d20590a10db0f1a2046fba4d9f205ed68
Author: Connector Switch <c8ef at outlook.com>
Date: 2025-03-08 (Sat, 08 Mar 2025)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/strings.yaml
M libc/src/strings/CMakeLists.txt
A libc/src/strings/ffs.cpp
A libc/src/strings/ffs.h
A libc/src/strings/ffsl.cpp
A libc/src/strings/ffsl.h
A libc/src/strings/ffsll.cpp
A libc/src/strings/ffsll.h
M libc/test/src/strings/CMakeLists.txt
A libc/test/src/strings/ffs_test.cpp
A libc/test/src/strings/ffsl_test.cpp
A libc/test/src/strings/ffsll_test.cpp
Log Message:
-----------
[libc] implement `strings/ffs` (#129892)
This patch adds the `strings/ffs` function.
ref: https://pubs.opengroup.org/onlinepubs/9799919799/functions/ffs.html
Closes: #122054.
Commit: 5bc166728abe3c80a271d3883d12805161b96335
https://github.com/llvm/llvm-project/commit/5bc166728abe3c80a271d3883d12805161b96335
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M llvm/include/llvm/ADT/EquivalenceClasses.h
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/unittests/ADT/EquivalenceClassesTest.cpp
Log Message:
-----------
Revert "Reland [EquivClasses] Introduce members iterator-helper" (#130380)
Reverts llvm/llvm-project#130319
Multiple bot failures.
Commit: cf1964af5a461196904b663ede04c26555fcff69
https://github.com/llvm/llvm-project/commit/cf1964af5a461196904b663ede04c26555fcff69
Author: R <rqou at berkeley.edu>
Date: 2025-03-08 (Sat, 08 Mar 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/CodeGen/TypeConverter.cpp
A flang/test/Fir/alloc-32.fir
M flang/test/Fir/alloc.fir
M flang/test/Integration/OpenMP/private-global.f90
M flang/test/Lower/OpenMP/parallel-reduction-mixed.f90
M flang/test/Lower/forall/character-1.f90
Log Message:
-----------
[flang] In AllocMemOp lowering, convert types for calling malloc on 32-bit (#129308)
Although 32-bit targets are currently not officially supported, add a type conversion in the AllocMemOp lowering when calling the `malloc` function on 32-bit targets. This fixes a type mismatch, and this fix makes it easier to potentially support such targets in the future.
This involves making sure the `LLVMTypeConverter` has the necessary information to know the target bit width.
Co-authored-by: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Commit: d8747eac36fb4f965de3cef252227be775a59959
https://github.com/llvm/llvm-project/commit/d8747eac36fb4f965de3cef252227be775a59959
Author: Bruno Cardoso Lopes <bruno.cardoso at gmail.com>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[MLIR][LLVMIR] Translation: honor frame-pointer fn attribute (#130335)
Commit: 3121da52aa788199185585aa11f3d55b03adc93d
https://github.com/llvm/llvm-project/commit/3121da52aa788199185585aa11f3d55b03adc93d
Author: R <rqou at berkeley.edu>
Date: 2025-03-08 (Sat, 08 Mar 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/CodeGen/TypeConverter.cpp
R flang/test/Fir/alloc-32.fir
M flang/test/Fir/alloc.fir
M flang/test/Integration/OpenMP/private-global.f90
M flang/test/Lower/OpenMP/parallel-reduction-mixed.f90
M flang/test/Lower/forall/character-1.f90
Log Message:
-----------
Revert "[flang] In AllocMemOp lowering, convert types for calling malloc on 32-bit (#129308)"
This reverts commit cf1964af5a461196904b663ede04c26555fcff69.
This causes breakage on all the non-x86 buildbots as they don't have the i686
target enabled. This was missed in pre-commit CI.
Commit: 89a7cdce2b702d34519d2390b4fc719cefc06614
https://github.com/llvm/llvm-project/commit/89a7cdce2b702d34519d2390b4fc719cefc06614
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M clang/test/CodeGenCXX/wasm-eh.cpp
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/strings.yaml
M libc/src/strings/CMakeLists.txt
A libc/src/strings/ffs.cpp
A libc/src/strings/ffs.h
A libc/src/strings/ffsl.cpp
A libc/src/strings/ffsl.h
A libc/src/strings/ffsll.cpp
A libc/src/strings/ffsll.h
M libc/test/src/strings/CMakeLists.txt
A libc/test/src/strings/ffs_test.cpp
A libc/test/src/strings/ffsl_test.cpp
A libc/test/src/strings/ffsll_test.cpp
M llvm/include/llvm/ADT/EquivalenceClasses.h
M llvm/include/llvm/IR/ModuleSummaryIndex.h
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-break-large-phis.ll
M llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll
M llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll
M llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll
M llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/fold-fabs.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll
M llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll
M llvm/test/CodeGen/AMDGPU/madmk.ll
M llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/rewrite-undef-for-phi.ll
M llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-undef.ll
M llvm/test/CodeGen/AMDGPU/si-spill-cf.ll
M llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
M llvm/test/CodeGen/AMDGPU/switch-default-block-unreachable.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/uniform-phi-with-undef.ll
M llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/X86/exp10-libcall-names.ll
M llvm/test/CodeGen/X86/finite-libcalls.ll
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
M llvm/unittests/ADT/EquivalenceClassesTest.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
rebase
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/0aa5b6100ade...89a7cdce2b70
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