[all-commits] [llvm/llvm-project] d19218: [SelectionDAG] Preserve fast math flags when legal...

[John Brawn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d19218e507b5613b9708ce0cd38aceb282a9d812
      https://github.com/llvm/llvm-project/commit/d19218e507b5613b9708ce0cd38aceb282a9d812
  Author: John Brawn <john.brawn at arm.com>
  Date:   2025-03-07 (Fri, 07 Mar 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
    M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
    A llvm/test/CodeGen/AArch64/fp16_fast_math.ll
    A llvm/test/CodeGen/ARM/fp16_fast_math.ll
    M llvm/test/CodeGen/ARM/vecreduce-fmax-legalization-soft-float.ll
    M llvm/test/CodeGen/ARM/vecreduce-fmin-legalization-soft-float.ll

  Log Message:
  -----------
  [SelectionDAG] Preserve fast math flags when legalizing/promoting (#130124)

When we have a floating-point operation that a target doesn't support
for a given type, but does support for a wider type, then there are two
ways this can be handled:

* If the target doesn't have any registers at all of this type then
LegalizeTypes will convert the operation.

* If we do have registers but no operation for this type, then the
operation action will be Promote and it's handled in PromoteNode.

In both cases the operation at the wider type, and the conversion
operations to and from that type, should have the same fast math flags
as the original operation.

This is being done in preparation for a DAGCombine patch which makes use
of these fast math flags.



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