[all-commits] [llvm/llvm-project] 5048a0: [RISCV] Generate MIPS load/store pair instructions...

[Djordje Todorovic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5048a0858beb15bdd203dee89dd4df9b2a72ba5f
      https://github.com/llvm/llvm-project/commit/5048a0858beb15bdd203dee89dd4df9b2a72ba5f
  Author: Djordje Todorovic <djordje.todorovic at htecgroup.com>
  Date:   2025-03-07 (Fri, 07 Mar 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/CMakeLists.txt
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.h
    A llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
    M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    A llvm/test/CodeGen/RISCV/load-store-pair.ll

  Log Message:
  -----------
  [RISCV] Generate MIPS load/store pair instructions (#124717)

Introduce RISCVLoadStoreOptimizer MIR Pass that will do the
optimization. The load/store pairing pass identifies adjacent load/store
instructions operating on consecutive memory locations and merges them
into a single paired instruction.

This is part of MIPS extensions for the p8700 CPU.

Production of ldp/sdp instructions is OFF by default, since it is
beneficial for -Os only in the case of p8700 CPU.



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