[all-commits] [llvm/llvm-project] ab1dce: AMDGPU: Add pseudoinstruction for agpr or vgpr con...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/amdgpu/add-av-mov-b32-pseudo
  Home:   https://github.com/llvm/llvm-project
  Commit: ab1dce66501b6c2419c1f96cf004609b1c9dd057
      https://github.com/llvm/llvm-project/commit/ab1dce66501b6c2419c1f96cf004609b1c9dd057
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-03-07 (Fri, 07 Mar 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    A llvm/test/CodeGen/AMDGPU/av_movimm_pseudo_expansion.mir
    M llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
    A llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir
    M llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-do-not-undo-subclass-split-with-remat.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
    A llvm/test/MachineVerifier/AMDGPU/verify-av-mov-imm-pseudo.mir

  Log Message:
  -----------
  AMDGPU: Add pseudoinstruction for agpr or vgpr constants

Currently constants are materialized with v_mov_b32, which
may fold into v_accvgpr_write_b32 if it happens to be copied
into an AGPR use. This is fine until the register allocator
wants to introduce temporary registers using the combined AV_
superclasses. Since each of these instructions is restricted to
writing the specific subclass, they block instances where
we could inflate the use register class. As v_accvgpr_write_b32 cannot
use a literal constant, only inline immediate values should be used
with the pseudo.

Introduce a pseudo with a flexible result register class. Alternatively
we would need to teach allocation about how to rewrite or rematerialize
with a change of opcode which would require a lot more machinery.

We may want a 64-bit variant, just in case we can make use of v_mov_b64.

This does not yet attempt to make use of it, and only adds the boilerplate
and tests on basic optimizations.


  Commit: 7690ffd0f6b8a36444521febe636cf5153ecea27
      https://github.com/llvm/llvm-project/commit/7690ffd0f6b8a36444521febe636cf5153ecea27
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-03-07 (Fri, 07 Mar 2025)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir

  Log Message:
  -----------
  Add broken tests from preexisting failure


  Commit: a1e2c4874280c7d6334ac5e407dc1391bb3d70a7
      https://github.com/llvm/llvm-project/commit/a1e2c4874280c7d6334ac5e407dc1391bb3d70a7
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-03-07 (Fri, 07 Mar 2025)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir

  Log Message:
  -----------
  Remove unneeded mir fields


Compare: https://github.com/llvm/llvm-project/compare/9081a0a88666...a1e2c4874280

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