[all-commits] [llvm/llvm-project] f01e76: [AArch64][SVE] Improve fixed-length addressing mod...

[Ricardo Jesus via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f01e760c08365426de95f02dc2c2dc670eb47352
      https://github.com/llvm/llvm-project/commit/f01e760c08365426de95f02dc2c2dc670eb47352
  Author: Ricardo Jesus <rjj at nvidia.com>
  Date:   2025-03-06 (Thu, 06 Mar 2025)

  Changed paths:
    M clang/test/CodeGen/AArch64/sve-vector-bits-codegen.c
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64Subtarget.h
    A llvm/test/CodeGen/AArch64/sve-fixed-length-offsets.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll

  Log Message:
  -----------
  [AArch64][SVE] Improve fixed-length addressing modes. (#129732)

When compiling VLS SVE, the compiler often replaces VL-based offsets
with immediate-based ones. This leads to a mismatch in the allowed
addressing modes due to SVE loads/stores generally expecting immediate
offsets relative to VL. For example, given:
```c

svfloat64_t foo(const double *x) {
  svbool_t pg = svptrue_b64();
  return svld1_f64(pg, x+svcntd());
}
```

When compiled with `-msve-vector-bits=128`, we currently generate:
```gas
foo:
        ptrue   p0.d
        mov     x8, #2
        ld1d    { z0.d }, p0/z, [x0, x8, lsl #3]
        ret
```

Instead, we could be generating:
```gas
foo:
        ldr     z0, [x0, #1, mul vl]
        ret
```

Likewise for other types, stores, and other VLS lengths.

This patch achieves the above by extending `SelectAddrModeIndexedSVE`
to let constants through when `vscale` is known.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications