[all-commits] [llvm/llvm-project] 3cacd0: [AMDGPU] Add GFX12 S_ALLOC_VGPR instruction

[Jannik Silvanus via All-commits]

  Branch: refs/heads/users/rovka/dvgpr-1
  Home:   https://github.com/llvm/llvm-project
  Commit: 3cacd079d8671473213fd273a8df6839723728a2
      https://github.com/llvm/llvm-project/commit/3cacd079d8671473213fd273a8df6839723728a2
  Author: Jannik Silvanus <jannik.silvanus at amd.com>
  Date:   2025-03-06 (Thu, 06 Mar 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SOPInstructions.td
    M llvm/test/MC/AMDGPU/gfx11_unsupported.s
    M llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
    M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt

  Log Message:
  -----------
  [AMDGPU] Add GFX12 S_ALLOC_VGPR instruction

This patch only adds the instruction for disassembly support.

We neither have an instrinsic nor codegen support, and it is
unclear whether we actually want to ever have an intrinsic,
given the fragile semantics.

For now, it will be generated only by the backend in very specific
circumstances.



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