[all-commits] [llvm/llvm-project] 6262d6: [RISCV] Check subtarget feature in getBrCond (#129...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6262d67446474c29a3a03544fff9b2109b7274da
      https://github.com/llvm/llvm-project/commit/6262d67446474c29a3a03544fff9b2109b7274da
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-03-05 (Wed, 05 Mar 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.h

  Log Message:
  -----------
  [RISCV] Check subtarget feature in getBrCond (#129859)

The function currently only checks to see if we compare against an
immediate before selecting the two branch immediate instructions that
are a part of the XCVbi vendor extension. This works at the moment since
there are no other extensions that have a branch immediate instruction.
It would be better if we explicitly check if the XCVbi extension is enabled
before returning the appropriate instruction.

This is also done in preparation for the branch immediate instructions
that are a part of the Xqcibi vendor extension from Qualcomm.



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