[all-commits] [llvm/llvm-project] 3ce67a: [TableGen] Remove unnecessary use of utostr to pri...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Tue Mar 4 09:04:19 PST 2025
Branch: refs/heads/users/alexey-bataev/spr/slpfiximprove-getspillcost-analysis
Home: https://github.com/llvm/llvm-project
Commit: 3ce67a81fac301e7a308c7c6c08e0abd883972e9
https://github.com/llvm/llvm-project/commit/3ce67a81fac301e7a308c7c6c08e0abd883972e9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[TableGen] Remove unnecessary use of utostr to print a byte. NFC
We can cast to unsigned instead.
Commit: efb880de11f8fa3646c04032c0a2c9bded1935d7
https://github.com/llvm/llvm-project/commit/efb880de11f8fa3646c04032c0a2c9bded1935d7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[TableGen] Fix incorrect comment. NFC
Commit: 313b71fc1a9ae17ea5ecba8afcb4e5b80e1f4043
https://github.com/llvm/llvm-project/commit/313b71fc1a9ae17ea5ecba8afcb4e5b80e1f4043
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
Log Message:
-----------
[RISCV] Simplify tracking of tracking and encoding of push/pop in RISCVFrameLowering. NFC (#129343)
Previously we calculated the max register id. Then converted it to the number
of registers and encoding. Then converted number of registers to stack
size. Then saved number of registers, encoding, and stack size to
MachineFunctionInfo.
This patch removes the calculation of max register id, and instead
calculates the number of registers. The encoding is removed from
MachineFunctionInfo in favor of converting the number of registers to
encoding at the time of use.
Commit: 3c90c900ba5ef9f0cb5808c73c388d3ee21cb683
https://github.com/llvm/llvm-project/commit/3c90c900ba5ef9f0cb5808c73c388d3ee21cb683
Author: TatWai Chong <tatwai.chong at arm.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Dialect/Tosa/level_check.mlir
Log Message:
-----------
[mlir][tosa] Add several level checks (#129580)
Add the following types of level check to consolidate the level validity
- Complete rank level checks for operations.
- Add MAX_LOG2_SIZE level check: The maximum value is 63 when the level
is set to "none" and 31 when the level is set to "8K".
- Add MAX_TENSOR_LIST_SIZE level check : The maximum value is 256 when
the level is set to "none" and 64 when the level is set to "8K".
- TOSA 1.0 spec does not allow operations with dynamic shapes, so an
error should be raised instead.
Co-authored-by: Tai Ly <tai.ly at arm.com>
Commit: dfc5f37e3a62a93ce16935cea1d9822bec649a2b
https://github.com/llvm/llvm-project/commit/dfc5f37e3a62a93ce16935cea1d9822bec649a2b
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Move onlyFirstLaneUsed to VPWidenInductionRecipe (NFC).
Move onlyFirstLaneUsed from VPWidenIntOrFpInductionRecipe and
VPWidenPointerInduction to VPWidenInductionRecipe. Also mark step value
as having only its first lane used.
Commit: b2ba43a9c1193f1d90ad9d30dada85caebd2c56d
https://github.com/llvm/llvm-project/commit/b2ba43a9c1193f1d90ad9d30dada85caebd2c56d
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M flang/lib/Semantics/check-declarations.cpp
A flang/test/Semantics/generic13.f90
Log Message:
-----------
[flang] Refine checking of type-bound generics (#129292)
I merged a patch yesterday
(https://github.com/llvm/llvm-project/pull/128980) that strengthened
error detection of indistinguishable specific procedures in a type-bound
generic procedure, and broke a couple of tests. Refine the check so that
it doesn't flag valid cases of overridden bindings, and add a thorough
test with all of the boundary cases that I can think of.
Commit: 79a25e11fe119520e7cb70118df18e199217c891
https://github.com/llvm/llvm-project/commit/79a25e11fe119520e7cb70118df18e199217c891
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M flang/include/flang/Evaluate/characteristics.h
M flang/include/flang/Evaluate/tools.h
M flang/lib/Evaluate/check-expression.cpp
M flang/lib/Evaluate/fold-logical.cpp
M flang/lib/Evaluate/fold.cpp
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Evaluate/shape.cpp
M flang/lib/Evaluate/tools.cpp
M flang/lib/Lower/ConvertConstant.cpp
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/data-to-inits.cpp
M flang/lib/Semantics/definable.cpp
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/pointer-assignment.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Evaluate/folding06.f90
M flang/test/Lower/HLFIR/null.f90
M flang/test/Semantics/associated.f90
M flang/test/Semantics/call27.f90
M flang/test/Semantics/null01.f90
Log Message:
-----------
[flang] Further work on NULL(MOLD=allocatable) (#129345)
Refine handling of NULL(...) in semantics to properly distinguish
NULL(), NULL(objectPointer), NULL(procPointer), and NULL(allocatable)
from each other in relevant contexts.
Add IsNullAllocatable() and IsNullPointerOrAllocatable() utility
functions. IsNullAllocatable() is true only for NULL(allocatable); it is
false for a bare NULL(), which can be detected independently with
IsBareNullPointer().
IsNullPointer() now returns false for NULL(allocatable).
ALLOCATED(NULL(allocatable)) now works, and folds to .FALSE.
These utilities were modified to accept const pointer arguments rather
than const references; I usually prefer this style when the result
should clearly be false for a null argument (in the C sense), and it
helped me find all of their use sites in the code.
Commit: f6e83664e01e8dcb9bf241dd0154ff3adcc2e876
https://github.com/llvm/llvm-project/commit/f6e83664e01e8dcb9bf241dd0154ff3adcc2e876
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M flang/lib/Semantics/check-declarations.cpp
M flang/test/Semantics/coarrays02.f90
M flang/test/Semantics/init01.f90
Log Message:
-----------
[flang] Improve two coarray error messages (#129597)
Two messages that complain about local variables mention that they don't
have the SAVE attribute; in both cases, it would be okay if they were
ALLOCATABLE instead. Clarify the messages.
Commit: edb7292a511171fb1fe75f85fc85464b91130a8f
https://github.com/llvm/llvm-project/commit/edb7292a511171fb1fe75f85fc85464b91130a8f
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/include/mlir/IR/OperationSupport.h
M mlir/lib/IR/AsmPrinter.cpp
M mlir/unittests/IR/OperationSupportTest.cpp
Log Message:
-----------
[mlir] Add use nameloc to OpPrintingFlags (#129584)
Commit: cb4f24b0e5c4e7c463e59120af4f13ab81519047
https://github.com/llvm/llvm-project/commit/cb4f24b0e5c4e7c463e59120af4f13ab81519047
Author: TatWai Chong <tatwai.chong at arm.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Dialect/Tosa/level_check.mlir
Log Message:
-----------
Revert "[mlir][tosa] Add several level checks" (#129602)
Reverts llvm/llvm-project#129580
There is a lit test failure reported in
https://lab.llvm.org/buildbot/#/builders/116/builds/11023
Commit: e1fd681837b85563e186f3739623cfa6653a722c
https://github.com/llvm/llvm-project/commit/e1fd681837b85563e186f3739623cfa6653a722c
Author: Douglas Gliner <Douglas.Gliner at sony.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticIDs.h
Log Message:
-----------
Bump DIAG_SIZE_LEX since we've hit the limit downstream as of 1c4e0f6.
Commit: 829401fe3ca1486285f5ef32865d189747a91305
https://github.com/llvm/llvm-project/commit/829401fe3ca1486285f5ef32865d189747a91305
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
A llvm/docs/CIBestPractices.rst
M llvm/docs/Reference.rst
Log Message:
-----------
[Github][Docs] Add CI Best Practices Docs (#129462)
This is something that Tom and I have discussed briefly for a while now,
a doc that lists out all of the best practices we want to adhere to
surrounding CI things along with their associated motivations/any other
relevant info. This patch adds that doc along with three best practices
surrounding Github Workflows that we try and adhere to (although more
work needs to be done to get 100% adherance).
Commit: ee09df8e73d8575542283d8cfe351764af290f96
https://github.com/llvm/llvm-project/commit/ee09df8e73d8575542283d8cfe351764af290f96
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M mlir/include/mlir/Dialect/Affine/Passes.td
M mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp
M mlir/test/Dialect/Affine/affine-data-copy.mlir
M mlir/test/Dialect/Affine/dma-generate.mlir
Log Message:
-----------
[MLIR][Affine] Switch default option for affine data copy generate pass (#129445)
The more common use of this pass for testing and other purposes is the
pointwise copy generation as opposed to DMA generation. Switch the
default pass option to pointwise copy generation for easier testing. NFC
otherwise.
Users who were relying on `generate-dma` to be on by default will have
to pass it explicitly: `-affine-data-copy-generate='generate-dma=1'`.
Commit: b44fbdee00bbead186baf4109ea7ca440bd8a0b3
https://github.com/llvm/llvm-project/commit/b44fbdee00bbead186baf4109ea7ca440bd8a0b3
Author: Petr Penzin <penzin.dev at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
M llvm/test/CodeGen/RISCV/features-info.ll
Log Message:
-----------
[RISCV] Tune flag for fast vrgather.vv (#124664)
Add tune knob for N*Log2(N) vrgather.vv cost.
Commit: a59b17c8adde34e26b0f101fc2942637b945e1e5
https://github.com/llvm/llvm-project/commit/a59b17c8adde34e26b0f101fc2942637b945e1e5
Author: Derek Schuff <dschuff at chromium.org>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M lld/test/wasm/emit-relocs.s
M lld/wasm/InputChunks.cpp
M lld/wasm/InputChunks.h
M lld/wasm/OutputSections.cpp
M lld/wasm/OutputSections.h
M lld/wasm/Symbols.cpp
Log Message:
-----------
[lld][WebAssembly] Do not emit relocs against dead symbols (#129346)
When emitting relocs with linked output (i.e. --emit-relocs)
skip relocs against dead symbols (which do not appear in the output)
and do not emit them.
Commit: cf05b6e25ac8dcbf6e0ea1524d86bc6d190bf8c0
https://github.com/llvm/llvm-project/commit/cf05b6e25ac8dcbf6e0ea1524d86bc6d190bf8c0
Author: JaydeepChauhan14 <chauhan.jaydeep.ashwinbhai at intel.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrFragments.td
M llvm/lib/Target/X86/X86InstrOperands.td
A llvm/test/CodeGen/X86/lea-16bit.ll
A llvm/test/CodeGen/X86/lea-8bit.ll
M llvm/utils/TableGen/X86RecognizableInstr.cpp
Log Message:
-----------
[X86] Added support for 8 and 16bit LEA instructions (#122102)
Commit: 4bd34273210329047a7829f1ea4f54c171000c68
https://github.com/llvm/llvm-project/commit/4bd34273210329047a7829f1ea4f54c171000c68
Author: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M llvm/include/llvm/IR/IRBuilder.h
Log Message:
-----------
IRBuilder: Add FMFSource parameter to CreateMaxNum/CreateMinNum (#129173)
In https://github.com/llvm/llvm-project/pull/112852, we claimed that
llvm.minnum and llvm.maxnum should treat +0.0>-0.0, while libc doesn't
require fmin(3)/fmax(3) for it.
Let's add FMFSource parameter to CreateMaxNum and CreateMinNum, so that
they can be used by CodeGenFunction::EmitBuiltinExpr of Clang.
Commit: c1aebd495be0e468044f716a3a0ff98fccccb2be
https://github.com/llvm/llvm-project/commit/c1aebd495be0e468044f716a3a0ff98fccccb2be
Author: Victor Mustya <victor.mustya at intel.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/Headers/opencl-c.h
Log Message:
-----------
[Clang][OpenCL] Wrap image functions with the macro (#129177)
According to the OpenCL C spec, the image functions are optional.
For OpenCL C 1.2, the image functions are guarded by the
`__IMAGE_SUPPORT__` macro. For the OpenCL C 3.0 and later, the
`__opencl_c_images` macro is used.
Commit: 6041c745f32e8fd60ed24e29e7d919d8d1c87ca6
https://github.com/llvm/llvm-project/commit/6041c745f32e8fd60ed24e29e7d919d8d1c87ca6
Author: Augusto Noronha <anoronha at apple.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M lldb/include/lldb/Host/macosx/HostInfoMacOSX.h
M lldb/include/lldb/Utility/XcodeSDK.h
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Utility/XcodeSDK.cpp
M lldb/unittests/SymbolFile/DWARF/XcodeSDKModuleTests.cpp
M lldb/unittests/Utility/XcodeSDKTest.cpp
Log Message:
-----------
Revert "[lldb][HostInfoMacOSX] Try to use DW_AT_LLVM_sysroot instead of xcrun when looking up SDK" (#129621)
Reverts llvm/llvm-project#128712
```
******************** TEST 'lldb-unit :: SymbolFile/DWARF/./SymbolFileDWARFTests/10/14' FAILED ********************
Script(shard):
--
GTEST_OUTPUT=json:/Users/ec2-user/jenkins/workspace/llvm.org/as-lldb-cmake/lldb-build/tools/lldb/unittests/SymbolFile/DWARF/./SymbolFileDWARFTests-lldb-unit-1021-10-14.json GTEST_SHUFFLE=1 GTEST_TOTAL_SHARDS=14 GTEST_SHARD_INDEX=10 GTEST_RANDOM_SEED=62233 /Users/ec2-user/jenkins/workspace/llvm.org/as-lldb-cmake/lldb-build/tools/lldb/unittests/SymbolFile/DWARF/./SymbolFileDWARFTests
--
Script:
--
/Users/ec2-user/jenkins/workspace/llvm.org/as-lldb-cmake/lldb-build/tools/lldb/unittests/SymbolFile/DWARF/./SymbolFileDWARFTests --gtest_filter=SDKPathParsingTests/SDKPathParsingMultiparamTests.TestSDKPathFromDebugInfo/6
--
/Users/ec2-user/jenkins/workspace/llvm.org/as-lldb-cmake/llvm-project/lldb/unittests/SymbolFile/DWARF/XcodeSDKModuleTests.cpp:265: Failure
Expected equality of these values:
found_mismatch
Which is: true
expect_mismatch
Which is: false
/Users/ec2-user/jenkins/workspace/llvm.org/as-lldb-cmake/llvm-project/lldb/unittests/SymbolFile/DWARF/XcodeSDKModuleTests.cpp:265
Expected equality of these values:
found_mismatch
Which is: true
expect_mismatch
Which is: false
```
Commit: d654d37c86a4f0dc99c65cbef0624b5533ed724c
https://github.com/llvm/llvm-project/commit/d654d37c86a4f0dc99c65cbef0624b5533ed724c
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M lldb/test/API/tools/lldb-dap/breakpoint-events/TestDAP_breakpointEvents.py
M lldb/tools/lldb-dap/Handler/InitializeRequestHandler.cpp
Log Message:
-----------
[lldb-dap] Correctly report breakpoints as resolved on macOS (#129589)
On macOS, breakpoints are briefly unresolved between process launch and
when the dynamic loader has informed us about the loaded libraries. This
information was being forwarded by lldb-dap, but only partially. In the
event handler, we were listening for the `LocationsAdded` and
`LocationsRemoved` breakpoint events. For the scenario described above,
the latter would trigger and we'd send an event reporting the breakpoint
as unresolved. The problem is that when the breakpoint location is
resolved again, you receive a `LocationsResolved` event, not a
`LocationsAdded` event. As a result, the breakpoint would continue to
show up as unresolved in the DAP client.
I found a test that tried to test part of this behavior, but the test
was broken and disabled. I revived the test and added coverage for the
situation described above.
Fixes #112629
rdar://137968318
Commit: 5bf1f03d1fb4fd4c16029355d5814ebce61ed939
https://github.com/llvm/llvm-project/commit/5bf1f03d1fb4fd4c16029355d5814ebce61ed939
Author: A. Jiang <de34 at live.cn>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M libcxx/include/__vector/vector.h
M libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_range.pass.cpp
Log Message:
-----------
[libc++] Fix assignment in insertion into `vector` (#116001)
Changes:
- Avoid direct assignment in iterator-pair `insert` overload and
`insert_range`, except when the assignment is move assignment.
Commit: f44fb56f62aafff93cd337d8818ead0ad7794d35
https://github.com/llvm/llvm-project/commit/f44fb56f62aafff93cd337d8818ead0ad7794d35
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M flang-rt/cmake/modules/AddFlangRTOffload.cmake
Log Message:
-----------
[flang-rt] Set CUDA_SEPARABLE_COMPILATION for PTX library. (#129563)
`CUDA_SEPARABLE_COMPILATION` adds `-rdc=true`, which is needed
for the PTX library build.
Commit: f57756a6406f93b3f579ce4da2b8be3fe211952f
https://github.com/llvm/llvm-project/commit/f57756a6406f93b3f579ce4da2b8be3fe211952f
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M flang/include/flang/Common/erfc-scaled.h
Log Message:
-----------
[flang-rt] Use RT_API_ATTRS for ErfcScaled. (#129598)
As long as it is a host-only function, it cannot be referenced
by the flang-rt's ErfcScaled entry points. With the markup in place,
it is compiling properly by a CUDA compiler.
Commit: bf9bf291a3174a3c7b50ec37ddf5782767827c61
https://github.com/llvm/llvm-project/commit/bf9bf291a3174a3c7b50ec37ddf5782767827c61
Author: A. Jiang <de34 at live.cn>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M libcxx/include/__algorithm/stable_partition.h
M libcxx/include/algorithm
M libcxx/test/std/algorithms/alg.modifying.operations/alg.partitions/stable_partition.pass.cpp
M libcxx/test/std/algorithms/robust_against_proxy_iterators_lifetime_bugs.pass.cpp
M libcxx/test/std/algorithms/robust_re_difference_type.compile.pass.cpp
Log Message:
-----------
[libc++] Implement part of P2562R1: constexpr `std::stable_partition` (#128868)
Drive-by changes:
- Enables no-memory case for Clang.
- Enables `robust_re_difference_type.compile.pass.cpp` and
`robust_against_proxy_iterators_lifetime_bugs.pass.cpp` test coverage
for `std::stable_sort` in constant evaluation since C++26. The changes
were missing in the PR making `std::stable_sort` `constexpr`.
Commit: 3963d2148292145543cf83b13ff839a63995fdc2
https://github.com/llvm/llvm-project/commit/3963d2148292145543cf83b13ff839a63995fdc2
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/test/CodeGen/AMDGPU/machine-sink-cycle.mir
Log Message:
-----------
[MachineSink] Fix typo in loop sinking (#127133)
Failure to sink a candidate should not block us from attempting to sink
other candidates. There are mechanisms in place to handle the case where
the failed to be sunk instruction uses an instruction that gets sunk (we
do not delete the original instruction corresponding with the sunk
instruction if it still has uses).
Commit: f38ce27c13760d166fda41dbb0ad815f40e4e874
https://github.com/llvm/llvm-project/commit/f38ce27c13760d166fda41dbb0ad815f40e4e874
Author: Jie Fu <jiefu at tencent.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Log Message:
-----------
[X86] Fix an unused variable warning (NFC)
/llvm-project/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:3090:7:
error: unused variable 'IndexType' [-Werror,-Wunused-variable]
EVT IndexType = Index.getValueType();
^
1 error generated.
Commit: 415f89905fa04bdee2f0f5a8886706756699d06e
https://github.com/llvm/llvm-project/commit/415f89905fa04bdee2f0f5a8886706756699d06e
Author: Daniel Zabawa <daniel.zabawa at intel.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc.ll
Log Message:
-----------
[X86] Remove single-use checks when combining xor and vfmulc/vcfmulc. (#128910)
The current implementation to combine xor patterns for conjugation with
complex multiplies will not perform the transformation when either the
conjugate xor result or other multiplicand have other uses. This change
eliminates both single-use checks.
The transformation will eliminate the xor dependence and hence should be
profitable even if the conjugate is used elsewhere - and more profitable
if the xor is used in multiple fmulc/fcmulc instructions, eventually
going dead.
The check of the other multiplicand isn't required for correctness and
has no apparent performance implications.
Commit: 0ed2945a596991b75e4ca090fe04240abba6012b
https://github.com/llvm/llvm-project/commit/0ed2945a596991b75e4ca090fe04240abba6012b
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/Format/Format.cpp
M clang/unittests/Format/SortIncludesTest.cpp
Log Message:
-----------
[clang-format] Don't sort includes for C# (#129369)
Fixes #106194
Commit: 136f2574ddfe81e73376ada0ea299b67170caf2c
https://github.com/llvm/llvm-project/commit/136f2574ddfe81e73376ada0ea299b67170caf2c
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/Format/Format.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Lex C++ only keywords as identifiers in C (#129426)
Fix #128847
Commit: 2ca085505996ca16cc79090dbc66d06ac46ed262
https://github.com/llvm/llvm-project/commit/2ca085505996ca16cc79090dbc66d06ac46ed262
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Fix a bug in wrapping function return type (#129374)
Fixes #113766
Commit: 956e56fa6d3d62e1ef1a27bdc9f6be3c0544b9c7
https://github.com/llvm/llvm-project/commit/956e56fa6d3d62e1ef1a27bdc9f6be3c0544b9c7
Author: TatWai Chong <tatwai.chong at arm.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Dialect/Tosa/level_check.mlir
Log Message:
-----------
[mlir][tosa] Add several level checks (#129580) (#129613)
Add the following types of level check to consolidate the level validity
- Complete rank level checks for operations.
- Add MAX_LOG2_SIZE level check: The maximum value is 63 when the
level is set to "none" and 31 when the level is set to "8K".
- Add MAX_TENSOR_LIST_SIZE level check : The maximum value is 256
when the level is set to "none" and 64 when the level is set to "8K".
- TOSA 1.0 spec does not allow operations with dynamic shapes, so an
error should be raised instead.
Co-authored-by: Tai Ly <tai.ly at arm.com>
Commit: ce1a18e2c714f39fe72cd46aa04faed29ad23cb6
https://github.com/llvm/llvm-project/commit/ce1a18e2c714f39fe72cd46aa04faed29ad23cb6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/tools/c-index-test/c-index-test.c
Log Message:
-----------
clang-tools: Fix sprintf is deprecated warnings (#120517)
Commit: 8476a5d480304bf7bd934c660a159e1c6906a69d
https://github.com/llvm/llvm-project/commit/8476a5d480304bf7bd934c660a159e1c6906a69d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/lib/CodeGen/SplitKit.h
A llvm/test/CodeGen/AMDGPU/splitkit-do-not-undo-subclass-split-with-remat.mir
M llvm/test/CodeGen/X86/eq-or-eq-range-of-2.ll
M llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll
M llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll
M llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
Log Message:
-----------
SplitKit: Fix rematerialization undoing subclass based split (#122110)
This fixes an allocation failure in the new test.
In cases where getLargestLegalSuperClass can inflate the register class,
rematerialization could effectively undo a split which was done to
inflate
the register class, if the defining instruction can only write a
subclass
and the use can read the superclass.
Some of the x86 tests changes look like improvements, but some are
likely regressions.
I'm not entirely sure this is the correct place to fix this. It also
seems more complicated than necessary, but the decision to change
the register class is far removed from the point where the decision
to split the virtual register is made. I'm also also not sure if this
should be considering the register classes of all the use indexes
in getUseSlots, rather than just checking if this use index instruction
reads the register.
Commit: 12b38c3e39512344b9c951406c5023b8a5549182
https://github.com/llvm/llvm-project/commit/12b38c3e39512344b9c951406c5023b8a5549182
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
Log Message:
-----------
TableGen: Fix comment typo
Commit: 4670f0d8275a7eacfba46a17d88d3e2d947f5a61
https://github.com/llvm/llvm-project/commit/4670f0d8275a7eacfba46a17d88d3e2d947f5a61
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
Log Message:
-----------
MachineVerifier: Print name of failing subregister index (#129491)
I'm not sure of a good example to test the "does not fully support"
case.
Commit: 50ff49ebbcdc88301070e94b04cb158d040db276
https://github.com/llvm/llvm-project/commit/50ff49ebbcdc88301070e94b04cb158d040db276
Author: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
Log Message:
-----------
Clang: ExprConstant use maxnum/minnum for fmax/fmin (#129630)
In APFloat, we have defined maxnum and minnum, so let's use them
directly here.
In `maxnum`/`minnum` of APFloat, we process sNaN, signed-zero as
strictly as possible.
Commit: 3aab3fe56fbd60b49a47ae0f90d96de2cd09fc18
https://github.com/llvm/llvm-project/commit/3aab3fe56fbd60b49a47ae0f90d96de2cd09fc18
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/include/llvm/IR/Analysis.h
M llvm/lib/CodeGen/MachineScheduler.cpp
Log Message:
-----------
[NPM][NFC] Chain PreservedAnalyses methods (#129505)
Commit: 82d111e8202328d3a04d923cdae19ad29bc79dbc
https://github.com/llvm/llvm-project/commit/82d111e8202328d3a04d923cdae19ad29bc79dbc
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
Log Message:
-----------
[clang][bytecode][NFC] Minor cleanups (#129553)
Pull local variables in to the closest scope, remove some unnecessary
calls to getLocation() and remove an outdated comment.
Commit: 6c87ec4f4d083a85ebcfbbda166ad4ba41d5da8d
https://github.com/llvm/llvm-project/commit/6c87ec4f4d083a85ebcfbbda166ad4ba41d5da8d
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIModeRegister.cpp
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
M llvm/test/CodeGen/AMDGPU/mode-register.mir
Log Message:
-----------
[AMDGPU][NPM] Port SIModeRegister to NPM (#129014)
Commit: af4ec59f8d2ec127425ed45c0ff67c51679f99ad
https://github.com/llvm/llvm-project/commit/af4ec59f8d2ec127425ed45c0ff67c51679f99ad
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
A llvm/include/llvm/CodeGen/ExpandPostRAPseudos.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/AArch64/seqpaircopy.mir
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
M llvm/test/CodeGen/SystemZ/copy-phys-reg-gr64-to-fp64.mir
Log Message:
-----------
[CodeGen][NPM] Port ExpandPostRAPseudos to NPM (#129509)
Commit: e9fe95acf3b9ead924a6f059c8ca8a8aabc55575
https://github.com/llvm/llvm-project/commit/e9fe95acf3b9ead924a6f059c8ca8a8aabc55575
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
Log Message:
-----------
[clang][bytecode][NFC] Use maxnum/minnum for fmax/fmin (#129643)
Equivalent of https://github.com/llvm/llvm-project/pull/129630 for the
bytecode interpreter.
Commit: 41473162fd886d7db548fb288cf3620570f73c17
https://github.com/llvm/llvm-project/commit/41473162fd886d7db548fb288cf3620570f73c17
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/include/llvm/CodeGen/RegAllocGreedyPass.h
Log Message:
-----------
[CodeGen][NPM]RAGreedy: Put up include guard in the header (#129510)
Commit: 4fb31e44017bd9ad914fc4c814fbaa60cc18d5b4
https://github.com/llvm/llvm-project/commit/4fb31e44017bd9ad914fc4c814fbaa60cc18d5b4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Log Message:
-----------
AMDGPU: Use const reference for DebugLoc
Commit: b3d5056c79b5496fc8751630ddd0ac0071cab0af
https://github.com/llvm/llvm-project/commit/b3d5056c79b5496fc8751630ddd0ac0071cab0af
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/acc-ldst.ll
A llvm/test/CodeGen/AMDGPU/coalesces-better.mir
A llvm/test/CodeGen/AMDGPU/coalesces-worse.mir
M llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
M llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll
M llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
Log Message:
-----------
AMDGPU: Try to perform copy to agpr from reg_sequence at the copy (#129463)
SIFoldOperands is frustratingly written in a def-folds-into-use
iteration pattern, with a few random cases starting at the uses.
We were handling this case by looking at the reg_sequence, and finding
the copy. This did not work for the most basic pattern of materializing
a vector constant that started in SGPRs. It just happens there is an
optimization bug in SelectionDAG that produced the expected pattern.
Perform an additional attempt at the fold rooted at the copy. This
mostly shows test improvements. There were some tricky updates to
perform. remaining-virtual-register-operands.ll managed to stop failing
the allocator, so needed to be tricked into failing again. I also do
not understand what schedule-xdl-resource.ll is trying to do for the test
so this changes it to some random output that exists in the debug output.
Commit: 39bf765bb671fa7df3fe6c164cc9532fcb8653bd
https://github.com/llvm/llvm-project/commit/39bf765bb671fa7df3fe6c164cc9532fcb8653bd
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nondeterminism.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mmra.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
Log Message:
-----------
DAG: Use phi to create vregs instead of the constant input (#129464)
For most targets, the register class comes from the type so this
makes no difference. For AMDGPU, the selected register class depends
on the divergence of the value. For a constant phi input, this will
always be false. The heuristic for whether to treat the value as
a scalar or vector constant based on the uses would then incorrectly
think this is a scalar use, when really the phi is a copy from S to V.
This avoids an intermediate s_mov_b32 plus a copy in some cases. These
would often, but not always, fold out in mi passes.
This only adjusts the constant input case. It may make sense to do
this for the non-constant case as well.
Commit: 9084d2a0a11d8e12ac02f8870c418073985c2e59
https://github.com/llvm/llvm-project/commit/9084d2a0a11d8e12ac02f8870c418073985c2e59
Author: Dmitri Gribenko <gribozavr at gmail.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M libc/src/stdlib/qsort_pivot.h
Log Message:
-----------
[libc] Add a missing include
This is a fixup for
https://github.com/llvm/llvm-project/commit/da6d5fa79a558b66c281bed3f5ce848a69a65208.
Commit: 2127af80fa46709a563ad7ecc400209f1640f96e
https://github.com/llvm/llvm-project/commit/2127af80fa46709a563ad7ecc400209f1640f96e
Author: Alexander Shaposhnikov <ashaposhnikov at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M compiler-rt/test/ubsan/TestCases/Float/cast-overflow.cpp
Log Message:
-----------
[compiler-rt][ubsa] Reformat cast-overflow test. NFC (#129662)
Reformat cast-overflow test. NFC
Commit: a5bbfcf0c9dd48e13951fdb35362e2e3d545dbad
https://github.com/llvm/llvm-project/commit/a5bbfcf0c9dd48e13951fdb35362e2e3d545dbad
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
Log Message:
-----------
[GlobalISel] Avoid repeated hash lookups (NFC) (#129653)
Commit: c61c88862805905dfa8a2c2f8c9f8ef7e1874720
https://github.com/llvm/llvm-project/commit/c61c88862805905dfa8a2c2f8c9f8ef7e1874720
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/tools/llvm-mca/CodeRegion.cpp
Log Message:
-----------
[llvm-mca] Avoid repeated hash lookups (NFC) (#129656)
Commit: a619a2e53a9ba09ba18a047b8389bf4dd1912b72
https://github.com/llvm/llvm-project/commit/a619a2e53a9ba09ba18a047b8389bf4dd1912b72
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
A clang/test/CodeGen/arm-neon-endianness.c
M clang/utils/TableGen/NeonEmitter.cpp
Log Message:
-----------
[ARM] Fix lane ordering for AdvSIMD intrinsics on big-endian targets (#127068)
In arm-neon.h, we insert shufflevectors around each intrinsic when the
target is big-endian, to compensate for the difference between the
ABI-defined memory format of vectors (with the whole vector stored as
one big-endian access) and LLVM's target-independent expectations (with
the lowest-numbered lane in the lowest address). However, this code was
written for the AArch64 ABI, and the AArch32 ABI differs slightly: it
requires that vectors are stored in memory as-if stored with VSTM, which
does a series of 64-bit accesses, instead of the AArch64 VSTR, which
does a single 128-bit access. This means that for AArch32 we need to
reverse the lanes in each 64-bit chunk of the vector, instead of in the
whole vector.
Since there are only a small number of different shufflevector orderings
needed, I've split them out into macros, so that this doesn't need
separate conditions in each intrinsic definition.
Commit: d6942d54f677000cf713d2b0eba57b641452beb4
https://github.com/llvm/llvm-project/commit/d6942d54f677000cf713d2b0eba57b641452beb4
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/VTableBuilder.h
M clang/include/clang/Basic/ABI.h
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/MicrosoftMangle.cpp
M clang/lib/AST/VTableBuilder.cpp
M clang/lib/CodeGen/CGCXX.cpp
M clang/lib/CodeGen/CGCXXABI.cpp
M clang/lib/CodeGen/CGCXXABI.h
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CGVTables.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/CodeGen/MicrosoftCXXABI.cpp
M clang/test/CodeGenCXX/debug-info-windows-dtor.cpp
M clang/test/CodeGenCXX/dllexport.cpp
M clang/test/CodeGenCXX/microsoft-abi-extern-template.cpp
M clang/test/CodeGenCXX/microsoft-abi-structors.cpp
M clang/test/CodeGenCXX/microsoft-abi-thunks.cpp
M clang/test/CodeGenCXX/microsoft-abi-vftables.cpp
M clang/test/CodeGenCXX/microsoft-abi-virtual-inheritance.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-multiple-nonvirtual-inheritance-vdtors.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-return-thunks.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-single-inheritance.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-virtual-inheritance-vtordisps.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-virtual-inheritance.cpp
M clang/test/CodeGenCXX/microsoft-no-rtti-data.cpp
A clang/test/CodeGenCXX/microsoft-vector-deleting-dtors.cpp
M clang/test/CodeGenCXX/vtable-consteval.cpp
M clang/test/Modules/vtable-windows.cppm
M clang/test/Profile/cxx-abc-deleting-dtor.cpp
Log Message:
-----------
[MS][clang] Add support for vector deleting destructors (#126240)
Whereas it is UB in terms of the standard to delete an array of objects
via pointer whose static type doesn't match its dynamic type, MSVC
supports an extension allowing to do it.
Aside from array deletion not working correctly in the mentioned case,
currently not having this extension implemented causes clang to generate
code that is not compatible with the code generated by MSVC, because
clang always puts scalar deleting destructor to the vftable. This PR
aims to resolve these problems.
Fixes https://github.com/llvm/llvm-project/issues/19772
Commit: aa37a698d4066058d03016ea467230bd039c1eb1
https://github.com/llvm/llvm-project/commit/aa37a698d4066058d03016ea467230bd039c1eb1
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
Log Message:
-----------
[LoopInterchange] Move some processes to another function (NFC) (#129514)
Some post-processing involved in exchanging a pair of loops has been
done separately from `processLoop`, which is a main function that does
the transformation. It's better to consolidate these processes into the
same function. This patch is a preparation of #127474.
Commit: 15770a1e9d0983ee59a8850f2ddd7b57e46dcc5a
https://github.com/llvm/llvm-project/commit/15770a1e9d0983ee59a8850f2ddd7b57e46dcc5a
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Remove dead recipes in entry when merging regions. (NFC)
Also remove recipes in the entry of the region that will be removed.
This makes sure we don't leave any dead users around. NFC at the moment,
but avoids causing issues in the future.
Commit: 23a30e68888e764b2f4d32e51d415b50fa5f5cac
https://github.com/llvm/llvm-project/commit/23a30e68888e764b2f4d32e51d415b50fa5f5cac
Author: Alexander Shaposhnikov <ashaposhnikov at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M compiler-rt/lib/ubsan/ubsan_value.cpp
M compiler-rt/test/ubsan/TestCases/Float/cast-overflow.cpp
Log Message:
-----------
[compiler-rt][ubsan] Add support for f16 (#129624)
LLVM supports long double <-> f16 conversions so we can remove the old FIXME.
Commit: 80bdfcd411cd8197b0a8b6139b89a87d3a4528fa
https://github.com/llvm/llvm-project/commit/80bdfcd411cd8197b0a8b6139b89a87d3a4528fa
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_estimated_tc.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_memcheck_cost.ll
Log Message:
-----------
[LoopUtils] Don't wrap in getLoopEstimatedTripCount (#129080)
getLoopEstimatedTripCount returns the trip count based on profiling
data, and its documentation says that it could return 0 when the trip
count is zero, but this is not the case: a valid trip count can never be
zero, and it returns 0 when the unsigned ExitCount is incremented by 1
and wraps. Some callers are careful about checking for this zero value
in an std::optional, but it makes for an API with footguns, as a
std::optional return value indicates that a non-nullopt value would be a
valid trip count. Fix this by explicitly returning std::nullopt when the
return value would wrap, and strip additional checks in callers. This
also fixes a minor bug in LoopVectorize.
Commit: 8266cd9f84b5a7d334ade7ff41393458b3789047
https://github.com/llvm/llvm-project/commit/8266cd9f84b5a7d334ade7ff41393458b3789047
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang-tools-extra/clangd/TidyProvider.cpp
M clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp
Log Message:
-----------
[clangd] Disable cppcoreguidelines-macro-to-enum clang-tidy checker (#129478)
Clangd does not support its checker because the checker relies on having
seen preprocessor conditionals that occur in the preamble, and clangd
does not currently replay those.
This checker was already disabled under its main name,
modernize-macro-to-enum (https://github.com/clangd/clangd/issues/1464).
This commit disables it under the alternative name
cppcoreguidelines-macro-to-enum as well.
Fixes https://github.com/llvm/llvm-project/issues/127965
Commit: 47fb9c4bb9b057ab45c5228937a2c1fbf51c4f72
https://github.com/llvm/llvm-project/commit/47fb9c4bb9b057ab45c5228937a2c1fbf51c4f72
Author: Luke Lau <luke at igalia.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanHCFGBuilder.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Add Name argument to VPWidenPHIRecipe. NFC (#129527)
This allows a different IR name for the generated phi to be used. This
is split off from #118638 and helps remove some of the diffs in it.
Commit: 03505a004ff6909c46d6b8c498a9ffccd47d88a0
https://github.com/llvm/llvm-project/commit/03505a004ff6909c46d6b8c498a9ffccd47d88a0
Author: Jim Lin <jim at andestech.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll
Log Message:
-----------
[RISCV] Enable scalable loop vectorization for fmax/fmin reductions with f16/bf16 type for zvfhmin/zvfbfmin (#129629)
This PR enable scalable loop vectorization for fmax and fmin reductions
with f16/bf16 type when only zvfhmin/zvfbfmin are enabled.
After https://github.com/llvm/llvm-project/pull/128800, we can promote
the fmax/fmin reductions with f16/bf16 type to f32 reductions for
zvfhmin/zvfbfmin.
Commit: 0eaca0412501da82d7f23811003f64624e17cba6
https://github.com/llvm/llvm-project/commit/0eaca0412501da82d7f23811003f64624e17cba6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Log Message:
-----------
AMDGPU: Remove repeated define in base info header
The identical define is repeated on the previous line.
Commit: b7f31044f34036d277f5c6e21ef3a126b5972508
https://github.com/llvm/llvm-project/commit/b7f31044f34036d277f5c6e21ef3a126b5972508
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/test/Transforms/GVN/opt-remarks.ll
Log Message:
-----------
[GVN][NFC] Remove unnecessary assembly output from test (#129670)
This test doesn't check any output from opt, so it can be safely
`disable-output` and thus less redirections.
Commit: a32d5438ac50ef509af9e688f9cd93f1e98d929d
https://github.com/llvm/llvm-project/commit/a32d5438ac50ef509af9e688f9cd93f1e98d929d
Author: Alexander Shaposhnikov <ashaposhnikov at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M compiler-rt/lib/ubsan/ubsan_value.cpp
M compiler-rt/test/ubsan/TestCases/Float/cast-overflow.cpp
Log Message:
-----------
Revert "[compiler-rt][ubsan] Add support for f16 (#129624)"
This reverts commit 23a30e68888e764b2f4d32e51d415b50fa5f5cac.
The commit has broken some build bots.
Commit: 2bef21f24ba932a757a644470358c340f4bcd113
https://github.com/llvm/llvm-project/commit/2bef21f24ba932a757a644470358c340f4bcd113
Author: James Chesterman <James.Chesterman at arm.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
Log Message:
-----------
[DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (#127083)
Add generic DAG combine for ISD::PARTIAL_REDUCE_U/SMLA nodes. Transforms
the DAG from:
PARTIAL_REDUCE_MLA(Acc, MUL(EXT(MulOpLHS), EXT(MulOpRHS)), Splat(1)) to
PARTIAL_REDUCE_MLA(Acc, MulOpLHS, MulOpRHS).
Commit: 7c8b1275bc87f6b5983788a6e603504725b490c9
https://github.com/llvm/llvm-project/commit/7c8b1275bc87f6b5983788a6e603504725b490c9
Author: Nathan Gauër <brioche at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/SPIRV.h
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
A llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
A llvm/test/CodeGen/SPIRV/pointers/array-skips-gep.ll
A llvm/test/CodeGen/SPIRV/pointers/getelementptr-downcast-vector.ll
Log Message:
-----------
[SPIR-V] Add pass to remove spv_ptrcast intrinsics (#128896)
OpenCL is allowed to cast pointers, meaning they can resolve some type
mismatches this way. In logical SPIR-V, those are restricted. This new
pass legalizes such pointer cast when targeting logical SPIR-V.
For now, this pass supports 3 cases we witnessed:
- loading a vec3 from a vec4*.
- loading a scalar from a vec*.
- loading the 1st element of an array.
---------
Co-authored-by: Steven Perron <stevenperron at google.com>
Commit: 7a06681398a33d53ba6d661777be8b4c1d19acb7
https://github.com/llvm/llvm-project/commit/7a06681398a33d53ba6d661777be8b4c1d19acb7
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
Log Message:
-----------
Revert "[DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (#127083)"
This reverts commit 2bef21f24ba932a757a644470358c340f4bcd113.
Multiple builtbot failures have been reported:
https://github.com/llvm/llvm-project/pull/127083
Commit: ef94d8a0f2d885d1753cd39c1ea76fe21a69d93b
https://github.com/llvm/llvm-project/commit/ef94d8a0f2d885d1753cd39c1ea76fe21a69d93b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
Log Message:
-----------
[CodeGen] Avoid repeated hash lookups (NFC) (#129652)
Commit: 9372d1d72ab287d5121ca1961dd416cf51224e62
https://github.com/llvm/llvm-project/commit/9372d1d72ab287d5121ca1961dd416cf51224e62
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
Log Message:
-----------
[TableGen] Avoid repeated hash lookups (NFC) (#129655)
Commit: 65330e20b189c38ddbb38eb63b15f93262385e73
https://github.com/llvm/llvm-project/commit/65330e20b189c38ddbb38eb63b15f93262385e73
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/tools/llvm-readobj/COFFDumper.cpp
Log Message:
-----------
[llvm-readobj] Avoid repeated hash lookups (NFC) (#129657)
Commit: f319a6546613d65661e1ad1ef1a2a648cefee84b
https://github.com/llvm/llvm-project/commit/f319a6546613d65661e1ad1ef1a2a648cefee84b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
Log Message:
-----------
AMDGPU: Fix broken broken negative test for gfx950 assembler (#129667)
Fix's not rejecting global_load_lds_dwordx3 and x4 on other targets.
The encoded versions of instructions should not touch SubtargetPredicate,
and only AssemblerPredicate.
Commit: 45901ccfcc528849a7079319f1b8ee26939202f0
https://github.com/llvm/llvm-project/commit/45901ccfcc528849a7079319f1b8ee26939202f0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/FLATInstructions.td
Log Message:
-----------
AMDGPU: Remove some overrides of SubtargetPredicate on real instructions (#129668)
AssemblerPredicate is the hack to use for cases where the encoding
change doesn't nicely line up with the subtarget predicate.
Commit: e187fc0ff780c2f6a8e495f9a5d70fbac2341b3b
https://github.com/llvm/llvm-project/commit/e187fc0ff780c2f6a8e495f9a5d70fbac2341b3b
Author: Adam Siemieniuk <adam.siemieniuk at intel.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M mlir/docs/Dialects/Linalg/_index.md
M mlir/include/mlir/Dialect/Linalg/IR/LinalgDoc.td
Log Message:
-----------
[mlir][linalg] Fix linalg.pack/unpack docs (#129559)
Adds missing relayout ops to Linalg docs tablegen.
Follow-up to #127729
Commit: d0eeeab5575d88498149a66096fda2815c132e3a
https://github.com/llvm/llvm-project/commit/d0eeeab5575d88498149a66096fda2815c132e3a
Author: Sushant Gokhale <sgokhale at nvidia.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
Log Message:
-----------
[NFC] test for usdot with multiple zext users (#129650)
Currently, usdot is not being generated in loop when zext has multiple. Subsequent patch will improve
this.
Commit: 0fcbf148df9c6d4f1a12eed356697cda665852e5
https://github.com/llvm/llvm-project/commit/0fcbf148df9c6d4f1a12eed356697cda665852e5
Author: AnastasiyaChernikova <anastasiya.chernikova at syntacore.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
A llvm/test/tools/llvm-exegesis/RISCV/latency-by-load.s
M llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp
Log Message:
-----------
[Exegesis] Implemented strategy for load operation (#113458)
This fix helps to map operand memory to destination registers. If
instruction is load, we can self-alias it in case when instruction
overrides whole address register. For that we use provided scratch
memory.
Commit: e0eb4edad66b3ea3c621c8c9f3298f2d64697bd7
https://github.com/llvm/llvm-project/commit/e0eb4edad66b3ea3c621c8c9f3298f2d64697bd7
Author: Vikram Hegde <115221833+vikramRH at users.noreply.github.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
A llvm/include/llvm/CodeGen/FixupStatepointCallerSaved.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/X86/statepoint-fixup-call.mir
M llvm/test/CodeGen/X86/statepoint-fixup-copy-prop-neg.mir
M llvm/test/CodeGen/X86/statepoint-fixup-copy-prop.mir
M llvm/test/CodeGen/X86/statepoint-fixup-invoke.mir
M llvm/test/CodeGen/X86/statepoint-fixup-shared-ehpad.mir
M llvm/test/CodeGen/X86/statepoint-fixup-undef-def.mir
M llvm/test/CodeGen/X86/statepoint-fixup-undef.mir
Log Message:
-----------
[CodeGen][NewPM] Port "FixupStatepointCallerSaved" pass to NPM (#129541)
Commit: 77a8770d4976e086f36004a6b8bf09e76d981451
https://github.com/llvm/llvm-project/commit/77a8770d4976e086f36004a6b8bf09e76d981451
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M lldb/include/lldb/Host/macosx/HostInfoMacOSX.h
M lldb/include/lldb/Utility/XcodeSDK.h
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Utility/XcodeSDK.cpp
M lldb/unittests/SymbolFile/DWARF/XcodeSDKModuleTests.cpp
M lldb/unittests/Utility/XcodeSDKTest.cpp
Log Message:
-----------
Reland "[lldb][HostInfoMacOSX] Try to use DW_AT_LLVM_sysroot instead of xcrun when looking up SDK" (#129621)"
This reverts commit 6041c745f32e8fd60ed24e29e7d919d8d1c87ca6.
Relands the original patch with the test-case data fixed. Weirldy the PR CI
didn't seem to run the unit-tests? In any case, the problem was an
incorrect expectation in the test-case data. Since we have both public
and internal SDK in that test-case, we should `expect_mismatch` to be
`true`.
Commit: e27b8b2eda767eb59d3d605d288e733b154a48c5
https://github.com/llvm/llvm-project/commit/e27b8b2eda767eb59d3d605d288e733b154a48c5
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M flang/lib/Optimizer/Dialect/FIRType.cpp
A flang/test/Integration/debug-cyclic-derived-type-4.f90
Log Message:
-----------
[flang][debug] Improve handling of cyclic derived types with classes. (#129588)
While checking if a type should be cached or not, we use
`getDerivedType` to peel outer layers and get to the base type. This
function did not peel the `fir.class` which caused the algorithm to
fail.
Fixes #128606.
Commit: 680391f07a45272bb9bfd385cf4c6846b8be32dd
https://github.com/llvm/llvm-project/commit/680391f07a45272bb9bfd385cf4c6846b8be32dd
Author: Discookie <viktor.cseh at ericsson.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/Analysis/FlowSensitive/Transfer.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
Log Message:
-----------
[clang][dataflow] Fix unsupported types always being equal (#129502)
Previously when the framework encountered unsupported values (such as
enum classes), they were always treated as equal when comparing with
`==`, regardless of their actual values being different.
Now the two sides are only equal if there's a Value assigned to them.
Added a Value assignment for `nullptr`, to handle the special case of
`nullptr == nullptr`.
Commit: c7dbf20e66606e7e26a28ad567ff75f3a493d3bd
https://github.com/llvm/llvm-project/commit/c7dbf20e66606e7e26a28ad567ff75f3a493d3bd
Author: Da-Viper <57949090+Da-Viper at users.noreply.github.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M lldb/test/API/tools/lldb-dap/variables/children/TestDAP_variables_children.py
Log Message:
-----------
[lldb-dap] Test: disable children return test for all arm architectures (#129409)
amd64 and aarch64 are treated differently
Follows up #106907
Commit: e3c8e17b073bf38e900014ed47230882c407dab8
https://github.com/llvm/llvm-project/commit/e3c8e17b073bf38e900014ed47230882c407dab8
Author: James Chesterman <james.chesterman at arm.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
Log Message:
-----------
Reland "[DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (#127083)"
This relands commit 7a06681398a33d53ba6d661777be8b4c1d19acb7.
Commit: ec54ec65e5172b624f34a801012fe471ccf5d261
https://github.com/llvm/llvm-project/commit/ec54ec65e5172b624f34a801012fe471ccf5d261
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M mlir/include/mlir/Analysis/FlatLinearValueConstraints.h
M mlir/include/mlir/Analysis/Presburger/IntegerRelation.h
M mlir/include/mlir/Dialect/Affine/Analysis/Utils.h
M mlir/lib/Analysis/FlatLinearValueConstraints.cpp
M mlir/lib/Analysis/Presburger/IntegerRelation.cpp
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/test/Dialect/Affine/dma-generate.mlir
M mlir/test/Dialect/Affine/loop-fusion-3.mlir
M mlir/test/Dialect/Affine/loop-fusion.mlir
Log Message:
-----------
[MLIR][Affine] Improve memref region bounding size and shape computation (#129009)
Improve memref region utility (`getConstantBoundingSizeAndShape`) to get
its constant bounding size and shape using affine expressions/maps by
also considering local variables in the system. Leads to significantly
precise and tighter bounding size and shape in the presence of div/mod
expressions (as evident from the test cases). The approach is now more
robust, proper, and complete. For affine fusion, this leads to private
memrefs of accurate size in several cases. This also impacts other
affine analysis-based passes like data copy generation that use memref
regions.
With contributions from `Vinayaka Bandishti <vinayaka at polymagelabs.com>`
on `getConstantBoundingSizeAndShape` and getConstantBoundOnDimSize`.
Fixes: https://github.com/llvm/llvm-project/issues/46317
Co-authored-by: Vinayaka Bandishti <vinayaka at polymagelabs.com>
Commit: 1e1781bca92c2c6ee05867702b26e88fe3227307
https://github.com/llvm/llvm-project/commit/1e1781bca92c2c6ee05867702b26e88fe3227307
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/sve-fcvt.ll
M llvm/test/CodeGen/AArch64/sve-split-fcvt.ll
Log Message:
-----------
[LLVM][SVE] Improve code generation for i1 based int_to_fp operations. (#129229)
Rather than extending the predicate we can use it directly to select
between the two possible results.
Commit: c711c65e57fe5e09b8321a675075dac9dbd12f82
https://github.com/llvm/llvm-project/commit/c711c65e57fe5e09b8321a675075dac9dbd12f82
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll
Log Message:
-----------
[X86] combineINSERT_SUBVECTOR - attempt to constant fold from constant pool loads (if we're not widening). (#129682)
Commit: da4cbeca6c5e147e7a3e19f1020befa8b119985e
https://github.com/llvm/llvm-project/commit/da4cbeca6c5e147e7a3e19f1020befa8b119985e
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/CodeGen/AArch64/sve-fcvt.ll
Log Message:
-----------
[LLVM][SVE] Implement isel for fptoi half/float/double to i1. (#129269)
Also adds an assert that SVE support for strict_fp fp<->int operations
is missing.
The added costs are to maintain the existing values expected by
Analysis/CostModel/AArch64/sve-cast.ll.
Commit: 25479a3c9c55af0f1651bf43b0ad5ec7d572ff34
https://github.com/llvm/llvm-project/commit/25479a3c9c55af0f1651bf43b0ad5ec7d572ff34
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/test/CodeGen/X86/setcc-lowering.ll
Log Message:
-----------
[X86] setcc-lowering.ll - regenerate VPTERNLOG comment
Commit: 06fc7d68ff816090ea8654a5a0240a4444a8eb6f
https://github.com/llvm/llvm-project/commit/06fc7d68ff816090ea8654a5a0240a4444a8eb6f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Descriptor.cpp
M clang/lib/AST/ByteCode/Descriptor.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Program.cpp
M clang/test/AST/ByteCode/records.cpp
Log Message:
-----------
[clang][bytecode] Don't error out on incomplete declarations (#129685)
Later operations on these are invalid, but the declaration is fine, if
extern.
Commit: 323112a38de04e4e7b8b7d8406575816f38507ac
https://github.com/llvm/llvm-project/commit/323112a38de04e4e7b8b7d8406575816f38507ac
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/sve-vector-splat.ll
Log Message:
-----------
[LLVM][SVE] Add isel for bfloat based constant splats. (#129550)
There are no dedicated bfloat MOV instructions but we can use the half
variants when the encoding allows (e.g. f16(1.875) == bf16(1.0)).
Commit: 607485f81c8bbfcf91ecb5a71a6323fb2bc367d9
https://github.com/llvm/llvm-project/commit/607485f81c8bbfcf91ecb5a71a6323fb2bc367d9
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Log Message:
-----------
[LLVM][SVE] Lower bfloat extends the same as other types. (#129544)
Commit: d9fb3cef5de1d1cd1261ae1753a578df1b9817de
https://github.com/llvm/llvm-project/commit/d9fb3cef5de1d1cd1261ae1753a578df1b9817de
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
R llvm/test/CodeGen/AMDGPU/coalesces-better.mir
R llvm/test/CodeGen/AMDGPU/coalesces-worse.mir
Log Message:
-----------
AMDGPU: Remove accidentally committed tests
Commit: 43ec9e18938930546e63db41ecda26d3de30e4ea
https://github.com/llvm/llvm-project/commit/43ec9e18938930546e63db41ecda26d3de30e4ea
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/www/cxx_status.html
Log Message:
-----------
[Clang] Mark that P2280R4 was approved as a dr in the status page
Commit: b25b38412807615d2e54702435f67b5c5b7170c0
https://github.com/llvm/llvm-project/commit/b25b38412807615d2e54702435f67b5c5b7170c0
Author: Adrian Kuegel <akuegel at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M mlir/lib/Conversion/MPIToLLVM/MPIToLLVM.cpp
Log Message:
-----------
[mlir] Apply ClangTidy finding (NFC)
prefer using 'override' or (rarely) 'final' instead of 'virtual'
Commit: 66d4294a77dc9ba7a5b94b3d3279a1e76ae026d1
https://github.com/llvm/llvm-project/commit/66d4294a77dc9ba7a5b94b3d3279a1e76ae026d1
Author: Adrian Kuegel <akuegel at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M mlir/lib/Conversion/MPIToLLVM/MPIToLLVM.cpp
Log Message:
-----------
Revert "[mlir] Apply ClangTidy finding (NFC)"
This reverts commit b25b38412807615d2e54702435f67b5c5b7170c0.
Applied the finding manually and got it wrong.
Commit: cd4c10afea7eaaf87c1830e340863f0bf8745b0b
https://github.com/llvm/llvm-project/commit/cd4c10afea7eaaf87c1830e340863f0bf8745b0b
Author: Adrian Kuegel <akuegel at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M mlir/lib/Conversion/MPIToLLVM/MPIToLLVM.cpp
Log Message:
-----------
[mlir] Apply ClangTidy finding (NFC)
prefer using 'override' or (rarely) 'final' instead of 'virtual'
second attempt
Commit: 53d433e702736f9edfee57ec2c1628c729336866
https://github.com/llvm/llvm-project/commit/53d433e702736f9edfee57ec2c1628c729336866
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/functions.cpp
Log Message:
-----------
[clang][bytecode] Only emit literal_comparison for string literals (#129691)
This is what the current interpreter does as well.
Commit: 22d8ba3dbc732fdf4acf830e741d972be282f827
https://github.com/llvm/llvm-project/commit/22d8ba3dbc732fdf4acf830e741d972be282f827
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] getConstVector - use APInt::extractBits instead of shift+mask. NFC.
Commit: b2d70e8796ab68a80567fb794079ee07bb243f6e
https://github.com/llvm/llvm-project/commit/b2d70e8796ab68a80567fb794079ee07bb243f6e
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Use Builder to create cast recipes in VPlanTransforms (NFC).
Use VPBuilder in a few more places. This avoids manual insertions and
will make changing the cast recipe easier in the future.
Commit: f838a5e96cb15f3cd70b2f26db0b520004350c7e
https://github.com/llvm/llvm-project/commit/f838a5e96cb15f3cd70b2f26db0b520004350c7e
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
[clang][bytecode] Fix diagnostic difference with opaque call cmps (#129702)
Try to dig out the call expression and diagnose this as an opaque call.
Commit: e5d5503e4efa48b61194b1e70e469aba91297bec
https://github.com/llvm/llvm-project/commit/e5d5503e4efa48b61194b1e70e469aba91297bec
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
A libclc/clc/include/clc/math/clc_hypot.h
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/math/clc_hypot.cl
A libclc/clc/lib/generic/math/clc_hypot.inc
M libclc/clspv/lib/SOURCES
R libclc/generic/include/math/clc_hypot.h
M libclc/generic/lib/SOURCES
R libclc/generic/lib/math/clc_hypot.cl
M libclc/generic/lib/math/hypot.cl
M libclc/spirv/lib/SOURCES
Log Message:
-----------
[libclc] Move hypot to CLC library; optimize (#129551)
This was already nominally in the CLC library; this commit just formally
moves it over. It simultaneously optimizes it for vector types by
avoiding scalarization.
Commit: 2af0e2f3e6c761ecd3f2dd31d0ae844572fcdce0
https://github.com/llvm/llvm-project/commit/2af0e2f3e6c761ecd3f2dd31d0ae844572fcdce0
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M lldb/bindings/python/CMakeLists.txt
M lldb/bindings/python/python.swig
Log Message:
-----------
Revert "Push down the swig module to avoid an import cycle" (#129714)
Reverts llvm/llvm-project#129135 due to buildbot test failures.
Definitely caused remote Linux to Windows failures
(https://lab.llvm.org/buildbot/#/builders/197/builds/2712), may be the
cause of Windows on Arm failures
https://lab.llvm.org/buildbot/#/builders/141/builds/6744.
Commit: 29dde55c5d03d7285882766795e15ec1e906f6c0
https://github.com/llvm/llvm-project/commit/29dde55c5d03d7285882766795e15ec1e906f6c0
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M libcxx/include/__utility/exception_guard.h
M libcxx/include/__utility/no_destroy.h
M libcxx/include/__utility/pair.h
M libcxx/include/__utility/scope_guard.h
M libcxx/include/__utility/swap.h
Log Message:
-----------
[libc++] Remove a few unused includes in <utility> headers (#129674)
Commit: 9ad515603d97615045470fc4bdc72e1865d2986d
https://github.com/llvm/llvm-project/commit/9ad515603d97615045470fc4bdc72e1865d2986d
Author: Chris B <chris.bieneman at me.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/test/Driver/hip-gz-options.hip
Log Message:
-----------
A more precise matching for the driver test (#129611)
Maybe this fixes issues detected after #128894
Commit: 1d8eb436ca694a9e215066e0b2dbd18b2d3943ea
https://github.com/llvm/llvm-project/commit/1d8eb436ca694a9e215066e0b2dbd18b2d3943ea
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/unions.cpp
Log Message:
-----------
[clang][bytecode] Diagnose member calls on inactive union fields (#129709)
Unless the function is a constructor, which is allowed to do this since
it will activate the member.
Commit: 4c4fd6b03149348cf11af245ad2603d24144a9d5
https://github.com/llvm/llvm-project/commit/4c4fd6b03149348cf11af245ad2603d24144a9d5
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.deprecated/p1.cpp
Log Message:
-----------
[clang] Fix missing diagnostic of declaration use when accessing TypeDecls through typename access (#129681)
We were missing a call to DiagnoseUseOfDecl when performing typename
access.
This refactors the code so that TypeDecl lookups funnel through a helper
which performs all the necessary checks, removing some related
duplication on the way.
Fixes #58547
Differential Revision: https://reviews.llvm.org/D136533
Commit: 1e6e845d49a336e9da7ca6c576ec45c0b419b5f6
https://github.com/llvm/llvm-project/commit/1e6e845d49a336e9da7ca6c576ec45c0b419b5f6
Author: Vinay Deshmukh <32487576+vinay-deshmukh at users.noreply.github.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/src/__support/CPP/bit.h
M libc/src/__support/CPP/span.h
M libc/src/__support/CPP/string.h
M libc/src/__support/CPP/string_view.h
M libc/src/__support/FPUtil/FPBits.h
M libc/src/__support/FPUtil/NormalFloat.h
M libc/src/__support/FPUtil/aarch64/FEnvImpl.h
M libc/src/__support/FPUtil/aarch64/fenv_darwin_impl.h
M libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
M libc/src/__support/OSUtil/darwin/io.h
M libc/src/__support/big_int.h
M libc/src/__support/high_precision_decimal.h
M libc/src/__support/integer_literals.h
M libc/src/__support/integer_to_string.h
M libc/src/__support/memory_size.h
M libc/src/__support/str_to_float.h
M libc/src/__support/str_to_integer.h
M libc/src/stdio/printf_core/parser.h
M libc/src/stdio/printf_core/writer.h
M libc/src/stdio/scanf_core/parser.h
M libc/src/stdlib/quick_sort.h
M libc/src/string/memory_utils/utils.h
M libc/src/string/string_utils.h
M libc/test/UnitTest/ExecuteFunction.h
M libc/test/UnitTest/ExecuteFunctionUnix.cpp
M libc/test/UnitTest/LibcTest.cpp
M libc/test/UnitTest/MemoryMatcher.h
M libc/test/src/__support/CPP/bit_test.cpp
M libc/test/src/__support/arg_list_test.cpp
M libc/test/src/__support/big_int_test.cpp
M libc/test/src/__support/blockstore_test.cpp
M libc/test/src/__support/fixedvector_test.cpp
M libc/test/src/__support/hash_test.cpp
M libc/test/src/__support/integer_to_string_test.cpp
M libc/test/src/__support/math_extras_test.cpp
M libc/test/src/__support/str_to_double_test.cpp
M libc/test/src/__support/str_to_float_test.cpp
M libc/test/src/__support/str_to_fp_test.h
M libc/test/src/math/FModTest.h
M libc/test/src/stdio/printf_core/parser_test.cpp
M libc/test/src/string/memmove_test.cpp
M libc/test/src/string/memory_utils/memory_check_utils.h
M libc/test/src/string/memory_utils/op_tests.cpp
M libc/test/src/string/memory_utils/utils_test.cpp
M libc/test/src/string/memset_test.cpp
M libc/test/src/strings/bcopy_test.cpp
Log Message:
-----------
[libc] Enable -Wconversion for tests. (#127523)
Relates to: #119281
Commit: d1c1ab100a496ada2208a92c37938c3ca8666e24
https://github.com/llvm/llvm-project/commit/d1c1ab100a496ada2208a92c37938c3ca8666e24
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/include/llvm/Transforms/IPO/ProfiledCallGraph.h
Log Message:
-----------
[IPO] Avoid repeated hash lookups (NFC) (#129654)
Commit: cd3d10cba512f34deb38d80e7acdf1af6b5d11c9
https://github.com/llvm/llvm-project/commit/cd3d10cba512f34deb38d80e7acdf1af6b5d11c9
Author: Jerry-Ge <jerry.ge at arm.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
A mlir/test/Dialect/Tosa/error_if_check.mlir
Log Message:
-----------
[mlir][tosa] Add more error_if checks for Resize Op (#129577)
Some of the error_if checks were missed in this PR:
https://github.com/llvm/llvm-project/pull/124956
Add back those tests to check suitable sizes for Resize
Signed-off-by: Luke Hutton <luke.hutton at arm.com>
Co-authored-by: Luke Hutton <luke.hutton at arm.com>
Commit: 9c542bcf0a1b243dd39c2ecffdd7331c15ae0fb1
https://github.com/llvm/llvm-project/commit/9c542bcf0a1b243dd39c2ecffdd7331c15ae0fb1
Author: T-Gruber <100079402+T-Gruber at users.noreply.github.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Core/ExprEngineCXX.cpp
M clang/unittests/StaticAnalyzer/ExprEngineVisitTest.cpp
Log Message:
-----------
[analyzer] performTrivialCopy triggers checkLocation before binding (#129016)
The triggered callbacks for the default copy constructed instance and
the instance used for initialization now behave in the same way. The LHS
already calls checkBind. To keep this consistent, checkLocation is now
triggered accordingly for the RHS.
Further details on the previous discussion:
https://discourse.llvm.org/t/checklocation-for-implicitcastexpr-of-kind-ck-noop/84729
---------
Authored-by: tobias.gruber <tobias.gruber at concentrio.io>
Commit: 180e305ac8c3c023faaf3fb4cea539d2cb6e311e
https://github.com/llvm/llvm-project/commit/180e305ac8c3c023faaf3fb4cea539d2cb6e311e
Author: Jerry-Ge <jerry.ge at arm.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
R mlir/test/Dialect/Tosa/error_if_check.mlir
Log Message:
-----------
Revert "[mlir][tosa] Add more error_if checks for Resize Op" (#129729)
Reverts llvm/llvm-project#129577. Need rebase to fix some errors.
Commit: 54ad11495ecd49171d238fbdb06a2d1ab8f68182
https://github.com/llvm/llvm-project/commit/54ad11495ecd49171d238fbdb06a2d1ab8f68182
Author: Thurston Dang <thurston at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-umaxv.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-uminv.ll
Log Message:
-----------
[msan][NFC] Add tests for Arm NEON umaxv/uminv (#129661)
This patch precommits tests for the umaxv/uminv intrinsics, which are currently handled suboptimally by visitInstruction.
Future work will update MSan to apply handleVectorReduceIntrinsic.
Commit: 0247a75072874d1238db89a88bed28ceea4c8625
https://github.com/llvm/llvm-project/commit/0247a75072874d1238db89a88bed28ceea4c8625
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.mir
A llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.mir
Log Message:
-----------
AMDGPU: Add some tests for folding immediates into subregister uses (#129663)
Commit: aeca2aa19374d7f70f6f84a99510535b854ec15a
https://github.com/llvm/llvm-project/commit/aeca2aa19374d7f70f6f84a99510535b854ec15a
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/memberpointers.cpp
Log Message:
-----------
[clang][bytecode] Fix CallPtr return type check (#129722)
CallExpr::getType() isn't enough here in some cases, we need to use
CallExpr::getCallReturnType().
Commit: 6720465c47303cafcd448c64af97e7b627c399a8
https://github.com/llvm/llvm-project/commit/6720465c47303cafcd448c64af97e7b627c399a8
Author: AZero13 <gfunni234 at gmail.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/test/CodeGenObjC/arc-blocks.m
M clang/test/CodeGenObjC/arc-property.m
M clang/test/CodeGenObjC/arc-weak-property.m
M clang/test/CodeGenObjC/arc.m
M clang/test/CodeGenObjC/arm64-int32-ivar.m
M clang/test/CodeGenObjC/bitfield-ivar-offsets.m
M clang/test/CodeGenObjC/constant-non-fragile-ivar-offset.m
M clang/test/CodeGenObjC/direct-method.m
M clang/test/CodeGenObjC/hidden-visibility.m
M clang/test/CodeGenObjC/interface-layout-64.m
M clang/test/CodeGenObjC/ivar-base-as-invariant-load.m
M clang/test/CodeGenObjC/metadata-symbols-64.m
M clang/test/CodeGenObjC/nontrivial-c-struct-property.m
M clang/test/CodeGenObjC/objc-asm-attribute-test.m
M clang/test/CodeGenObjC/ubsan-bool.m
Log Message:
-----------
[ObjC] Expand isClassLayoutKnownStatically to base classes as long as the implementation of it is known (#85465)
Only NSObject we can trust the layout of won't change even though we
cannot directly see its @implementation
Commit: fd374e56b62e5e01adeb64aa6e34f8e73af5f208
https://github.com/llvm/llvm-project/commit/fd374e56b62e5e01adeb64aa6e34f8e73af5f208
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang-tools-extra/clangd/TidyProvider.cpp
M clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/VTableBuilder.h
M clang/include/clang/Basic/ABI.h
M clang/include/clang/Basic/DiagnosticIDs.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Descriptor.cpp
M clang/lib/AST/ByteCode/Descriptor.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/MicrosoftMangle.cpp
M clang/lib/AST/VTableBuilder.cpp
M clang/lib/Analysis/FlowSensitive/Transfer.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCXX.cpp
M clang/lib/CodeGen/CGCXXABI.cpp
M clang/lib/CodeGen/CGCXXABI.h
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/lib/CodeGen/CGVTables.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/CodeGen/MicrosoftCXXABI.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Headers/opencl-c.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCXX.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/functions.cpp
M clang/test/AST/ByteCode/memberpointers.cpp
M clang/test/AST/ByteCode/records.cpp
M clang/test/AST/ByteCode/unions.cpp
M clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.deprecated/p1.cpp
A clang/test/CodeGen/arm-neon-endianness.c
M clang/test/CodeGenCXX/debug-info-windows-dtor.cpp
M clang/test/CodeGenCXX/dllexport.cpp
M clang/test/CodeGenCXX/microsoft-abi-extern-template.cpp
M clang/test/CodeGenCXX/microsoft-abi-structors.cpp
M clang/test/CodeGenCXX/microsoft-abi-thunks.cpp
M clang/test/CodeGenCXX/microsoft-abi-vftables.cpp
M clang/test/CodeGenCXX/microsoft-abi-virtual-inheritance.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-multiple-nonvirtual-inheritance-vdtors.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-return-thunks.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-single-inheritance.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-virtual-inheritance-vtordisps.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-virtual-inheritance.cpp
M clang/test/CodeGenCXX/microsoft-no-rtti-data.cpp
A clang/test/CodeGenCXX/microsoft-vector-deleting-dtors.cpp
M clang/test/CodeGenCXX/vtable-consteval.cpp
M clang/test/CodeGenObjC/arc-blocks.m
M clang/test/CodeGenObjC/arc-property.m
M clang/test/CodeGenObjC/arc-weak-property.m
M clang/test/CodeGenObjC/arc.m
M clang/test/CodeGenObjC/arm64-int32-ivar.m
M clang/test/CodeGenObjC/bitfield-ivar-offsets.m
M clang/test/CodeGenObjC/constant-non-fragile-ivar-offset.m
M clang/test/CodeGenObjC/direct-method.m
M clang/test/CodeGenObjC/hidden-visibility.m
M clang/test/CodeGenObjC/interface-layout-64.m
M clang/test/CodeGenObjC/ivar-base-as-invariant-load.m
M clang/test/CodeGenObjC/metadata-symbols-64.m
M clang/test/CodeGenObjC/nontrivial-c-struct-property.m
M clang/test/CodeGenObjC/objc-asm-attribute-test.m
M clang/test/CodeGenObjC/ubsan-bool.m
M clang/test/Driver/hip-gz-options.hip
M clang/test/Modules/vtable-windows.cppm
M clang/test/Profile/cxx-abc-deleting-dtor.cpp
M clang/tools/c-index-test/c-index-test.c
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/SortIncludesTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/StaticAnalyzer/ExprEngineVisitTest.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M clang/www/cxx_status.html
M compiler-rt/test/ubsan/TestCases/Float/cast-overflow.cpp
M flang-rt/cmake/modules/AddFlangRTOffload.cmake
M flang/include/flang/Common/erfc-scaled.h
M flang/include/flang/Evaluate/characteristics.h
M flang/include/flang/Evaluate/tools.h
M flang/lib/Evaluate/check-expression.cpp
M flang/lib/Evaluate/fold-logical.cpp
M flang/lib/Evaluate/fold.cpp
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Evaluate/shape.cpp
M flang/lib/Evaluate/tools.cpp
M flang/lib/Lower/ConvertConstant.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/check-declarations.cpp
M flang/lib/Semantics/data-to-inits.cpp
M flang/lib/Semantics/definable.cpp
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/pointer-assignment.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Evaluate/folding06.f90
A flang/test/Integration/debug-cyclic-derived-type-4.f90
M flang/test/Lower/HLFIR/null.f90
M flang/test/Semantics/associated.f90
M flang/test/Semantics/call27.f90
M flang/test/Semantics/coarrays02.f90
A flang/test/Semantics/generic13.f90
M flang/test/Semantics/init01.f90
M flang/test/Semantics/null01.f90
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/src/__support/CPP/bit.h
M libc/src/__support/CPP/span.h
M libc/src/__support/CPP/string.h
M libc/src/__support/CPP/string_view.h
M libc/src/__support/FPUtil/FPBits.h
M libc/src/__support/FPUtil/NormalFloat.h
M libc/src/__support/FPUtil/aarch64/FEnvImpl.h
M libc/src/__support/FPUtil/aarch64/fenv_darwin_impl.h
M libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
M libc/src/__support/OSUtil/darwin/io.h
M libc/src/__support/big_int.h
M libc/src/__support/high_precision_decimal.h
M libc/src/__support/integer_literals.h
M libc/src/__support/integer_to_string.h
M libc/src/__support/memory_size.h
M libc/src/__support/str_to_float.h
M libc/src/__support/str_to_integer.h
M libc/src/stdio/printf_core/parser.h
M libc/src/stdio/printf_core/writer.h
M libc/src/stdio/scanf_core/parser.h
M libc/src/stdlib/qsort_pivot.h
M libc/src/stdlib/quick_sort.h
M libc/src/string/memory_utils/utils.h
M libc/src/string/string_utils.h
M libc/test/UnitTest/ExecuteFunction.h
M libc/test/UnitTest/ExecuteFunctionUnix.cpp
M libc/test/UnitTest/LibcTest.cpp
M libc/test/UnitTest/MemoryMatcher.h
M libc/test/src/__support/CPP/bit_test.cpp
M libc/test/src/__support/arg_list_test.cpp
M libc/test/src/__support/big_int_test.cpp
M libc/test/src/__support/blockstore_test.cpp
M libc/test/src/__support/fixedvector_test.cpp
M libc/test/src/__support/hash_test.cpp
M libc/test/src/__support/integer_to_string_test.cpp
M libc/test/src/__support/math_extras_test.cpp
M libc/test/src/__support/str_to_double_test.cpp
M libc/test/src/__support/str_to_float_test.cpp
M libc/test/src/__support/str_to_fp_test.h
M libc/test/src/math/FModTest.h
M libc/test/src/stdio/printf_core/parser_test.cpp
M libc/test/src/string/memmove_test.cpp
M libc/test/src/string/memory_utils/memory_check_utils.h
M libc/test/src/string/memory_utils/op_tests.cpp
M libc/test/src/string/memory_utils/utils_test.cpp
M libc/test/src/string/memset_test.cpp
M libc/test/src/strings/bcopy_test.cpp
A libclc/clc/include/clc/math/clc_hypot.h
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/math/clc_hypot.cl
A libclc/clc/lib/generic/math/clc_hypot.inc
M libclc/clspv/lib/SOURCES
R libclc/generic/include/math/clc_hypot.h
M libclc/generic/lib/SOURCES
R libclc/generic/lib/math/clc_hypot.cl
M libclc/generic/lib/math/hypot.cl
M libclc/spirv/lib/SOURCES
M libcxx/include/__algorithm/stable_partition.h
M libcxx/include/__utility/exception_guard.h
M libcxx/include/__utility/no_destroy.h
M libcxx/include/__utility/pair.h
M libcxx/include/__utility/scope_guard.h
M libcxx/include/__utility/swap.h
M libcxx/include/__vector/vector.h
M libcxx/include/algorithm
M libcxx/test/std/algorithms/alg.modifying.operations/alg.partitions/stable_partition.pass.cpp
M libcxx/test/std/algorithms/robust_against_proxy_iterators_lifetime_bugs.pass.cpp
M libcxx/test/std/algorithms/robust_re_difference_type.compile.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_range.pass.cpp
M lld/test/wasm/emit-relocs.s
M lld/wasm/InputChunks.cpp
M lld/wasm/InputChunks.h
M lld/wasm/OutputSections.cpp
M lld/wasm/OutputSections.h
M lld/wasm/Symbols.cpp
M lldb/bindings/python/CMakeLists.txt
M lldb/bindings/python/python.swig
M lldb/test/API/tools/lldb-dap/breakpoint-events/TestDAP_breakpointEvents.py
M lldb/test/API/tools/lldb-dap/variables/children/TestDAP_variables_children.py
M lldb/tools/lldb-dap/Handler/InitializeRequestHandler.cpp
M lldb/unittests/SymbolFile/DWARF/XcodeSDKModuleTests.cpp
A llvm/docs/CIBestPractices.rst
M llvm/docs/Reference.rst
M llvm/docs/ReleaseNotes.md
A llvm/include/llvm/CodeGen/ExpandPostRAPseudos.h
A llvm/include/llvm/CodeGen/FixupStatepointCallerSaved.h
M llvm/include/llvm/CodeGen/RegAllocGreedyPass.h
M llvm/include/llvm/IR/Analysis.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Transforms/IPO/ProfiledCallGraph.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
M llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/lib/CodeGen/SplitKit.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIModeRegister.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/SPIRV.h
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
A llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrFragments.td
M llvm/lib/Target/X86/X86InstrOperands.td
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanHCFGBuilder.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/seqpaircopy.mir
M llvm/test/CodeGen/AArch64/sve-fcvt.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-split-fcvt.ll
M llvm/test/CodeGen/AArch64/sve-vector-splat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/acc-ldst.ll
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nondeterminism.ll
M llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.mir
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-cycle.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/mmra.ll
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
M llvm/test/CodeGen/AMDGPU/mode-register.mir
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
M llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll
M llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
A llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.mir
A llvm/test/CodeGen/AMDGPU/splitkit-do-not-undo-subclass-split-with-remat.mir
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
A llvm/test/CodeGen/SPIRV/pointers/array-skips-gep.ll
A llvm/test/CodeGen/SPIRV/pointers/getelementptr-downcast-vector.ll
M llvm/test/CodeGen/SystemZ/copy-phys-reg-gr64-to-fp64.mir
M llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc.ll
M llvm/test/CodeGen/X86/eq-or-eq-range-of-2.ll
M llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll
M llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll
A llvm/test/CodeGen/X86/lea-16bit.ll
A llvm/test/CodeGen/X86/lea-8bit.ll
M llvm/test/CodeGen/X86/setcc-lowering.ll
M llvm/test/CodeGen/X86/statepoint-fixup-call.mir
M llvm/test/CodeGen/X86/statepoint-fixup-copy-prop-neg.mir
M llvm/test/CodeGen/X86/statepoint-fixup-copy-prop.mir
M llvm/test/CodeGen/X86/statepoint-fixup-invoke.mir
M llvm/test/CodeGen/X86/statepoint-fixup-shared-ehpad.mir
M llvm/test/CodeGen/X86/statepoint-fixup-undef-def.mir
M llvm/test/CodeGen/X86/statepoint-fixup-undef.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
M llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-umaxv.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-uminv.ll
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
M llvm/test/Transforms/GVN/opt-remarks.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_estimated_tc.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_memcheck_cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll
A llvm/test/tools/llvm-exegesis/RISCV/latency-by-load.s
M llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp
M llvm/tools/llvm-mca/CodeRegion.cpp
M llvm/tools/llvm-readobj/COFFDumper.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/TableGen/X86RecognizableInstr.cpp
M mlir/docs/Dialects/Linalg/_index.md
M mlir/include/mlir/Analysis/FlatLinearValueConstraints.h
M mlir/include/mlir/Analysis/Presburger/IntegerRelation.h
M mlir/include/mlir/Dialect/Affine/Analysis/Utils.h
M mlir/include/mlir/Dialect/Affine/Passes.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgDoc.td
M mlir/include/mlir/IR/OperationSupport.h
M mlir/lib/Analysis/FlatLinearValueConstraints.cpp
M mlir/lib/Analysis/Presburger/IntegerRelation.cpp
M mlir/lib/Conversion/MPIToLLVM/MPIToLLVM.cpp
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/test/Dialect/Affine/affine-data-copy.mlir
M mlir/test/Dialect/Affine/dma-generate.mlir
M mlir/test/Dialect/Affine/loop-fusion-3.mlir
M mlir/test/Dialect/Affine/loop-fusion.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/unittests/IR/OperationSupportTest.cpp
Log Message:
-----------
Rebase, address comments
Created using spr 1.3.5
Compare: https://github.com/llvm/llvm-project/compare/617b0c39d04c...fd374e56b62e
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