[all-commits] [llvm/llvm-project] f909b2: [libcxx] Provide locale conversions to tests throu...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Tue Mar 4 06:58:11 PST 2025
Branch: refs/heads/users/alexey-bataev/spr/slpreduce-number-of-alternate-instruction-where-possible-1
Home: https://github.com/llvm/llvm-project
Commit: f909b2229ac16ae3898d8b158bee85c384173dfa
https://github.com/llvm/llvm-project/commit/f909b2229ac16ae3898d8b158bee85c384173dfa
Author: Martin Storsjö <martin at martin.st>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M libcxx/test/std/localization/locale.categories/category.monetary/locale.money.get/locale.money.get.members/get_long_double_fr_FR.pass.cpp
M libcxx/test/std/localization/locale.categories/category.monetary/locale.money.get/locale.money.get.members/get_long_double_ru_RU.pass.cpp
M libcxx/test/std/localization/locale.categories/category.monetary/locale.money.put/locale.money.put.members/put_long_double_fr_FR.pass.cpp
M libcxx/test/std/localization/locale.categories/category.monetary/locale.money.put/locale.money.put.members/put_long_double_ru_RU.pass.cpp
M libcxx/test/std/localization/locale.categories/category.monetary/locale.moneypunct.byname/thousands_sep.pass.cpp
M libcxx/test/std/localization/locale.categories/facet.numpunct/locale.numpunct.byname/thousands_sep.pass.cpp
M libcxx/test/std/time/time.duration/time.duration.nonmember/ostream.pass.cpp
M libcxx/test/support/locale_helpers.h
M libcxx/utils/libcxx/test/features.py
Log Message:
-----------
[libcxx] Provide locale conversions to tests through lit substitution (#105651)
There are 2 problems today that this PR resolves:
libcxx tests assume the thousands separator for fr_FR locale is x00A0 on
Windows. This currently fails when run on newer versions of Windows (it
seems to have been updated to the new correct value of 0x202F around
windows 11. The exact windows version where it changed doesn't seem to
be documented anywhere). Depending the OS version, you need different
values.
There are several ifdefs to determine the environment/platform-specific
locale conversion values and it leads to maintenance as things change
over time.
This PR includes the following changes:
- Provide the environment's locale conversion values through a
substitution. The test can opt in by placing the substitution value in a
define flag.
- Remove the platform ifdefs (the swapping of values between Windows,
Linux, Apple, AIX).
This is accomplished through a lit feature action that fetches the
environment's locale conversions (lconv) for members like
'thousands_sep' that we need to provide. This should ensure that we
don't lose the effectiveness of the test itself.
In addition, as a result of the above, this PR:
- Fixes a handful of locale tests which unexpectedly fail on newer
Windows versions.
- Resolves 3 XFAIL FIX-MEs.
Originally submitted in https://github.com/llvm/llvm-project/pull/86649.
Co-authored-by: Rodrigo Salazar <4rodrigosalazar at gmail.com>
Commit: ddbce2fd2380a4eafce9065ad991318f46a3292b
https://github.com/llvm/llvm-project/commit/ddbce2fd2380a4eafce9065ad991318f46a3292b
Author: jimingham <jingham at apple.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M lldb/include/lldb/Target/ThreadPlanShouldStopHere.h
M lldb/source/Target/ThreadPlanShouldStopHere.cpp
M lldb/source/Target/ThreadPlanStepInRange.cpp
Log Message:
-----------
Control the "step out through thunk" logic explicitly when pushing thread plans (#129301)
Jonas recently added a trampoline handling strategy for simple language
thunks that does: "step through language thunks stepping in one level
deep and stopping if you hit user code". That was actually pulled over
from the swift implementation. However, this strategy and the strategy
we have to "step out past language thunks" when stepping out come into
conflict if the thunk you are stepping through calls some other function
before dispatching to the intended method. When you step out of the
called function back into the thunk, should you keep stepping out past
the thunk or not?
In most cases, you want to step out past the thunk, but in this
particular case you don't.
This patch adds a way to inform the thread plan (or really it's
ShouldStopHere behavior) of which behavior it should have, and passes
the don't step through thunks to the step through plan it uses to step
through thunks.
I didn't add a test for this because I couldn't find a C++ thunk that
calls another function before getting to the target function. I asked
the clang folks here if they could think of a case where clang would do
this, and they couldn't. If anyone can think of such a construct, it
will be easy to write the step through test for it...
This does happen in swift, however, so when I cherry-pick this to the
swift fork I'll test it there.
Commit: d2cbd5fe6b6e280b71994c30da878751bc2a435a
https://github.com/llvm/llvm-project/commit/d2cbd5fe6b6e280b71994c30da878751bc2a435a
Author: vporpo <vporpodas at google.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M llvm/include/llvm/SandboxIR/Region.h
M llvm/unittests/SandboxIR/RegionTest.cpp
Log Message:
-----------
[SandboxIR][Region][NFC] Change visibility of Region::add()/remove() (#129277)
The vectorizer's passes should not be allowed to manually add/remove
elements. This should only be done automatically by the callbacks.
Commit: 006534315972728390d82fc8381c9ab1bf6e6490
https://github.com/llvm/llvm-project/commit/006534315972728390d82fc8381c9ab1bf6e6490
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M llvm/lib/Target/NVPTX/CMakeLists.txt
M llvm/lib/Target/NVPTX/NVPTX.h
A llvm/lib/Target/NVPTX/NVPTXForwardParams.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
A llvm/test/CodeGen/NVPTX/forward-ld-param.ll
M llvm/test/CodeGen/NVPTX/i128-array.ll
M llvm/test/CodeGen/NVPTX/lower-args-gridconstant.ll
M llvm/test/CodeGen/NVPTX/lower-args.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/nvptx-basic.ll.expected
Log Message:
-----------
[NVPTX] Improve device function byval parameter lowering (#129188)
PTX supports 2 methods of accessing device function parameters:
- "simple" case: If a parameters is only loaded, and all loads can
address the parameter via a constant offset, then the parameter may be
loaded via the ".param" address space. This case is not possible if the
parameters is stored to or has it's address taken. This method is
preferable when possible.
- "move param" case: For more complex cases the address of the param may
be placed in a register via a "mov" instruction. This mov also
implicitly moves the param to the ".local" address space and allows for
it to be written to. This essentially defers the responsibilty of the
byval copy to the PTX calling convention.
The handling of these cases in the NVPTX backend for byval pointers has
some major issues. We currently attempt to determine if a copy is
necessary in NVPTXLowerArgs and either explicitly make an additional
copy in the IR, or insert "addrspacecast" to move the param to the param
address space. Unfortunately the criteria for determining which case is
possible are not correct, leading to miscompilations
(https://godbolt.org/z/Gq1fP7a3G). Further, the criteria for the
"simple" case aren't enforceable in LLVM IR across other transformations
and instruction selection, making deciding between the 2 cases in
NVPTXLowerArgs brittle and buggy.
This patch aims to fix these issues and improve address space related
optimization. In NVPTXLowerArgs, we conservatively assume that all
parameters will use the "move param" case and the local address space.
Responsibility for switching to the "simple" case is given to a new
MachineIR pass, NVPTXForwardParams, which runs once it has become clear
whether or not this is possible. This ensures that the correct address
space is known for the "move param" case allowing for optimization,
while still using the "simple" case where ever possible.
Commit: 7e11ef170edccfe5ff85ce4756b58adf9e3455ba
https://github.com/llvm/llvm-project/commit/7e11ef170edccfe5ff85ce4756b58adf9e3455ba
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/SCF/Utils/Utils.h
M mlir/lib/Dialect/SCF/Utils/Utils.cpp
Log Message:
-----------
[mlir][scf] Fix typo of `epilogue`(NFC) (#128707)
Commit: 6ff0f69fec0ebdc86abf2e6af75f2edcccc2f936
https://github.com/llvm/llvm-project/commit/6ff0f69fec0ebdc86abf2e6af75f2edcccc2f936
Author: vporpo <vporpodas at google.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
Log Message:
-----------
[SandboxVec][BottomUpVec] Fix vectorization of vector constants (#129290)
This patch fixes the value we generate when we vectorize constants.
Commit: a19e685ea228ec367a7fa01bbf811c3cded37a83
https://github.com/llvm/llvm-project/commit/a19e685ea228ec367a7fa01bbf811c3cded37a83
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
R clang/include/clang/CIR/Dialect/IR/CIRAttrVisitor.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
Log Message:
-----------
[CIR] Realign CIR-to-LLVM IR lowering code with incubator (#129293)
The previously upstreamed lowering from ClangIR to LLVM IR diverged from
the incubator implementation, but when the incubator was updated to
incorporate these changes some issues arose which require the upstream
implementation to be modified to re-align with the incubator.
First, in the earlier upstream implementation a CIRAttrVisitor class was
introduced with the intention that an mlir-tblgen based extension would
be created to automatically add all CIR attributes to the visitor. When
I proposed this in mlir-tblgen a reviewer suggested that what I wanted
could be better accomplished with TypeSwitch.
See https://github.com/llvm/llvm-project/pull/126332
This was done in the incubator, and here I am bringing that
implementation upstream.
The other issue was that the global op initialization in the incubator
had more cases than I had accounted for in my previous upstream
refactoring. I did still refactor the incubator code, but not in quite
the same way as the upstream code. This change re-aligns the two.
Commit: 22965dc5f9c72d6b411458d4115e05a310d619eb
https://github.com/llvm/llvm-project/commit/22965dc5f9c72d6b411458d4115e05a310d619eb
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
Log Message:
-----------
[RISCV] Simplify getStackAdjBase. NFC (#129281)
Use math instead of a switch.
Commit: 21a050049d2cdec04376cc61d92a4931f3adf380
https://github.com/llvm/llvm-project/commit/21a050049d2cdec04376cc61d92a4931f3adf380
Author: Alex Voicu <alexandru.voicu at amd.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M clang/lib/Headers/__clang_hip_libdevice_declares.h
M clang/lib/Headers/__clang_hip_math.h
M clang/test/Headers/__clang_hip_math.hip
Log Message:
-----------
Reapply "[clang][HIP] Make some math not not work with AMDGCN SPIR-V #128360" (#129306)
This reapplies #128360, the only change being that the modified tests
also checks for the availability of the SPIRV target.
Commit: b3e05d58b93c054b619c1fa9b967455a3d269484
https://github.com/llvm/llvm-project/commit/b3e05d58b93c054b619c1fa9b967455a3d269484
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
Log Message:
-----------
[mlir][nvvm] Add conversion for math.erfc (#129329)
Add missing pattern to convert `math.erfc` operation to `__nv_erfcf` or
`__nv_erfc` function call.
Commit: ae84717d11bf89e69eb9fd74f3ddd32af51192d7
https://github.com/llvm/llvm-project/commit/ae84717d11bf89e69eb9fd74f3ddd32af51192d7
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M flang-rt/lib/cuda/memory.cpp
Log Message:
-----------
[flang][cuda] Fix descriptor sync in data transfer (#129333)
The destination descriptor on the device needs to be sync with the
destination descriptor on the host, not the src one.
Commit: b697bf3c0176e0f9c2f1ab5d39c797469f9037bd
https://github.com/llvm/llvm-project/commit/b697bf3c0176e0f9c2f1ab5d39c797469f9037bd
Author: Min Hsu <min.hsu at sifive.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M llvm/test/tools/llvm-exegesis/RISCV/rvv/explicit-sew.test
M llvm/test/tools/llvm-exegesis/RISCV/rvv/skip-rm.test
M llvm/test/tools/llvm-exegesis/RISCV/rvv/valid-sew-zvk.test
M llvm/test/tools/llvm-exegesis/RISCV/rvv/valid-sew.test
Log Message:
-----------
[Exegesis][RISCV] Skip some of the tests under expensive checks
Under expensive checks, some of the tests will fail to pass the
MachineVerifier. It's because right after a snippet is generated, its VL
operand (if it's a register) is assigned a physical register. While
we'll replace it with virtual register in RISCVExegesisPreprocessing,
it's technically violating RISCVInstrInfo's validation rule.
Under normal circumstances, this won't trigger a MachineVerifier failure
because the codegen pipeline doesn't validate the code until the very
end -- which is not the case under EXPENSIVE_CHECKS where
MachineVerifierPass is sprinkled here and there.
This is really caused by the fact that RISCV exegesis has an odd
"codegen" Pass pipeline. And I don't have a good solution yet, so I'm
surpressing these tests under EXPENSIVE_CHECKS.
Commit: b2cc28cab113554aa63b9097f23796d59175d28f
https://github.com/llvm/llvm-project/commit/b2cc28cab113554aa63b9097f23796d59175d28f
Author: Min Hsu <min.hsu at sifive.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M llvm/test/tools/llvm-exegesis/RISCV/rvv/reduction.test
Log Message:
-----------
[Exegesis][RISCV] Only check if vd and vs2 are alias in rvv/reduction.test
This test was designed to check if we alias between vd and vs2. While we
make sure there is no alias relationship between vd and vs1 in the
snippet generator, there is nothing preventing the randomizer to assign
the same register between vs1 and vs2. Which makes this test pretty
unstable.
However, we really only care if vd and vs2 are alias, so instead of
going an extra mile to check whether vd and vs1 are NOT alias, which is
actually irrelevant, we should just focusing on checking if vd and vs2
are alias.
Commit: 5cf9435fd4e7ab0a27ba514557e0982f9c882bc0
https://github.com/llvm/llvm-project/commit/5cf9435fd4e7ab0a27ba514557e0982f9c882bc0
Author: pirama-arumuga-nainar <pirama at google.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
Log Message:
-----------
[compiler-rt][rtsan] Do not intercept [f]truncate64 for musl (#129331)
Musl has 64-bit off_t by default and has macros that redefine
[f]truncate64 to [f]truncate.
Commit: 743571b5f11599232a2a0a9c396827782ed4868c
https://github.com/llvm/llvm-project/commit/743571b5f11599232a2a0a9c396827782ed4868c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Log Message:
-----------
[RISCV] Remove unused argument. NFC
Commit: 273fca94d4c4896df15f967a1388b7c533b76062
https://github.com/llvm/llvm-project/commit/273fca94d4c4896df15f967a1388b7c533b76062
Author: Pranav Bhandarkar <pranav.bhandarkar at amd.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-target-private-allocatable.mlir
Log Message:
-----------
[MLIR][OpenMP] - Fix translation of omp.target when private variables need cleaning up (#129205)
This is a simple fix that ensures that the InsertPoint is properly fixed
up after we have translated the dealloc region of all privatized
variables during translation of omp.target from MLIR to LLVMIR.
Fix for https://github.com/llvm/llvm-project/issues/129202
Commit: a085da66783e9576f9a9105e7fd5726f2039303b
https://github.com/llvm/llvm-project/commit/a085da66783e9576f9a9105e7fd5726f2039303b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
Log Message:
-----------
[RISCV] Remove X26 from encodeRlist. NFC
The caller already checks X26 and generates its own error.
Commit: 45d018097c8e92f1978478382426c683b19be88f
https://github.com/llvm/llvm-project/commit/45d018097c8e92f1978478382426c683b19be88f
Author: vporpo <vporpodas at google.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
A llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Debug.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/TransactionAcceptOrRevert.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/TransactionSave.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.cpp
Log Message:
-----------
[SandboxVec][NFC] Add LLVM_DEBUG dumps (#129335)
This patch updates/adds LLVM_DEBUG dumps.
It moves the DEBUG_TYPE into SandboxVectorizer/Debug.h such that it can
be shared across all components of the vectorizer.
Commit: 11b9466c04db4da7439fc1d9d8ba7241a9d68705
https://github.com/llvm/llvm-project/commit/11b9466c04db4da7439fc1d9d8ba7241a9d68705
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M lldb/source/Commands/CommandObjectThread.cpp
M lldb/source/Commands/Options.td
M lldb/test/API/functionalities/plugins/python_os_plugin/TestPythonOSPlugin.py
Log Message:
-----------
[lldb] Add ability to inspect backing threads with `thread info` (#129275)
When OS plugins are present, it can be helpful to query information
about the backing thread behind an OS thread, if it exists. There is no
mechanism to do so prior to this commit.
As a first step, this commit enhances `thread info` with a
`--backing-thread` flag, causing the command to use the backing thread
of the selected thread, if it exists.
Commit: 23c41bf1d599fddb4c5ee5eee7a30b5fdaa7f1be
https://github.com/llvm/llvm-project/commit/23c41bf1d599fddb4c5ee5eee7a30b5fdaa7f1be
Author: Min Hsu <min.hsu at sifive.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M llvm/test/tools/llvm-exegesis/RISCV/rvv/filter.test
Log Message:
-----------
[Exegesis][RISCV] Allow rvv/filter.test to retry
Sometimes it'll fail to generate any snippet because it's unable to
assign unique def and use registers.
Mark this test as ALLOW_RETRIES. Also, lower the minimum number of
instructions per snippet in the hope to increase the chance of
assigning unique registers for every instructions.
Commit: 1f27ff91b3104f3d2038324f09fb9cab2c75d037
https://github.com/llvm/llvm-project/commit/1f27ff91b3104f3d2038324f09fb9cab2c75d037
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h
M llvm/lib/Target/NVPTX/NVPTXInstrFormats.td
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
Log Message:
-----------
[NVPTX] Delete `IsSimpleMove` (NFC) (#129178)
This field is never used, so we should remove it.
Commit: 32dffdce0511a9e2358842b8856da1b4103d72cb
https://github.com/llvm/llvm-project/commit/32dffdce0511a9e2358842b8856da1b4103d72cb
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
M llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlseg-vsseg.s
Log Message:
-----------
[RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (#128978)
It seems like we had been picking the wrong VPseudo scheduling class for
indexed memory operations in RISCVMCACustomBehavior: the VPseudo opcode
of indexed memory ops encode two EMULs, one for index and the other for
data. However, in RISCVInversePseudoTable, we're only able to look up
against one of them, yielding an incorrect VPseudo opcode with the wrong
data EEW (index EEW is encoded in the opcode). Since scheduling classes
for indexed memory ops uses data EMUL / EEW in their scheduling class,
we would eventually fetch the wrong scheduling classes with faulty data
EEW.
This patch fixes this issue by deducting the correct index EMUL with
LMUL (data EMUL), SEW (data EEW), and index EEW. With these parameters
we can thus fetch the correct VPseudo opcode with `getVLXPseudo` /
`getVLXSEGPseudo` and friends.
The new search table, RISCVBaseVXMemOpTable, is created to extract the
NF and index EEW info from MC opcode. Otherwise we need to write a
gigantic switch statement to decode this info.
Commit: 7cf2f602df40e619adef7259dac5cc50434e8769
https://github.com/llvm/llvm-project/commit/7cf2f602df40e619adef7259dac5cc50434e8769
Author: Jie Fu <jiefu at tencent.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/TransactionAcceptOrRevert.cpp
Log Message:
-----------
[Vectorize] Fix unused variable warnings (NFC)
/llvm-project/llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/TransactionAcceptOrRevert.cpp:24:8: error: unused variable 'CostBefore' [-Werror,-Wunused-variable]
auto CostBefore = SB.getBeforeCost();
^
/llvm-project/llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/TransactionAcceptOrRevert.cpp:25:8: error: unused variable 'CostAfter' [-Werror,-Wunused-variable]
auto CostAfter = SB.getAfterCost();
^
2 errors generated.
Commit: 074c2c6713277c087e1c3b9938cefff012d3840c
https://github.com/llvm/llvm-project/commit/074c2c6713277c087e1c3b9938cefff012d3840c
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M bolt/lib/Core/BinaryFunction.cpp
Log Message:
-----------
[BOLT] Refactor MCInst target symbol lookup. NFCI (#129131)
In analyzeInstructionForFuncReference(), use MCPlusBuilder interface
while scanning symbolic operands of MCInst. Should be NFC on x86, but
will make the function work on other architectures. Note that it's
currently unused on non-x86 as its functionality is exclusive to safe
ICF that runs on x86 only.
Commit: 4ab9c13ba2a6f505fb1b72ae33753902ae9f81e8
https://github.com/llvm/llvm-project/commit/4ab9c13ba2a6f505fb1b72ae33753902ae9f81e8
Author: Nico Weber <thakis at chromium.org>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-exegesis/lib/RISCV/BUILD.gn
Log Message:
-----------
[gn] port c253e5c9917b (RISCV llvm-exegesis)
See here for the additional tblgen deps:
https://github.com/llvm/llvm-project/pull/128767#issuecomment-2691834320
Commit: 0a0775e795850503e1d7da3543e663f584c1810c
https://github.com/llvm/llvm-project/commit/0a0775e795850503e1d7da3543e663f584c1810c
Author: Nico Weber <thakis at chromium.org>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCA/BUILD.gn
Log Message:
-----------
[gn] port 32dffdce0511 (more RISCV depedency things)
Looks like RISCV is picking up AMDGPU's bad habits wrt generated files.
Commit: 9421e1785b837fc2645ca1e165bbf975faab4288
https://github.com/llvm/llvm-project/commit/9421e1785b837fc2645ca1e165bbf975faab4288
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/NVPTX/BUILD.gn
Log Message:
-----------
[gn build] Port 006534315972
Commit: 78de27aac6b3e8d3f6394e9bbca887eb721af07b
https://github.com/llvm/llvm-project/commit/78de27aac6b3e8d3f6394e9bbca887eb721af07b
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M mlir/include/mlir/Analysis/Presburger/IntegerRelation.h
M mlir/lib/Analysis/FlatLinearValueConstraints.cpp
M mlir/lib/Analysis/Presburger/IntegerRelation.cpp
Log Message:
-----------
[MLIR] NFC. Improve API signature + clang-tidy warning in IntegerRelation (#128993)
Commit: 3c518940b0bdb7acd0692d280e1b4e2337fb5236
https://github.com/llvm/llvm-project/commit/3c518940b0bdb7acd0692d280e1b4e2337fb5236
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M .ci/metrics/metrics.py
Log Message:
-----------
[CI] Make Metrics Container Use Python Logging
This patch makes the metrics container use the python logging library. This
is more of what we want given we're essentially just logging the status of
things. It also means we do not have to explicitly specify an output file
and lets us control verbosity a bit more cleanly.
Commit: cef6dbbe544ff4c49fca65cdc50df783d8c39c28
https://github.com/llvm/llvm-project/commit/cef6dbbe544ff4c49fca65cdc50df783d8c39c28
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M .ci/metrics/metrics.py
Log Message:
-----------
[CI] Add Logging for Workflow Jobs
This patch adds some logging information for individual workflow jobs inside
the metrics container. This is mainly intended for debugging why we seem to be
missing metrics from some workflows within Grafana.
Commit: 84b365c26b963de47ed4b712f59d276b15871ddb
https://github.com/llvm/llvm-project/commit/84b365c26b963de47ed4b712f59d276b15871ddb
Author: Trevor Gross <t.gross35 at gmail.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Correct documentation for `roundeven` (#125452)
Langref for `roundeven` implies that the C standard function `roundeven`
may raise floating point exceptions. However, this is not correct; C23
does not mention exceptions for `roundeven`, and per [1] `FE_INEXACT` is
never raised.
Clarify that LLVM's `roundeven` behaves the same.
[1]: https://en.cppreference.com/w/c/numeric/math/roundeven
Commit: 620953328dc768ef6b205077214a01ae0579975c
https://github.com/llvm/llvm-project/commit/620953328dc768ef6b205077214a01ae0579975c
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M libc/utils/MPCWrapper/MPCUtils.h
Log Message:
-----------
[libc] Fix warning in libc/utils/MPCWrapper/MPCUtils.h (#129349)
`cpp::is_complex_type_same<T1, T2>` is a function, so we need
parentheses in order to call it. Otherwise the expression is treated
like a function pointer which is always true in this boolean context.
Commit: dfca4f9519e6c55364d791f26fcde374cb67fb67
https://github.com/llvm/llvm-project/commit/dfca4f9519e6c55364d791f26fcde374cb67fb67
Author: Veera <32646674+veera-sivarajan at users.noreply.github.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
Log Message:
-----------
[SimplifyLibCalls][NFC] Fix Typo in Header Comment (#114314)
Commit: 810150bcb64b59bd90364f981e72b9f58137adc4
https://github.com/llvm/llvm-project/commit/810150bcb64b59bd90364f981e72b9f58137adc4
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Log Message:
-----------
[RISCV] Remove the offset numbers from the FixedCSRFIMap. NFC (#129297)
Use the position within the table instead with a little bit of
arithmetic.
Commit: ef1128b48209cf906d6973e71a9b11c5e2bb8fdd
https://github.com/llvm/llvm-project/commit/ef1128b48209cf906d6973e71a9b11c5e2bb8fdd
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
Log Message:
-----------
AMDGPU: Sort an instruction definition by opcode (#129350)
Commit: 8d1f385d40634fcffabe701334efb90c57243636
https://github.com/llvm/llvm-project/commit/8d1f385d40634fcffabe701334efb90c57243636
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M llvm/include/llvm/ADT/SCCIterator.h
Log Message:
-----------
[ADT] Avoid repeated hash lookups (NFC) (#129355)
Commit: 83d2c68fc151ab50e005ecd36edb53a2af89e71c
https://github.com/llvm/llvm-project/commit/83d2c68fc151ab50e005ecd36edb53a2af89e71c
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
Log Message:
-----------
Prune a redundant include "RISCVISelDAGToDAG.h" (fixup for #128978)
Seems it is not affected.
Commit: cab738bea1a6d06c6aaebc0e9ad5954a2c5c1e0b
https://github.com/llvm/llvm-project/commit/cab738bea1a6d06c6aaebc0e9ad5954a2c5c1e0b
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
R clang/test/CoverageMapping/mcdc-error-nests.cpp
A clang/test/CoverageMapping/mcdc-nested-expr.cpp
Log Message:
-----------
[MC/DC] Update CoverageMapping tests (#125404)
To resolve the error, rename mcdc-error-nests.cpp ->
mcdc-nested-expr.cpp at first.
- `func_condop` A corner case that contains close decisions.
- `func_expect` Uses `__builtin_expect`. (#124565)
- `func_lnot` Contains logical not(s) `!` among MC/DC binary operators.
(#124563)
Commit: 7e8a06cfa4a2951b8ee77e19e34926e6e535b4d1
https://github.com/llvm/llvm-project/commit/7e8a06cfa4a2951b8ee77e19e34926e6e535b4d1
Author: Fangrui Song <i at maskray.me>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M lld/ELF/Driver.cpp
M lld/test/ELF/aarch64-bti-pac-cli-error.s
M lld/test/ELF/aarch64-feature-bti.s
M lld/test/ELF/aarch64-feature-pauth.s
M lld/test/ELF/i386-feature-cet.s
M lld/test/ELF/x86-64-feature-cet.s
Log Message:
-----------
[ELF] Make -z *-report=unknown error message conventional
Commit: 24921a9cb5f127f138ad7a36b10aee81b53bf4bf
https://github.com/llvm/llvm-project/commit/24921a9cb5f127f138ad7a36b10aee81b53bf4bf
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M mlir/lib/IR/Types.cpp
Log Message:
-----------
[mlir] Remove duplicate comment(NFC) (#128304)
The comments in the source file duplicate the documentation already
present in the header file `mlir/IR/Types.h`.
https://github.com/llvm/llvm-project/blob/876174ffd7533dc220f94721173bb767b659fa7f/mlir/include/mlir/IR/Types.h#L136-L141
Commit: f611e95d30df6e8e25818008c8abb57b7ebb8f5c
https://github.com/llvm/llvm-project/commit/f611e95d30df6e8e25818008c8abb57b7ebb8f5c
Author: Jerry-Ge <jerry.ge at arm.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
Log Message:
-----------
[mlir][tosa] Add missing controlflow extension comment (#129338)
A previous patch(#128216) that added the support for the control flow
extension overlooked adding a comment. This patch adds the comment.
Signed-off-by: Luke Hutton <luke.hutton at arm.com>
Co-authored-by: Luke Hutton <luke.hutton at arm.com>
Commit: 8f4d2e02bea6933d7f4c35f577bf5780bad93beb
https://github.com/llvm/llvm-project/commit/8f4d2e02bea6933d7f4c35f577bf5780bad93beb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
Log Message:
-----------
[VectorCombine] scalarizeLoadExtract - add debug message for match + cost-comparison
Helps with debugging to show to that the fold found the match, and shows the old + new costs to indicate whether the fold was/wasn't profitable.
Commit: 0751418024442ac97b8ff484c01f9386aa5723b8
https://github.com/llvm/llvm-project/commit/0751418024442ac97b8ff484c01f9386aa5723b8
Author: João Gouveia <jtalonegouveia at gmail.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/combine-i64-trunc-srl-add.ll
Log Message:
-----------
[X86] Extend `combinei64TruncSrlAdd` to handle patterns with `or` and `xor` (#128435)
As discussed in #126448, the fold implemented by #126448 / #128353 can
be extended to operations other than `add`. This patch extends the fold
performed by `combinei64TruncSrlAdd` to include `or` and `xor` (proof:
https://alive2.llvm.org/ce/z/AXuaQu). There's no need to extend it to
`sub` and `and`, as similar folds are already being performed for those
operations.
CC: @phoebewang @RKSimon
Commit: 65f105b6cf4a36e45565b5ab7eafa1904497f61e
https://github.com/llvm/llvm-project/commit/65f105b6cf4a36e45565b5ab7eafa1904497f61e
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M libcxx/docs/Status/Cxx23Issues.csv
M libcxx/include/__iterator/istream_iterator.h
M libcxx/include/iterator
M libcxx/test/std/iterators/stream.iterators/istream.iterator/istream.iterator.cons/copy.pass.cpp
Log Message:
-----------
[libc++] Implements LWG3600 Making istream_iterator copy constructor trivial is an ABI break (#127343)
Closes: #105003
Commit: d2b09e21bccac364962cacdd63e63c1d23ce87ac
https://github.com/llvm/llvm-project/commit/d2b09e21bccac364962cacdd63e63c1d23ce87ac
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M libcxx/docs/Status/Cxx17Issues.csv
M libcxx/include/initializer_list
A libcxx/test/std/language.support/support.initlist/support.initlist.syn/specialization.verify.cpp
Log Message:
-----------
[libc++] Prohibits initializer_list specializations. (#128042)
This relies on Clang's no_specializations attribute which is not
supported by GCC.
Implements:
- LWG2129: User specializations of std::initializer_list
Fixes: #126270
Commit: 2709366f75b054e2cba4f61310de5a9605f4aa24
https://github.com/llvm/llvm-project/commit/2709366f75b054e2cba4f61310de5a9605f4aa24
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/X86/vselect-constants.ll
Log Message:
-----------
[DAGCombiner] Don't ignore N2's undef elements in `foldVSelectOfConstants` (#129272)
Since N2 will be reused in the fold, we cannot skip N2's undef elements
if the corresponding element in N1 is well-defined.
For example:
```
t2: v4i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<0>, Constant:i32<0>, Constant:i32<0>
t24: v4i32 = BUILD_VECTOR undef:i32, undef:i32, Constant:i32<1>, undef:i32
t11: v4i32 = vselect t8, t2, t10
```
Before this patch, we fold t11 into:
```
t26: v4i32 = sign_extend t8
t27: v4i32 = add t26, t24
```
The last element of t27 is incorrect.
Closes https://github.com/llvm/llvm-project/issues/129181.
Commit: 39edcf9126ee1709753728205d2ed211aac4f7b3
https://github.com/llvm/llvm-project/commit/39edcf9126ee1709753728205d2ed211aac4f7b3
Author: R <rqou at berkeley.edu>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M clang/lib/Driver/ToolChains/WebAssembly.cpp
M clang/test/Driver/wasm-toolchain.c
Log Message:
-----------
[WebAssembly] Make WASI -threads environment behave as -pthread (#129164)
If the user specifies a target triple of wasm32-wasi-threads, then
enable all of the same flags as if `-pthread` were passed. This helps
prevent user error, as the whole point of selecting this target is to
gain pthread support.
The reverse does not happen (passing `-pthread` does not alter the
target triple) so as to not interfere with custom environments and/or
custom multilib setups.
Commit: 9f37cdca52331c4feebcadebb921e7e975c3d0e3
https://github.com/llvm/llvm-project/commit/9f37cdca52331c4feebcadebb921e7e975c3d0e3
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
Log Message:
-----------
[VPlan] Update VPTransformState accessors to take const VPValue (NFC).
This will enable using const VPValue * pointers are in more places.
Commit: 60b44d31afe53556ec707dc855983b93971d83c4
https://github.com/llvm/llvm-project/commit/60b44d31afe53556ec707dc855983b93971d83c4
Author: Arnab Dutta <85476402+arnab-polymage at users.noreply.github.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M mlir/lib/IR/AffineExpr.cpp
M mlir/test/Dialect/Affine/simplify-structures.mlir
Log Message:
-----------
[MLIR][Affine] Fix bug in `simplifySemiAffine` utility (#129200)
Whenever `symbolicDivide` returns nullptr when called from inside
`simplifySemiAffine` we substitute the result with the original
expression (`expr`). nullptr simply indicates that the floordiv
expression cannot be simplified further.
Fixes: https://github.com/llvm/llvm-project/issues/122231
Commit: 37374fbcd33c6b96637d0d6195e269a46f0daa04
https://github.com/llvm/llvm-project/commit/37374fbcd33c6b96637d0d6195e269a46f0daa04
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
M llvm/test/Transforms/InstCombine/load.ll
Log Message:
-----------
[InstCombine] Simplify nonnull phi nodes (#128466)
Fix some regressions caused by
https://github.com/llvm/llvm-project/pull/128111.
Compile-time impact:
https://llvm-compile-time-tracker.com/compare.php?from=1e0e4169dd00bf8a37cef8d74d0add7861982c4e&to=3a27268e264826ef9cf493f645507e490f05e7f3&stat=instructions%3Au
Commit: cc5d8a4b2fc765c3c432f1ad0b185dae518d41bd
https://github.com/llvm/llvm-project/commit/cc5d8a4b2fc765c3c432f1ad0b185dae518d41bd
Author: Sebastian Schaller <4145046+sschaller at users.noreply.github.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/emutls-fallback.ll
Log Message:
-----------
[AArch64] fall back to SDAG for instructions with emulated TLS variables (#129215)
Fixes #126200
At the moment, GlobalISel is missing an implementation for emulated TLS
variables.
I fixed the issue by falling back to SDAG in this case, as I currently
don't have the knowledge to implement it myself.
Co-authored-by: Schaller, Sebastian <sebastian.schaller at dentsplysirona.com>
Commit: 00414c3371701961363f243338e0e848d8066509
https://github.com/llvm/llvm-project/commit/00414c3371701961363f243338e0e848d8066509
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonCopyHoisting.cpp
Log Message:
-----------
[Hexagon] Avoid repeated hash lookups (NFC) (#129357)
Commit: 0bcc37cf1efd563e1683ad79a42b88b9d5d31d9d
https://github.com/llvm/llvm-project/commit/0bcc37cf1efd563e1683ad79a42b88b9d5d31d9d
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp
Log Message:
-----------
[SPIRV] Avoid repeated hash lookups (NFC) (#129358)
Commit: f892dc7440c17ca880359174e7bd1ea599869f7d
https://github.com/llvm/llvm-project/commit/f892dc7440c17ca880359174e7bd1ea599869f7d
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h
Log Message:
-----------
[Transforms] Avoid repeated hash lookups (NFC) (#129359)
Commit: 70af83ff5f87f2b36c5dbbbb050f705ec4389e24
https://github.com/llvm/llvm-project/commit/70af83ff5f87f2b36c5dbbbb050f705ec4389e24
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86LowerAMXType.cpp
Log Message:
-----------
[X86] Avoid repeated hash lookups (NFC) (#129360)
Commit: 70f4e6abf653afadd29e91ef2bfa4b2db46a4013
https://github.com/llvm/llvm-project/commit/70f4e6abf653afadd29e91ef2bfa4b2db46a4013
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/Layer.cpp
Log Message:
-----------
[ExecutionEngine] Avoid repeated hash lookups (NFC) (#129356)
Commit: 88460137d97c0b8d3742203e0173ab9ed6c5c8a7
https://github.com/llvm/llvm-project/commit/88460137d97c0b8d3742203e0173ab9ed6c5c8a7
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
Log Message:
-----------
[memprof] Use llvm::equal in stackFrameIncludesInlinedCallStack (NFC) (#129372)
llvm::equal hides all the iterator manipulation behind the scenes
while reducing the line count.
Commit: 5ddf40fa78705384966c22da78e12134df7bd723
https://github.com/llvm/llvm-project/commit/5ddf40fa78705384966c22da78e12134df7bd723
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/X86/load-extractelement-scalarization.ll
Log Message:
-----------
[VectorCombine] scalarizeLoadExtract - don't create scalar loads if any extract is waiting to be erased (#129375)
If any extract is waiting to be erased, then bail out as this will distort the cost calculation and possibly lead to infinite loops.
Fixes #129373
Commit: bc35510725e5d55f7798cc6eb3be7e5f19c38d59
https://github.com/llvm/llvm-project/commit/bc35510725e5d55f7798cc6eb3be7e5f19c38d59
Author: Veera <32646674+veera-sivarajan at users.noreply.github.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/test/Transforms/InstSimplify/icmp-monotonic.ll
Log Message:
-----------
[InstSimplify] Fold `X * C >= X` to `true` (#129352)
Proof: https://alive2.llvm.org/ce/z/T_ocLy
Discovered in: https://github.com/rust-lang/rust/issues/114386
This PR folds `X * C >= X` to `true` when `C` is known to be non-zero
and `mul` is `nuw`.
Folds for other math operators exist already:
https://llvm-ir.godbolt.org/z/GKcYEf5Kb
Commit: b356a3085be43fda14a9f34f9e81bdf36b73e915
https://github.com/llvm/llvm-project/commit/b356a3085be43fda14a9f34f9e81bdf36b73e915
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
Log Message:
-----------
[Mips] Format some MCTargetDesc files. NFC
In preparation for #127581
Commit: b65e0947cade9bd39036a7700b54c1df4ec00756
https://github.com/llvm/llvm-project/commit/b65e0947cade9bd39036a7700b54c1df4ec00756
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
A llvm/test/MC/Mips/fixup-expr.s
M llvm/test/MC/Mips/imm-operand-err.s
Log Message:
-----------
[Mips] Allow expressions in some immediate operands
e.g.
`addiu $t2, $t3, .Lend-.Lstart-4`
used by libdragon/boot/boot_trampoline.S
To make this work, update a few places:
* AsmParser: When matching a isSImm/isUImm, consider an expression
that does not evaluate to an assemble-time constant an immediate.
* MCCodeEmitter: If this is an I-type instruction and the expression
does not evaluate to an assemble-time constant, append a
`fixup_Mips_AnyImm16`.
TODO: in MipsInstrInfo.td, more `Operand` should switch from the
default `getMachineOpValue` to `getImmOpValue` like RISCV.
* AsmBackend: If the expression does not evaluate to a constant
with assembler layout information, report "unknown relocation type"
like X86. If the result is not within [-32768,65535] (the bound gas
uses when parsing a constant integer for ADDIU)
Fix #126531
Pull Request: https://github.com/llvm/llvm-project/pull/127581
Commit: 9b7b7d60755c914e38337ec43a92497e5c1afef0
https://github.com/llvm/llvm-project/commit/9b7b7d60755c914e38337ec43a92497e5c1afef0
Author: Csanád Hajdú <csanad.hajdu at arm.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/Writer.cpp
A lld/test/ELF/aarch64-execute-only-report.s
A lld/test/ELF/arm-execute-only-report.s
M lld/test/ELF/target-specific-options.s
Log Message:
-----------
[LLD][ELF] Add `-z execute-only-report` that checks PURECODE section flags (#128883)
`-z execute-only-report` checks that all executable sections have either
the SHF_AARCH64_PURECODE or SHF_ARM_PURECODE section flag set on AArch64
and ARM respectively.
Commit: fe187961427674257a9b4012d37b4798e65d1598
https://github.com/llvm/llvm-project/commit/fe187961427674257a9b4012d37b4798e65d1598
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M offload/cmake/caches/AMDGPUBot.cmake
Log Message:
-----------
[Offload][AMDGPU] Enable SPIRV target in build conf (#129323)
Enable the SPIRV backend on the CMake-cache file buildbots.
Commit: 304c053a5c7b8a67f6f3fddf9492971a57901715
https://github.com/llvm/llvm-project/commit/304c053a5c7b8a67f6f3fddf9492971a57901715
Author: Trevor Laughlin <trevor.w.laughlin at gmail.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M clang/bindings/python/clang/cindex.py
M clang/bindings/python/tests/cindex/test_type.py
M clang/docs/ReleaseNotes.rst
M clang/include/clang-c/Index.h
M clang/tools/libclang/CIndexCXX.cpp
M clang/tools/libclang/libclang.map
Log Message:
-----------
[cindex] Add API to query the class methods of a type (#123539)
Inspired by https://github.com/llvm/llvm-project/pull/120300, add a new
API `clang_visitCXXMethods` to libclang (and the Python bindings) which
allows iterating over the class methods of a type.
---------
Co-authored-by: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: 75270e3750db13e20ddbf42df6b7094c6266ed57
https://github.com/llvm/llvm-project/commit/75270e3750db13e20ddbf42df6b7094c6266ed57
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanHCFGBuilder.cpp
M llvm/lib/Transforms/Vectorize/VPlanHCFGBuilder.h
M llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp
Log Message:
-----------
[VPlan] Don't print VPlan DT after VPlan construction. (NFC)
Remove unnecessary code to just print VPlan dominator tree.
Commit: 038731c709c665634714275996559c21f36372f2
https://github.com/llvm/llvm-project/commit/038731c709c665634714275996559c21f36372f2
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/docs/UndefinedBehaviorSanitizer.rst
M clang/include/clang/Basic/Sanitizers.def
M clang/lib/Driver/SanitizerArgs.cpp
M clang/test/Driver/fsanitize.c
M clang/test/Driver/sanitizer-ld.c
Log Message:
-----------
[ubsan] Remove -fsanitizer=vptr from -fsanitizer=undefined (#121115)
This makes `undefined` more consistent.
`vptr` check adds additional constraints:
1. trap is off, or silently disabled
2. rtti is no, or compilation error
3. c++abi, or linking error
So it's not obvious if `-fsanitizer=undefined`
will have it on.
https://discourse.llvm.org/t/rfc-remove-vptr-from-undefined/83830
Commit: 872e4a33884b56384ca1ac92aed135bb0d9cc280
https://github.com/llvm/llvm-project/commit/872e4a33884b56384ca1ac92aed135bb0d9cc280
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86FixupKinds.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
Log Message:
-----------
[X86] Replace reloc_global_offset_table8 with R_X86_64_GOTPC64
Commit: 8910e41c86ccf350188369d3cf2b5ce7f8e454e5
https://github.com/llvm/llvm-project/commit/8910e41c86ccf350188369d3cf2b5ce7f8e454e5
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Passes/ADRRelaxationPass.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
Log Message:
-----------
[BOLT][AArch64] Refactor ADR to ADRP+ADD conversion pass. NFCI (#129399)
In preparation of using the new interface in more places, refactor the
ADR conversion pass.
Commit: e3e9c5c8733a87455cf59b91e5e802f427cf5152
https://github.com/llvm/llvm-project/commit/e3e9c5c8733a87455cf59b91e5e802f427cf5152
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/MC/MCParser/AsmParser.cpp
Log Message:
-----------
[MC] Remove unneeded onLabelParsed and onLabelParsed from HLASM
They are only used by ARM and wasm.
Commit: 5e6c0853fd121fa9179fd5edda9ac8649b70aff6
https://github.com/llvm/llvm-project/commit/5e6c0853fd121fa9179fd5edda9ac8649b70aff6
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Log Message:
-----------
[MCParser] Clean up onEndOfFile
and modernize NumOfMacroInstantiations
Commit: 8ec0d60e28f77149eef9c865515b79bc0a5e8f41
https://github.com/llvm/llvm-project/commit/8ec0d60e28f77149eef9c865515b79bc0a5e8f41
Author: Da-Viper <57949090+Da-Viper at users.noreply.github.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py
M lldb/test/API/tools/lldb-dap/variables/children/TestDAP_variables_children.py
M lldb/test/API/tools/lldb-dap/variables/children/main.cpp
M lldb/test/API/tools/lldb-dap/variables/main.cpp
M lldb/tools/lldb-dap/Handler/VariablesRequestHandler.cpp
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[lldb-dap] Add: show return value on step out (#106907)
https://github.com/user-attachments/assets/cff48c6f-37ae-4f72-b881-3eff4178fb3c
Commit: 077497d180c6ad52d7c3ee6c36ee5ae56ac8c1d1
https://github.com/llvm/llvm-project/commit/077497d180c6ad52d7c3ee6c36ee5ae56ac8c1d1
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/include/llvm/MC/MCParser/MCAsmParser.h
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
Log Message:
-----------
[MCParser] Remove parseParenExprOfDepth
Introduced by http://reviews.llvm.org/D9742 as a hack, which then became
unneeded.
Primary test: llvm/test/MC/Mips/memory-offsets.s
Commit: 43c3014ec1eda1d14d836f19395f0232c06f4536
https://github.com/llvm/llvm-project/commit/43c3014ec1eda1d14d836f19395f0232c06f4536
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/MC/MCParser/MasmParser.cpp
Log Message:
-----------
[llvm-ml] Remove unused parser functions
Commit: b6d5fa05ada6e51ede32c62ff47f046ca5085d28
https://github.com/llvm/llvm-project/commit/b6d5fa05ada6e51ede32c62ff47f046ca5085d28
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/MC/MCParser/MasmParser.cpp
Log Message:
-----------
[llvm-ml] Remove unused DWARF/Mach-O/ARM If-Then functions
Commit: 83941577cf82d0831d2e363438b6517ff2421e5c
https://github.com/llvm/llvm-project/commit/83941577cf82d0831d2e363438b6517ff2421e5c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/test/tools/llvm-rc/windres-preproc.test
Log Message:
-----------
llvm-rc: Relax error message checked in test (#129243)
In the fork path, it does not print the piece about posix_spawn failed
Part of #129208
Commit: a0540e6c98972954f42d3b72d70976d8286113ea
https://github.com/llvm/llvm-project/commit/a0540e6c98972954f42d3b72d70976d8286113ea
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/unittests/Support/ProgramTest.cpp
Log Message:
-----------
unittests: Use EXPECT_ instead of ASSERT_ in a few tests (#129251)
Commit: 5a11912ece2731eb9c50f80fdfd75bd1dfc2ebc8
https://github.com/llvm/llvm-project/commit/5a11912ece2731eb9c50f80fdfd75bd1dfc2ebc8
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M bolt/include/bolt/Core/BinaryContext.h
M bolt/include/bolt/Passes/PatchEntries.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Passes/PatchEntries.cpp
Log Message:
-----------
[BOLT] Refactor interface for creating instruction patches. NFCI (#129404)
Add BinaryContext::createInstructionPatch() interface for patching parts
of the original binary with new instruction sequences. Refactor
PatchEntries pass to use the new interface.
Commit: 1b1dc505057322f4fa1110ef4f53c44347f52986
https://github.com/llvm/llvm-project/commit/1b1dc505057322f4fa1110ef4f53c44347f52986
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/include/llvm/MC/MCParser/MCAsmParser.h
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCParser/MCAsmParserExtension.cpp
M llvm/test/MC/AsmParser/directive_loc.s
M llvm/test/MC/COFF/cv-errors.s
Log Message:
-----------
[MCParser] Improve parseIntToken error message
Add a default argument, which is more readable than existing call sites
and encourages new call sites to omit the argument.
Omit " in ... directive" since this the error message includes the line.
Commit: 74638f16349768c5ddde0f2dd43715471d5de910
https://github.com/llvm/llvm-project/commit/74638f16349768c5ddde0f2dd43715471d5de910
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M bolt/test/X86/Inputs/define_bar.s
M lld/test/ELF/linkerscript/lma-align.test
M lld/test/ELF/linkerscript/section-address-align.test
M lld/test/ELF/linkerscript/section-align2.test
Log Message:
-----------
[test] Replace .data.rel.ro with .section .data.rel.ro,"aw"
to avoid using the extension unsupported by gas.
Commit: 99ff3d0bcb2781f6bb7fe78e7d970d072f2f901f
https://github.com/llvm/llvm-project/commit/99ff3d0bcb2781f6bb7fe78e7d970d072f2f901f
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/MC/MCParser/ELFAsmParser.cpp
M llvm/test/MC/ELF/elf_directive_section.s
Log Message:
-----------
[MCParser] Remove some section directive not supported by gas
and not emitted by AsmPrinter.
The intention was to remove `.eh_frame`, which had the wrong
section flags. Let's also remove .data.rel and .data.rel.ro
but keep other extensions like .rodata
Commit: 81a8b5c579acc7597fdb1069355e733aaa7466d4
https://github.com/llvm/llvm-project/commit/81a8b5c579acc7597fdb1069355e733aaa7466d4
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-01 (Sat, 01 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/MachineSink.cpp
Log Message:
-----------
[MachineSink] Use Register and MCRegUnit. NFC
Commit: 2c1e9f14be32c30f6f561274292bef1f52635f82
https://github.com/llvm/llvm-project/commit/2c1e9f14be32c30f6f561274292bef1f52635f82
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/Descriptor.cpp
M clang/lib/AST/ByteCode/Descriptor.h
M clang/lib/AST/ByteCode/DynamicAllocator.cpp
M clang/lib/AST/ByteCode/Program.cpp
M clang/unittests/AST/ByteCode/toAPValue.cpp
Log Message:
-----------
[clang][bytecode] Explicit composite array descriptor types (#129376)
When creating descriptor for array element types, we only save the
original source, e.g. int[2][2][2]. So later calls to getType() of the
element descriptors will also return int[2][2][2], instead of e.g.
int[2][2] for the second dimension.
Fix this by explicitly tracking the array types.
The last attached test case used to have an lvalue offset of 32 instead
of 24.
We should do this for more desriptor types though and not just composite
array, but I'm leaving that to a later patch.
Commit: 69c7336c77f80b8f3417f2fb5143cbaa2fcb1c2a
https://github.com/llvm/llvm-project/commit/69c7336c77f80b8f3417f2fb5143cbaa2fcb1c2a
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/Analysis/ProfileSummaryInfo.cpp
Log Message:
-----------
[Analysis] Avoid repeated hash lookups (NFC) (#129417)
Commit: 2bbb394a9820aea28258de974acfafec4a9741a9
https://github.com/llvm/llvm-project/commit/2bbb394a9820aea28258de974acfafec4a9741a9
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
Log Message:
-----------
[CodeGen] Avoid repeated hash lookups (NFC) (#129418)
Commit: c1211d5cc41fe245245a33e8a69389ea618ecec8
https://github.com/llvm/llvm-project/commit/c1211d5cc41fe245245a33e8a69389ea618ecec8
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/include/llvm/Transforms/IPO/ProfiledCallGraph.h
Log Message:
-----------
[IPO] Avoid repeated hash lookups (NFC) (#129419)
Commit: 4eef3de58840a62042d727a764c73ae2edc98c8f
https://github.com/llvm/llvm-project/commit/4eef3de58840a62042d727a764c73ae2edc98c8f
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/Target/Mips/Mips16ISelLowering.cpp
Log Message:
-----------
[Mips] Avoid repeated hash lookups (NFC) (#129420)
Commit: 1fd014c13d29b45031d13389b8812d9162abd419
https://github.com/llvm/llvm-project/commit/1fd014c13d29b45031d13389b8812d9162abd419
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
Log Message:
-----------
[SPIRV] Avoid repeated hash lookups (NFC) (#129421)
Commit: 4b3f0fa7e7af69a514d7b855cff523539082b292
https://github.com/llvm/llvm-project/commit/4b3f0fa7e7af69a514d7b855cff523539082b292
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
Log Message:
-----------
[llvm-jitlink] Avoid repeated hash lookups (NFC) (#129422)
Commit: 4a8412d4302e15db28a24b80af6902b9e267991b
https://github.com/llvm/llvm-project/commit/4a8412d4302e15db28a24b80af6902b9e267991b
Author: AdityaK <hiraditya at msn.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M libcxx/test/std/numerics/numeric.ops/numeric.ops.gcd/gcd.pass.cpp
Log Message:
-----------
[libc++] Add tests for gcd that result in something other than zero or one (#129395)
@colincross identified gcd does not have a single case whose answer is
not 0, 1, or the smaller of the two inputs.
Commit: fa5db05ca36a732bffb8128ff017c575ec6e1201
https://github.com/llvm/llvm-project/commit/fa5db05ca36a732bffb8128ff017c575ec6e1201
Author: A. Jiang <de34 at live.cn>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M libcxx/test/std/thread/futures/futures.async/thread_create_failure.pass.cpp
Log Message:
-----------
[libc++][test] XFAIL for FreeBSD in thread_create_failure.pass.cpp (#129413)
Per https://man.freebsd.org/cgi/man.cgi?query=setrlimit, FreeBSD's
`setrlimit` seems to limit the number of processes, not threads via
`RLIMIT_NPROC`. So this test should be XFAIL for FreeBSD.
Commit: f937b17e8570082d4710b6dca7a91b5c235c1c70
https://github.com/llvm/llvm-project/commit/f937b17e8570082d4710b6dca7a91b5c235c1c70
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
Log Message:
-----------
[LV] Don't query SCEV for non-invariant values in cost model.
This fixes a divergence between VPlan and legacy cost model, matching
behavior further up in getInstructionCost as well.
Fixes https://github.com/llvm/llvm-project/issues/129236.
Commit: 416c7b370e3285b06b36a0b853b70070b8741f10
https://github.com/llvm/llvm-project/commit/416c7b370e3285b06b36a0b853b70070b8741f10
Author: JP Hafer <146973677+jph-13 at users.noreply.github.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/include/llvm/TargetParser/ARMTargetParser.h
Log Message:
-----------
[ARM] Remove unneeded global inits (NFCI) (#129299)
Theses consts in ASMTargetParser were causing unnecessary global
initialization fuctions.
_GLOBAL__sub_I_ARMTargetParser.cpp
_GLOBAL__sub_I_Triple.cpp
Both functions init the same consts. I messed up the first PR on this
sorry.
Commit: 60afce2df97d1f8fd78405a039e8e818c5154565
https://github.com/llvm/llvm-project/commit/60afce2df97d1f8fd78405a039e8e818c5154565
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-values.cpp
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
M clang/unittests/Analysis/ExprMutationAnalyzerTest.cpp
Log Message:
-----------
[clang-tidy] fix fp when modifying variant by ``operator[]`` with template in parameters (#128407)
`ArraySubscriptExpr` can switch base and idx. For dependent array
subscript access, we should check both base and idx conservatively.
Commit: ba7e27381f1ce56b46839dca89e5d56ea170714e
https://github.com/llvm/llvm-project/commit/ba7e27381f1ce56b46839dca89e5d56ea170714e
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Use VP_CLASSOF_IMPL in VPWidenRecipe. (NFC)
Commit: ac8b5a9e47a550f4171020f619b51b69310766d5
https://github.com/llvm/llvm-project/commit/ac8b5a9e47a550f4171020f619b51b69310766d5
Author: Amir Bishara <139038766+amirBish at users.noreply.github.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-using-interface.mlir
Log Message:
-----------
[mlir][scf]-Fix reverse iterator overflow in loop traversal (#128421)
Fix a bug in method `getUntiledProducerFromSliceSource` where address
sanitizer fails compilation on heap
buffer overflow for accessing value out of the iteration range.
This PR fixes the issue and adds a lit test to reproduce it.
Commit: f858ac7acc33ac6c1a32510b9938d63a59276cc2
https://github.com/llvm/llvm-project/commit/f858ac7acc33ac6c1a32510b9938d63a59276cc2
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M lld/test/COFF/autoimport-arm64-data.s
M lld/test/COFF/autoimport-arm64ec-data.test
Log Message:
-----------
[LLD][COFF] Correct relocation size comments in autoimport tests (NFC) (#129403)
Commit: c6598f6ddf62e88af6c4c20b12264503ad11f234
https://github.com/llvm/llvm-project/commit/c6598f6ddf62e88af6c4c20b12264503ad11f234
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M lld/COFF/Driver.cpp
M lld/COFF/Writer.cpp
A lld/test/COFF/autoimport-arm64x-data.test
Log Message:
-----------
[LLD][COFF] Add support for autoimports on ARM64X (#129282)
Commit: 8eba02288634e5b14f5d2a13763ddfd0ea89068b
https://github.com/llvm/llvm-project/commit/8eba02288634e5b14f5d2a13763ddfd0ea89068b
Author: Billy Laws <blaws05 at gmail.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/IR/EHPersonalities.cpp
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
A llvm/test/CodeGen/AArch64/arm64ec-eh.ll
Log Message:
-----------
[CodeGen][ARM64EC] Mangle EH personality handler names (#121652)
Commit: d403f33886a3eda18e1a7368e6d5607b1fd83f0c
https://github.com/llvm/llvm-project/commit/d403f33886a3eda18e1a7368e6d5607b1fd83f0c
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M lld/COFF/Driver.cpp
A lld/test/COFF/gc-dwarf-eh-arm64x.s
Log Message:
-----------
[LLD][COFF] Mark personality functions as live in both symbol tables on ARM64X (#129295)
Commit: f5f5286da3a64608b5874d70b32f955267039e1c
https://github.com/llvm/llvm-project/commit/f5f5286da3a64608b5874d70b32f955267039e1c
Author: A. Jiang <de34 at live.cn>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/include/tuple
R libcxx/test/libcxx/utilities/no_specializations.verify.cpp
A libcxx/test/libcxx/utilities/tuple/no_specializations.verify.cpp
A libcxx/test/libcxx/utilities/variant/no_specializations.verify.cpp
Log Message:
-----------
[libc++] Implement LWG3990 for Clang (#128834)
This patch adds `[[_Clang::__no_specializations__]]` to `tuple`, with
warning/error suppressed for `tuple<>`.
Commit: 376ffec876acddb95fabf4fac30a8f77652f54d2
https://github.com/llvm/llvm-project/commit/376ffec876acddb95fabf4fac30a8f77652f54d2
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M libcxx/test/std/utilities/format/format.formattable/concept.formattable.compile.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.locking/enable_nonlocking_formatter_optimization.compile.pass.cpp
Log Message:
-----------
[libc++][format] Enables formattable tests for chrono formatters. (#128356)
These were forgotten when these types were implemented.
Commit: 00e74632051688e194685e91119fc607f1fb110a
https://github.com/llvm/llvm-project/commit/00e74632051688e194685e91119fc607f1fb110a
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M libcxx/include/chrono
Log Message:
-----------
[libc++][chrono][doc] Use stable names in synopsis. (#129381)
Fixes: #80895
Commit: 3a11d5a8dfb6c95a5ba0c6b4463e15494005a369
https://github.com/llvm/llvm-project/commit/3a11d5a8dfb6c95a5ba0c6b4463e15494005a369
Author: isuckatcs <65320245+isuckatcs at users.noreply.github.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/lib/Lex/PPExpressions.cpp
A clang/test/Preprocessor/warn-macro-undef-true.c
Log Message:
-----------
[clang][diagnostics] add `-Wundef-true` warning option (#128265)
New option `-Wundef-true` added and enabled by default to warn when `true` is used in the C preprocessor without being defined before C23.
Commit: 6d847b1aada50d59c3e29f2e7eff779c0ee8182c
https://github.com/llvm/llvm-project/commit/6d847b1aada50d59c3e29f2e7eff779c0ee8182c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/include/llvm/CodeGen/FastISel.h
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/utils/TableGen/FastISelEmitter.cpp
Log Message:
-----------
[FastISel] Use Register. NFC
Commit: 18e09da2552d99a641b8257e22b4067730cdb2bc
https://github.com/llvm/llvm-project/commit/18e09da2552d99a641b8257e22b4067730cdb2bc
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/include/llvm/MC/MCAsmInfo.h
M llvm/include/llvm/MC/MCAsmMacro.h
M llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
M llvm/lib/MC/MCParser/AsmLexer.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCParser/MCAsmLexer.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
M llvm/test/MC/Mips/expr1.s
M llvm/test/MC/Mips/macro-aliases-invalid-wrong-error.s
Log Message:
-----------
[Mips] Rework relocation expression parsing
A relocation expression might be used in an immediate operand or a
memory offset. https://reviews.llvm.org/D23110 , which intended to
generalize chained relocation operators (%hi(%neg(%gp_rel(x)))),
inappropriated introduced intrusive changes to the generic code. This
patch drops the intrusive changes and significantly simplifies the code.
The new style is similar to pre-D23110 but much cleaner.
Some weird expressions allowed by gas are not supported for simplicity,
e.g. "%lo foo", "(%lo(foo))", "%lo(foo)+1".
"(%lo(foo))", while previously parsed, is not used in practice.
"%lo(foo)+1" and "%lo(2*4)+foo" were previously parsed but would lead to
an error anyway as the expression is not relocatable
(`evaluateSymbolicAdd` does not fold the Add when RefKind are
different).
Commit: a9f02a49979c84cd8c1b75acfe7e7cef56cb8623
https://github.com/llvm/llvm-project/commit/a9f02a49979c84cd8c1b75acfe7e7cef56cb8623
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/CFIInstrInserter.cpp
Log Message:
-----------
[CFIInstrInserter] Don't store Dwarf register number in Register. NFC
Commit: 527af302b90eaf686959dfe569dceadd8e58d611
https://github.com/llvm/llvm-project/commit/527af302b90eaf686959dfe569dceadd8e58d611
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M clang/cmake/caches/BOLT.cmake
M clang/tools/driver/CMakeLists.txt
M clang/utils/perf-training/perf-helper.py
Log Message:
-----------
Add support for dynamic libraries in CLANG_BOLT (#127020)
Commit: 20362c51dd94a1dfbf1c7e8327a9b6280609c572
https://github.com/llvm/llvm-project/commit/20362c51dd94a1dfbf1c7e8327a9b6280609c572
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
Log Message:
-----------
[TwoAddressInstructionPass] Use Register. NFC
Commit: 2fb7f09f6323c69e48e0e5fe86a34a6bec87dbdd
https://github.com/llvm/llvm-project/commit/2fb7f09f6323c69e48e0e5fe86a34a6bec87dbdd
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
Log Message:
-----------
[FastISel] Use Register. NFC
Commit: 1d9207fda0fef28cb304ad922fe8223b01b18889
https://github.com/llvm/llvm-project/commit/1d9207fda0fef28cb304ad922fe8223b01b18889
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/TailDuplicator.cpp
Log Message:
-----------
[TailDuplicator] Use Register. NFC
Commit: fd3326b65f83968541d7df32c07c12892bd2dc04
https://github.com/llvm/llvm-project/commit/fd3326b65f83968541d7df32c07c12892bd2dc04
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
M llvm/lib/CodeGen/AggressiveAntiDepBreaker.h
Log Message:
-----------
[AggressiveAntiDepBreaker] Use MCRegister. NFC
Commit: dcca3f407cf138eee8d935fdbe24b4ccd1970968
https://github.com/llvm/llvm-project/commit/dcca3f407cf138eee8d935fdbe24b4ccd1970968
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
M llvm/lib/CodeGen/AggressiveAntiDepBreaker.h
Log Message:
-----------
Revert "[AggressiveAntiDepBreaker] Use MCRegister. NFC"
This reverts commit fd3326b65f83968541d7df32c07c12892bd2dc04.
Getting a failure on the buildbots
Commit: 31bf16a7a2e1f5e783af9055fa2a1d815c090da2
https://github.com/llvm/llvm-project/commit/31bf16a7a2e1f5e783af9055fa2a1d815c090da2
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/include/llvm/MC/MCStreamer.h
M llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFTargetStreamer.cpp
Log Message:
-----------
[MC] Add MCTargetStreamer::getContext to simplify code
Commit: 60486292b79885b7800b082754153202bef5b1f0
https://github.com/llvm/llvm-project/commit/60486292b79885b7800b082754153202bef5b1f0
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/include/llvm/MC/MCAsmInfo.h
M llvm/include/llvm/MC/MCFixup.h
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/MC/MCAsmBackend.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCNullStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.h
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/test/MC/Mips/relocation.s
M llvm/tools/llvm-mca/CodeRegionGenerator.h
Log Message:
-----------
[MC] Move MIPS-specific gprel/tprel/dtprel from MCStreamer to MipsTargetStreamer
https://reviews.llvm.org/D23669 inappropriately added MIPS-specific
dtprel/tprel directives to MCStreamer. In addition,
llvm-mc -filetype=null parsing these directives will crash.
This patch moves these functions to MipsTargetStreamer and fixes
-filetype=null.
gprel32 and gprel64, called by AsmPrinter, are moved to
MCTargetStreamer.
Commit: ca0612c383bc1c487b8dabff9e5830af173a7da8
https://github.com/llvm/llvm-project/commit/ca0612c383bc1c487b8dabff9e5830af173a7da8
Author: A. Jiang <de34 at live.cn>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M libcxx/include/locale
A libcxx/test/std/localization/locale.categories/category.monetary/locale.money.get/locale.money.get.members/get_long_double_overlong.pass.cpp
Log Message:
-----------
[libc++] Fix `money_get::do_get` with huge input (#126273)
`money_get::do_get` needs to be fixed to handle extremely huge input
(e.g. more than 100 digits).
1. `__double_or_nothing` needs to copy the contents of the stack buffer
on the initial allocation.
2. The `sscanf` call in `do_get` needs to scan the dynamic buffer if
dynamic allocation happens.
Commit: f745cb68f1adae854fe1ff7cc43b4bbe36db3ac2
https://github.com/llvm/llvm-project/commit/f745cb68f1adae854fe1ff7cc43b4bbe36db3ac2
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
M llvm/lib/CodeGen/AggressiveAntiDepBreaker.h
Log Message:
-----------
[AggressiveAntiDepBreaker] Use MCRegister. NFC
Commit: 0c5d709301b25b588ccb9cfb4d9c219cc5bdcaf1
https://github.com/llvm/llvm-project/commit/0c5d709301b25b588ccb9cfb4d9c219cc5bdcaf1
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/include/llvm/CodeGen/AsmPrinter.h
M llvm/include/llvm/MC/MCAsmInfo.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.h
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.h
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
Log Message:
-----------
Move MIPS-specific GPRel32Directive and EK_GPRel32BlockAddress from generic code to Mips/
Follow-up to 60486292b79885b7800b082754153202bef5b1f0
gprel/gprel64 functions can now be moved from MCTargetStreamer
to MipsTargetStreamer.
Commit: b02cfbd73c8007aa52f6f1e2df557d742b6be151
https://github.com/llvm/llvm-project/commit/b02cfbd73c8007aa52f6f1e2df557d742b6be151
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/MC/MCParser/MasmParser.cpp
Log Message:
-----------
[llvm-ml] Remove unused VariantKind parsing code
Commit: d1fd3698a9b755250f622fd1b14c57a27e2a9d77
https://github.com/llvm/llvm-project/commit/d1fd3698a9b755250f622fd1b14c57a27e2a9d77
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M flang/include/flang/Evaluate/tools.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Semantics/assignment.cpp
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
Log Message:
-----------
[flang][cuda] Allow unsupported data transfer to be done on the host (#129160)
Some data transfer marked as unsupported can actually be deferred to an
assignment on the host when the variables involved are unified or
managed.
Commit: 3c80d9b8dda38162016f72defe24baf79d4cf0ef
https://github.com/llvm/llvm-project/commit/3c80d9b8dda38162016f72defe24baf79d4cf0ef
Author: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/IR/Instruction.cpp
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-unoptimized-debug-data.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/after-inlining.ll
M llvm/test/Transforms/LoopDeletion/diundef.ll
M llvm/test/Transforms/MergeFunc/mergefunc-preserve-debug-info.ll
M llvm/test/Transforms/SLPVectorizer/X86/debug-info-salvage.ll
M llvm/test/Transforms/SROA/alignment.ll
M llvm/test/Transforms/SROA/vector-promotion.ll
M llvm/test/Transforms/SafeStack/X86/debug-loc2.ll
Log Message:
-----------
[Instruction] Set metadata to `poison` on deletion (#129449)
Represent extant metadata uses of a deleted instruction with `poison`
instead of `undef`.
Commit: 8c7c791284877e36f73c41ffa56b52c13e613993
https://github.com/llvm/llvm-project/commit/8c7c791284877e36f73c41ffa56b52c13e613993
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/MC/MCExpr.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
Log Message:
-----------
[MCParser] Use getVariantKindForName and move PPC specific VariantKind to PowerPC/
Commit: 14951a5a3120e50084b3c5fb217e2d47992a24d1
https://github.com/llvm/llvm-project/commit/14951a5a3120e50084b3c5fb217e2d47992a24d1
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/MC/MCExpr.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
M llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
M llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
Log Message:
-----------
[MCParser] Extract some VariantKind from getVariantKindForName
All VariantKinds except VK_None/VK_Invalid are target-specific (e.g. a
target may not support "@plt" even if it is widely available).
Move the parsers to lib/Target to ensure that VariantKind from unrelated
targets will not be parsed.
Commit: f5f3612453fb3568a76056daea41f67df82636af
https://github.com/llvm/llvm-project/commit/f5f3612453fb3568a76056daea41f67df82636af
Author: Ami-zhang <zhanglimin at loongson.cn>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/Basic/Targets.cpp
M clang/lib/Driver/ToolChains/OHOS.cpp
A clang/test/Driver/Inputs/ohos_native_tree/llvm/lib/clang/x.y.z/lib/loongarch64-linux-ohos/.keep
A clang/test/Driver/Inputs/ohos_native_tree/llvm/lib/clang/x.y.z/lib/loongarch64-linux-ohos/clang_rt.crtbegin.o
A clang/test/Driver/Inputs/ohos_native_tree/llvm/lib/clang/x.y.z/lib/loongarch64-linux-ohos/clang_rt.crtend.o
A clang/test/Driver/Inputs/ohos_native_tree/llvm/lib/clang/x.y.z/lib/loongarch64-linux-ohos/libclang_rt.builtins.a
A clang/test/Driver/Inputs/ohos_native_tree/sysroot/usr/include/loongarch64-linux-ohos/.keep
A clang/test/Driver/Inputs/ohos_native_tree/sysroot/usr/lib/loongarch64-linux-ohos/.keep
M clang/test/Driver/ohos.c
M clang/test/Preprocessor/ohos.c
Log Message:
-----------
[clang][LoongArch] Add OHOS target (#127555)
Add support for OHOS on loongarch64.
Commit: cb7030dbe7f3f1947c31b3059958ff3968cc22ff
https://github.com/llvm/llvm-project/commit/cb7030dbe7f3f1947c31b3059958ff3968cc22ff
Author: tangaac <tangyan01 at loongson.cn>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/test/CodeGen/LoongArch/lsx/vec-sext.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll
Log Message:
-----------
[LoongArch] use TypeWidenVector for most illegal vector types (#126456)
`TypeWidenVector` makes an illegal vector a larger one
e.g. in lsx
v2i32 -> v4i32
v4i16 -> v8i16
With this we can make good use of `vilvh`, `vilvl` instructions in
vector `sext`, `zext` in later pr.
Previous action is `TypePromoteInteger`, which replaces integer with a
larger one
e.g. in lsx
v2i32 -> v2i64
v4i16 -> v4i32
Commit: db0e7c72aff622849abbc92c3ed0d06efb8e2d16
https://github.com/llvm/llvm-project/commit/db0e7c72aff622849abbc92c3ed0d06efb8e2d16
Author: Bruno Cardoso Lopes <bruno.cardoso at gmail.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M mlir/include/mlir/Target/LLVMIR/LLVMImportInterface.h
M mlir/lib/Target/LLVMIR/CMakeLists.txt
A mlir/lib/Target/LLVMIR/LLVMImportInterface.cpp
M mlir/test/Target/LLVMIR/Import/import-failure.ll
A mlir/test/Target/LLVMIR/Import/intrinsic-unregistered.ll
Log Message:
-----------
Reapply [MLIR][LLVMIR] Import unregistered intrinsics via llvm.intrin… (#129174)
…sic_call
Original introduced in https://github.com/llvm/llvm-project/pull/128626,
reverted in https://github.com/llvm/llvm-project/pull/128973
Reproduced the issue on a shared lib build locally on Linux, moved
content around to satisfy both static and shared lib builds.
### Original commit message
Currently, the llvm importer can only cover intrinsics that have a first
class representation in an MLIR dialect (arm-neon, etc). This PR
introduces a fallback mechanism that allow "unregistered" intrinsics to
be imported by using the generic `llvm.intrinsic_call` operation. This
is useful in several ways:
1. Allows round-trip the LLVM dialect output lowered from other dialects
(example: ClangIR)
2. Enables MLIR-linking tools to operate on imported LLVM IR without
requiring to add new operations to dozen of different targets.
If multiple dialects implement this interface hook, the last one to
register is the one converting all unregistered intrinsics.
---------
Co-authored-by: Bruno Cardoso Lopes <bcardosolopes at users.noreply.github.com>
Commit: e42ab4c54eca0e792a0ae461481f9acbd0260363
https://github.com/llvm/llvm-project/commit/e42ab4c54eca0e792a0ae461481f9acbd0260363
Author: Jim Lin <jim at andestech.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
A llvm/test/CodeGen/RISCV/rvv/zvbb-demanded-bits.ll
Log Message:
-----------
[RISCV] Handle zvbb instructions in getVectorLowDemandedScalarBits. (#129011)
Commit: cf00ac81ac049cddb80aec1d6d88b8fab4f209e8
https://github.com/llvm/llvm-project/commit/cf00ac81ac049cddb80aec1d6d88b8fab4f209e8
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp
Log Message:
-----------
[Hexagon] Call MCExpr::print with valid MAI
operator<< should be avoided when operands with VariantKind are dumped.
This prepares for the upcoming change that moves target-specific
VariantKind printer to MCAsmInfo.
Commit: e6aae2a4905982c10412e7f35b4f3c940a1a86f5
https://github.com/llvm/llvm-project/commit/e6aae2a4905982c10412e7f35b4f3c940a1a86f5
Author: Oliver Hunt <oliver at apple.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
A clang/test/Analysis/Checkers/WebKit/binding-to-refptr.cpp
Log Message:
-----------
[analyzer] Handle structured bindings in alpha.webkit.UncountedCallArgsChecker (#129424)
Simply add awareness of BindingDecl to the logic for identifying local
assignments.
Commit: 98a640a2faf4d5557e3a949dd87a01ba900745d6
https://github.com/llvm/llvm-project/commit/98a640a2faf4d5557e3a949dd87a01ba900745d6
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/include/llvm/MC/MCAsmInfo.h
M llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
M llvm/lib/MC/MCAsmInfo.cpp
M llvm/lib/MC/MCExpr.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
M llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
M llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
M llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
M llvm/lib/Target/VE/MCTargetDesc/VEMCAsmInfo.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp
Log Message:
-----------
[MC] Move VariantKind info to MCAsmInfo
Follow-up to 14951a5a3120e50084b3c5fb217e2d47992a24d1
* Unify getVariantKindName and getVariantKindForName
* Allow each target to specify the preferred case (albeit ignored in MCParser)
Note: targets that use variant kinds should call MCExpr::print with a
non-null MAI to print variant kinds. operator<< passes a nullptr to
`MCExpr::print`, which should be avoided (e.g. Hexagon; fixed in
commit cf00ac81ac049cddb80aec1d6d88b8fab4f209e8).
Commit: c804e86f558a42f328946331af391d700747fa90
https://github.com/llvm/llvm-project/commit/c804e86f558a42f328946331af391d700747fa90
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/include/clang-c/Index.h
M clang/include/clang/AST/Type.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Specifiers.h
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/Type.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaType.cpp
M clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
M clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
M clang/test/CodeGen/RISCV/riscv-vector-callingconv.c
M clang/test/CodeGen/RISCV/riscv-vector-callingconv.cpp
M clang/tools/libclang/CXType.cpp
M llvm/include/llvm/AsmParser/LLToken.h
M llvm/include/llvm/BinaryFormat/Dwarf.def
M llvm/include/llvm/IR/CallingConv.h
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/Assembler/riscv_vls_cc.ll
M llvm/test/Bitcode/compatibility.ll
Log Message:
-----------
[RISCV][VLS] Support RISCV VLS calling convention (#100346)
This patch adds a function attribute `riscv_vls_cc` for RISCV VLS
calling
convention which takes 0 or 1 argument, the argument is the `ABI_VLEN`
which is the `VLEN` for passing the fixed-vector arguments, it wraps the
argument as a scalable vector(VLA) using the `ABI_VLEN` and uses the
corresponding mechanism to handle it. The range of `ABI_VLEN` is [32,
65536],
if not specified, the default value is 128.
Here is an example of VLS argument passing:
Non-VLS call:
```
void original_call(__attribute__((vector_size(16))) int arg) {}
=>
define void @original_call(i128 noundef %arg) {
entry:
...
ret void
}
```
VLS call:
```
void __attribute__((riscv_vls_cc(256))) vls_call(__attribute__((vector_size(16))) int arg) {}
=>
define riscv_vls_cc void @vls_call(<vscale x 1 x i32> %arg) {
entry:
...
ret void
}
}
```
The first Non-VLS call passes generic vector argument of 16 bytes by
flattened integer.
On the contrary, the VLS call uses `ABI_VLEN=256` which wraps the
vector to <vscale x 1 x i32> where the number of scalable vector
elements
is calaulated by: `ORIG_ELTS * RVV_BITS_PER_BLOCK / ABI_VLEN`.
Note: ORIG_ELTS = Vector Size / Type Size = 128 / 32 = 4.
PsABI PR: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/418
C-API PR: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/68
Commit: e9c8d42b895fe4934a149478788fa020bd69f7bf
https://github.com/llvm/llvm-project/commit/e9c8d42b895fe4934a149478788fa020bd69f7bf
Author: Baranov Victor <70346889+vbvictor at users.noreply.github.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/misc/unused-using-decls.cpp
Log Message:
-----------
[clang-tidy] `misc-unused-using-decls`: add correct handling of `operator""` with template parametes (#129392)
Fixes false-positives when operator"" has template paremetes, e.g.
```cpp
template <char... Ts>
int operator""_r() {
return {};
}
```
Closes https://github.com/llvm/llvm-project/issues/53444.
---------
Co-authored-by: Congcong Cai <congcongcai0907 at 163.com>
Commit: f244b8eed37a12539fb11b76e19ec7a7eb41dccc
https://github.com/llvm/llvm-project/commit/f244b8eed37a12539fb11b76e19ec7a7eb41dccc
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.cpp
M llvm/lib/Target/M68k/MCTargetDesc/M68kMCAsmInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp
Log Message:
-----------
[MC] Port initializeVariantKinds to a few targets
Commit: aa1fe57b196de4255bb2516ef6c5515491c4aaab
https://github.com/llvm/llvm-project/commit/aa1fe57b196de4255bb2516ef6c5515491c4aaab
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir
M llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir
M llvm/test/CodeGen/AArch64/pr51516.mir
M llvm/test/CodeGen/AArch64/spill-fold.mir
M llvm/test/CodeGen/MIR/Generic/runPass.mir
M llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir
M llvm/test/CodeGen/Thumb/high-reg-clobber.mir
M llvm/test/CodeGen/X86/limit-split-cost.mir
A llvm/test/tools/llc/new-pm/x86_64-regalloc-pipeline.mir
M llvm/tools/llc/NewPMDriver.cpp
Log Message:
-----------
[RegAlloc][NewPM] Plug Greedy RA in codegen pipeline (#120557)
Use `-passes="regallocgreedy<[all|sgpr|wwm|vgpr]>` to insert the greedy
RA with a filter and `-regalloc-npm=<type>` to control which RA to use
in existing pipeline.
Commit: e11867039f0806bdfebeb33bb71d8ce3ba8ee33d
https://github.com/llvm/llvm-project/commit/e11867039f0806bdfebeb33bb71d8ce3ba8ee33d
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/test/DebugInfo/ARM/tls.ll
Log Message:
-----------
[test] Replace tlsldo with TLSLDO to be consistent with most TLS*
Commit: 69c8312c0ab30e0906a374ecfc88c60ea7ffe5a4
https://github.com/llvm/llvm-project/commit/69c8312c0ab30e0906a374ecfc88c60ea7ffe5a4
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/MachineCycleAnalysis.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/X86/cycle-info.mir
Log Message:
-----------
[CodeGen][NewPM] Port MachineCycleInfo to NPM (#114745)
Commit: 04b49b11a8f70424263a3fc1f9c5bc69a9f46844
https://github.com/llvm/llvm-project/commit/04b49b11a8f70424263a3fc1f9c5bc69a9f46844
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/include/llvm/MC/MCExpr.h
M llvm/lib/MC/MCAsmInfo.cpp
M llvm/lib/MC/MCExpr.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp
Log Message:
-----------
[MCExpr] Remove generic getVariantKindName and getVariantKindForName
They are error-prone as MCParser may parse a variant kind,
which cannot be handled by the target.
The replacement in MCAsmInfo should be used instead.
Follow-up to f244b8eed37a12539fb11b76e19ec7a7eb41dccc
Commit: 03015805804c8d334382a2c7fcdb6d3d368cd94f
https://github.com/llvm/llvm-project/commit/03015805804c8d334382a2c7fcdb6d3d368cd94f
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/include/llvm/MC/MCExpr.h
M llvm/lib/MC/MCAsmInfo.cpp
M llvm/lib/MC/MCELFStreamer.cpp
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Log Message:
-----------
[PowerPC] Remove VK_PPC_TLSGD and VK_PPC_TLSLD
52cf8e44880bcf614068b66b63393aa8da1edd76 (2013) introduced the
VK_PPC_TLSGD workaround to prevent unconditional reference to
_GLOBAL_OFFSET_TABLE_ in ELFObjectWriter.
e2b355d651ed8f2cbe61672c4c39b6419e471265 (2015) removed the
`_GLOBAL_OFFSET_TABLE_` hack for the generic VK_TLSGD,
making the VK_PPC_TLSGD workaround unneeded.
Commit: 7bd2be42666dfd5ceac5fb5b2fa793b6534206fc
https://github.com/llvm/llvm-project/commit/7bd2be42666dfd5ceac5fb5b2fa793b6534206fc
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
M llvm/include/llvm/CodeGen/Register.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
M llvm/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
Log Message:
-----------
[SelectionDAG] Use Register and MCRegister. NFC
Add operators to Register to supporting adding an offset to get
another Register.
Commit: e56215d17ce8edd06d728742d7a97b7fccf073f0
https://github.com/llvm/llvm-project/commit/e56215d17ce8edd06d728742d7a97b7fccf073f0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegAllocFast.cpp
Log Message:
-----------
[RegAllocFast] Use Register and MCRegister. NFC
Commit: 13cce8c0bcf0f2e5d02f863fcbee47e3d7956eca
https://github.com/llvm/llvm-project/commit/13cce8c0bcf0f2e5d02f863fcbee47e3d7956eca
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/include/llvm/CodeGen/RegisterPressure.h
M llvm/lib/CodeGen/BranchFolding.cpp
M llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/RegisterScavenging.cpp
Log Message:
-----------
[CodeGen] Use Register::id() to avoid implicit cast. NFC
Commit: a70175ab932412ac7d46f3c82cd19384c33fc868
https://github.com/llvm/llvm-project/commit/a70175ab932412ac7d46f3c82cd19384c33fc868
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/include/llvm/CodeGen/LiveInterval.h
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/LiveDebugVariables.cpp
M llvm/lib/CodeGen/LiveVariables.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineBasicBlock.cpp
M llvm/lib/CodeGen/MachineCSE.cpp
M llvm/lib/CodeGen/MachineTraceMetrics.cpp
M llvm/lib/CodeGen/PHIElimination.cpp
M llvm/lib/CodeGen/PHIEliminationUtils.cpp
M llvm/lib/CodeGen/PHIEliminationUtils.h
M llvm/lib/CodeGen/ReachingDefAnalysis.cpp
M llvm/lib/CodeGen/RenameIndependentSubregs.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/lib/CodeGen/StackMaps.cpp
Log Message:
-----------
[CodeGen] Use MCRegister and Register. NFC
Commit: dd9bb32b9774f0e993837081a79d08e11cfeda02
https://github.com/llvm/llvm-project/commit/dd9bb32b9774f0e993837081a79d08e11cfeda02
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/MachineCSE.cpp
Log Message:
-----------
[MachineCSE] Const correct some function arguments. NFC
Commit: aaaaa4d2567fa8ac3468b51390a688cf5d6cdfe7
https://github.com/llvm/llvm-project/commit/aaaaa4d2567fa8ac3468b51390a688cf5d6cdfe7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/MachineLICM.cpp
Log Message:
-----------
[MachineLICM] Use Register. NFC
Commit: 1b043c25573aa0b13ad4241c641c38ca26f26bc1
https://github.com/llvm/llvm-project/commit/1b043c25573aa0b13ad4241c641c38ca26f26bc1
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
Log Message:
-----------
[RISCV] Simplify RISCVMCExpr::evaluateAsConstant
Most VariantKind cannot be evaluated at the parsing time.
It makes more sense to list the evaluable cases.
Commit: 71f4c7dabec0f32b2d475e8e08f0da99628a067c
https://github.com/llvm/llvm-project/commit/71f4c7dabec0f32b2d475e8e08f0da99628a067c
Author: chrisPyr <32153107+chrisPyr at users.noreply.github.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/examples/Kaleidoscope/MCJIT/cached/toy.cpp
M llvm/examples/OrcV2Examples/LLJITDumpObjects/LLJITDumpObjects.cpp
M llvm/examples/OrcV2Examples/LLJITWithExecutorProcessControl/LLJITWithExecutorProcessControl.cpp
M llvm/examples/OrcV2Examples/LLJITWithLazyReexports/LLJITWithLazyReexports.cpp
M llvm/examples/OrcV2Examples/LLJITWithThinLTOSummaries/LLJITWithThinLTOSummaries.cpp
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
M llvm/lib/Analysis/FunctionPropertiesAnalysis.cpp
M llvm/lib/Analysis/IRSimilarityIdentifier.cpp
M llvm/lib/Analysis/InlineSizeEstimatorAnalysis.cpp
M llvm/lib/Analysis/MemoryProfileInfo.cpp
M llvm/lib/CGData/CodeGenData.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/WindowScheduler.cpp
M llvm/lib/LTO/LTOCodeGenerator.cpp
M llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
M llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
M llvm/lib/Target/ARM/MVELaneInterleavingPass.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
M llvm/lib/Transforms/IPO/ElimAvailExtern.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/IPO/ModuleInliner.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SeedCollector.cpp
M llvm/tools/bugpoint/ExecutionDriver.cpp
M llvm/tools/bugpoint/OptimizerDriver.cpp
M llvm/tools/llvm-as/llvm-as.cpp
M llvm/tools/llvm-cat/llvm-cat.cpp
M llvm/tools/llvm-cfi-verify/llvm-cfi-verify.cpp
M llvm/tools/llvm-cxxdump/llvm-cxxdump.cpp
M llvm/tools/llvm-cxxmap/llvm-cxxmap.cpp
M llvm/tools/llvm-diff/llvm-diff.cpp
M llvm/tools/llvm-extract/llvm-extract.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/tools/llvm-lto/llvm-lto.cpp
M llvm/tools/llvm-lto2/llvm-lto2.cpp
M llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/tools/llvm-undname/llvm-undname.cpp
M llvm/tools/reduce-chunk-list/reduce-chunk-list.cpp
M llvm/tools/yaml2obj/yaml2obj.cpp
M llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
M llvm/utils/yaml-bench/YAMLBench.cpp
Log Message:
-----------
[NFC]Make file-local cl::opt global variables static (#126486)
#125983
Commit: 59138a603fca2a4e848ecf97af81c61559e9301d
https://github.com/llvm/llvm-project/commit/59138a603fca2a4e848ecf97af81c61559e9301d
Author: Huibin Wang <fighter90 at 163.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAGCombiner] Cleanup MatchFunnelPosNeg by using SDPatternMatch matchers (#129482)
Fixes issue: https://github.com/llvm/llvm-project/issues/129034
Commit: 6a161cbfd458ab2af39b382056dff515ff549eb6
https://github.com/llvm/llvm-project/commit/6a161cbfd458ab2af39b382056dff515ff549eb6
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/lib/Passes/PatchEntries.cpp
Log Message:
-----------
[BOLT] Remove BinaryFunction::IsPatched. NFC (#129461)
BinaryFunction::IsPatched is no longer used.
Commit: 8a9a363ffb96b569a52825d8c2b41ac412f4eb28
https://github.com/llvm/llvm-project/commit/8a9a363ffb96b569a52825d8c2b41ac412f4eb28
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
Log Message:
-----------
[MIRCanonicalizerPass] Use MCRegister. NFC
Commit: 49ba565913e189f45e0822f475b0f61f50670c55
https://github.com/llvm/llvm-project/commit/49ba565913e189f45e0822f475b0f61f50670c55
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/IfConversion.cpp
Log Message:
-----------
[IfConversion] Use MCRegister. NFC
Commit: 3fe22559c7e743c9e19c55d4263ca21b5cf06ddf
https://github.com/llvm/llvm-project/commit/3fe22559c7e743c9e19c55d4263ca21b5cf06ddf
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/InlineSpiller.cpp
Log Message:
-----------
[InlineSpiller] Use Register. NFC
Commit: 9f8e148a6cdcdb8e89c284c2bc71e3ea28d2c5f1
https://github.com/llvm/llvm-project/commit/9f8e148a6cdcdb8e89c284c2bc71e3ea28d2c5f1
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/include/llvm/CodeGen/CalcSpillWeights.h
M llvm/lib/CodeGen/CalcSpillWeights.cpp
Log Message:
-----------
[CalcSpillWeights] Use Register. NFC
Commit: 7cee4c7c59fdbb28fb7b502ea39da521b1e634a2
https://github.com/llvm/llvm-project/commit/7cee4c7c59fdbb28fb7b502ea39da521b1e634a2
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/include/llvm/CodeGen/CallingConvLower.h
M llvm/lib/CodeGen/CallingConvLower.cpp
Log Message:
-----------
[CallingConvLower] Use MCRegister. NFC
Commit: caa798cb1e5cc8d4d75ed2347e3f2df533367c25
https://github.com/llvm/llvm-project/commit/caa798cb1e5cc8d4d75ed2347e3f2df533367c25
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
Log Message:
-----------
[GlobalISel] Use Register. NFC
Commit: 5387a77f8b82d154a98c8c2fd8bfa4b2b1ee67d9
https://github.com/llvm/llvm-project/commit/5387a77f8b82d154a98c8c2fd8bfa4b2b1ee67d9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-02 (Sun, 02 Mar 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFrameInfo.h
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
Log Message:
-----------
[CodeGen] Use MCRegister in CalleeSavedInfo. NFC
Commit: 3f48d34dfffac81bc73db626438f531c5324f85b
https://github.com/llvm/llvm-project/commit/3f48d34dfffac81bc73db626438f531c5324f85b
Author: foxtran <39676482+foxtran at users.noreply.github.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M openmp/runtime/src/kmp_taskdeps.cpp
Log Message:
-----------
[OpenMP][runtime] Fix comparison of integer expressions of different signedness (#128204)
This PR fixes warning which occurs if one compiles OpenMP runtime with
GCC:
```
warning: comparison of integer expressions of different signedness: 'kmp_intptr_t' {aka 'long int'} and 'long unsigned int' [-Wsign-compare]
```
Commit: 8d1e260fc419e31bb11cb5a2f1f872a2b679d217
https://github.com/llvm/llvm-project/commit/8d1e260fc419e31bb11cb5a2f1f872a2b679d217
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/include/mlir/Analysis/Presburger/IntegerRelation.h
Log Message:
-----------
[MLIR] Fix IntegerPolyhedron ctors to avoid copy (#129446)
Use const ref. NFC otherwise.
Commit: 9db72e55edf8c10b2a1b72f1a2d4594d312dd91c
https://github.com/llvm/llvm-project/commit/9db72e55edf8c10b2a1b72f1a2d4594d312dd91c
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/utils/perf-training/perf-helper.py
Log Message:
-----------
[clang][cmake] Fix support for dynamic libraries in CLANG_BOLT
Patch typo introduced in #127020
Commit: c13ebb527961e96e96ec1913dbbbcc6782512e18
https://github.com/llvm/llvm-project/commit/c13ebb527961e96e96ec1913dbbbcc6782512e18
Author: Arnab Dutta <85476402+arnab-polymage at users.noreply.github.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp
M mlir/test/Conversion/GPUCommon/lower-memcpy-to-gpu-runtime-calls.mlir
Log Message:
-----------
Fix bug in gpu.memcpy lowering for dynamically shaped operands. (#128820)
Compute the number of elements to be copied by multiplying dim sizes
along all the dimensions.
Commit: 2af4007822c75b231d90c84552bc0a4e101e1171
https://github.com/llvm/llvm-project/commit/2af4007822c75b231d90c84552bc0a4e101e1171
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/include/llvm/MC/MCExpr.h
M llvm/lib/MC/MCAsmInfo.cpp
M llvm/lib/MC/MCExpr.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp
Log Message:
-----------
Revert "[MCExpr] Remove generic getVariantKindName and getVariantKindForName"
This reverts commit 04b49b11a8f70424263a3fc1f9c5bc69a9f46844.
This patch breaks ThinLTO/X86/memprof-tailcall-nonunique.ll.
Builtbot failures:
https://lab.llvm.org/buildbot/#/builders/108/builds/9933
https://lab.llvm.org/buildbot/#/builders/25/builds/6868
https://lab.llvm.org/buildbot/#/builders/46/builds/12890
Commit: 9805854699d6aca242ec63ca64dfab142a8bb951
https://github.com/llvm/llvm-project/commit/9805854699d6aca242ec63ca64dfab142a8bb951
Author: jeanPerier <jperier at nvidia.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M flang/test/Analysis/AliasAnalysis/alias-analysis-3.fir
M flang/test/Analysis/AliasAnalysis/load-ptr-designate.fir
M flang/test/Analysis/AliasAnalysis/ptr-component.fir
M flang/test/Fir/CUDA/cuda-abstract-result.mlir
M flang/test/Fir/boxproc-2.fir
M flang/test/Transforms/omp-map-info-finalization.fir
Log Message:
-----------
[flang][NFC] clean-up fir.field_index legacy usages in tests (#129219)
After #127231, fir.coordinate_of should directly carry the field.
I updated the lowering and codegen tests in #12731, but not the FIR to
FIR tests, which is what this patch is cleaning up.
Commit: 178fb96f72b95b9df87227832b3dd495d9b9f91c
https://github.com/llvm/llvm-project/commit/178fb96f72b95b9df87227832b3dd495d9b9f91c
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
Log Message:
-----------
[ExecutionEngine] Avoid repeated hash lookups (NFC) (#129466)
Commit: 0e5826ea07b17d05d6ea5a397288e9cc96f1d8cd
https://github.com/llvm/llvm-project/commit/0e5826ea07b17d05d6ea5a397288e9cc96f1d8cd
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
Log Message:
-----------
[IPO] Avoid repeated hash lookups (NFC) (#129467)
Commit: ec66c87c3455f2b22e8c8b830e5b1c3e477bd2cf
https://github.com/llvm/llvm-project/commit/ec66c87c3455f2b22e8c8b830e5b1c3e477bd2cf
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
Log Message:
-----------
[Scalar] Avoid repeated hash lookups (NFC) (#129468)
Commit: 1891281a15817996c0caada09dadc9d026331345
https://github.com/llvm/llvm-project/commit/1891281a15817996c0caada09dadc9d026331345
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] Avoid repeated hash lookups (NFC) (#129470)
Commit: cb113a78126ad54109738c298794ff2293a47b37
https://github.com/llvm/llvm-project/commit/cb113a78126ad54109738c298794ff2293a47b37
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
Log Message:
-----------
RegisterCoalescer: Avoid repeated getRegClass on all paths (#129490)
Commit: 59f407020ea60d46af974563e4b87b8d9f188802
https://github.com/llvm/llvm-project/commit/59f407020ea60d46af974563e4b87b8d9f188802
Author: Robert Konicar <xkonicar at fi.muni.cz>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
Log Message:
-----------
[MLIR] Fix printing of switch case for negative value (#129266)
This patch fixes the printer for the `llvm.switch` operation with
negative values in a case.
The previous behaviour printed the value as an unsigned integer, as the
`getLimitedValue()` returns unsigned value. This caused the roundtrip to
fail (assertion in `APInt`), as the printed unsigned integer could not
be parsed into the same amount of bits in a signed integer.
I don't see a good reason for keeping any restriction on the printed
value, as LLVMIR `switch` afaik does not have a limit on the bitwidth of
the values and `APInt` handles printing just fine.
Commit: 7be8b78f827a0f30bbd9fc3ee84a62f440b41546
https://github.com/llvm/llvm-project/commit/7be8b78f827a0f30bbd9fc3ee84a62f440b41546
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
Log Message:
-----------
AMDGPU: Add mir test for agpr constant reg_sequence handling (#129058)
Commit: 49a533a4859eac99efac3220a1ffc62616cb3664
https://github.com/llvm/llvm-project/commit/49a533a4859eac99efac3220a1ffc62616cb3664
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
Log Message:
-----------
AMDGPU: Stop introducing v_accvgpr_write_b32 for reg-to-reg copy (#129059)
This was trying to hack around the intermediate VGPR requirement
to copy to AGPRs on gfx908. We should still use a copy for all
reg-to-reg cases. This should matter less these days, as we
reserve a VGPR to handle it when required (and no end to end tests
need updating).
This was also an obstacle to handling this fold for input registers
which are larger than 32-bits.
Commit: 3d5348b54ca91ac081a97b37d53e1ef4db62fdbe
https://github.com/llvm/llvm-project/commit/3d5348b54ca91ac081a97b37d53e1ef4db62fdbe
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/include/mlir/Dialect/Affine/Analysis/AffineStructures.h
M mlir/lib/Dialect/Affine/Analysis/AffineStructures.cpp
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/test/Dialect/Affine/parallelize.mlir
Log Message:
-----------
[MLIR][Affine] Fix addInductionVarOrTerminalSymbol to return status (#129476)
Fixes: https://github.com/llvm/llvm-project/issues/64287
This method is failable on valid IR and we should've been returning
failure instead of asserting, and checking status at its users.
Commit: 1119b7297780e870e8ae05651389913e09ae2036
https://github.com/llvm/llvm-project/commit/1119b7297780e870e8ae05651389913e09ae2036
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/CodeGen/Targets/RISCV.cpp
Log Message:
-----------
[RISCV][clang] Add address space argument to getNaturalAlignIndirect (#129493)
This is introduced in 39ec9de7c23063b87f5c56f4e80c8d0f8b511a4b
Commit: da7403ed1d5727cd758560ffc7957bba5c395745
https://github.com/llvm/llvm-project/commit/da7403ed1d5727cd758560ffc7957bba5c395745
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/docs/analyzer/checkers.rst
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.def
M clang/lib/StaticAnalyzer/Checkers/DereferenceChecker.cpp
M clang/test/Analysis/analyzer-config.c
M clang/test/Analysis/cast-value-notes.cpp
M clang/test/Analysis/concrete-address.c
M clang/test/Analysis/misc-ps.m
A clang/test/Analysis/suppress-dereferences-from-any-address-space.c
Log Message:
-----------
[clang][analyzer] Add checker 'alpha.core.FixedAddressDereference' (#127191)
Commit: 75bfdebdeee3a8783a5e6cae3fb8370091329a83
https://github.com/llvm/llvm-project/commit/75bfdebdeee3a8783a5e6cae3fb8370091329a83
Author: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Log Message:
-----------
[SelectionDAG] Use `poison` instead of `undef` for `dbg.values` (#127915)
`undef dbg.values` can be replaced with `poison dbg.values`.
Commit: 05589ee455334530addaabc56205f05df0954caf
https://github.com/llvm/llvm-project/commit/05589ee455334530addaabc56205f05df0954caf
Author: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/IR/Metadata.cpp
M llvm/test/DebugInfo/X86/undef-dbg-val.ll
Log Message:
-----------
[Metadata] Replace `undef` VAMs with `poison` VAMs (#129450)
`undef` debug info can be replaced with `poison` debug info.
Commit: 77f44a964212a54ebc014a703c6787ae236b6ef4
https://github.com/llvm/llvm-project/commit/77f44a964212a54ebc014a703c6787ae236b6ef4
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
A llvm/include/llvm/CodeGen/MachineSink.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/test/CodeGen/AArch64/loop-sink.mir
M llvm/test/CodeGen/AArch64/sink-and-fold-preserve-debugloc.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
M llvm/test/CodeGen/ARM/machine-sink-multidef.mir
M llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir
M llvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir
M llvm/test/CodeGen/RISCV/MachineSink-implicit-x0.mir
M llvm/test/CodeGen/SystemZ/machinesink-dead-cc.mir
M llvm/test/CodeGen/X86/machinesink-debug-inv-0.mir
M llvm/test/DebugInfo/MIR/X86/sink-leaves-undef.mir
Log Message:
-----------
[CodeGen][NewPM] Port MachineSink to NPM (#115434)
Targets can set the EnableSinkAndFold option in CGPassBuilderOptions for
the NPM pipeline in buildCodeGenPipeline(... &Opts, ...)
Commit: c545d571c596a2d59e1d164bc9dc5f40881c3ff1
https://github.com/llvm/llvm-project/commit/c545d571c596a2d59e1d164bc9dc5f40881c3ff1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineConcatVectorOps - use ConcatSubOperand helper to concat VPERMV3 subvector operands together.
Shouldn't affect existing test coverage, but aggressively peeking through bitcasts before concatenation will help in a future patch.
Commit: 44607666b3429868bce9f0489715eb367d0e08f8
https://github.com/llvm/llvm-project/commit/44607666b3429868bce9f0489715eb367d0e08f8
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp
Log Message:
-----------
[AMDGPU] Simplify conditional expressions. NFC. (#129228)
Simplfy `cond ? val : false` to `cond && val` and similar.
Commit: a55786170df204ca38caf922850df68ac188c7e0
https://github.com/llvm/llvm-project/commit/a55786170df204ca38caf922850df68ac188c7e0
Author: Sergey Kachkov <sergey.kachkov at syntacore.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
A llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
Log Message:
-----------
[RISCV][NFC] Add pre-commit test
Commit: 370d34fe40162946905b900097ed746dd4aeb6ad
https://github.com/llvm/llvm-project/commit/370d34fe40162946905b900097ed746dd4aeb6ad
Author: Jean-Didier PAILLEUX <jean-didier.pailleux at sipearl.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/Flang.cpp
M flang/lib/Frontend/CompilerInvocation.cpp
A flang/test/Driver/fd-lines-as.f90
A flang/test/Preprocessing/fd-lines-as.f90
Log Message:
-----------
[flang][Driver] Add support of -fd-lines-as-comments and -fd-lines-as-code flags (#127605)
`-fd-lines-as-code` and `-fd-lines-as-comments` enables treatment for
lines beginning with `d` or `D` in fixed form sources.
Using these options in free form has no effect.
If the `-fd-lines-as-code` option is given they are treated as if the
first column contained a blank.
If the `-fd-lines-as-comments` option is given, they are treated as
comment lines.
Commit: 742fa8ac67796198dde99e18cdadeaf9b96c2f88
https://github.com/llvm/llvm-project/commit/742fa8ac67796198dde99e18cdadeaf9b96c2f88
Author: Austin <zhenhangwang at huawei.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/Arch/ARM.cpp
M clang/test/Driver/arm-thread-pointer.c
Log Message:
-----------
[ARM] Introduce -mtp=auto and make it the default (#128901)
This adds a new value auto to the possible values of the existing -mtp=
clang option which controls how the thread pointer is found. auto means
the same as soft if the target architecture doesn't support a hardware
thread pointer at all; otherwise it means the same as cp15.
This behavior is the default in gcc version 4.1.0 and later. The new
auto option is therefore also the default in clang, so this change
aligns clang with gcc.
Fixes #123864.
Commit: 55fdeccc4567bcd4e3f8df0d177195880a194a6a
https://github.com/llvm/llvm-project/commit/55fdeccc4567bcd4e3f8df0d177195880a194a6a
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/test/CodeGen/PowerPC/llvm.modf.ll
Log Message:
-----------
[SDAG][X86] Remove hack needed to avoid missing x87 FPU stack pops (#128055)
If a (two-result) node like `FMODF` or `FFREXP` is expanded to a library
call, where said library has the function prototype like: `float(float,
float*)` -- that is it returns a float from the call and via an output
pointer. The first result of the node maps to the value returned by
value and the second result maps to the value returned via the output
pointer.
If only the second result is used after the expansion, we hit an issue
on x87 targets:
```
// Before expansion:
t0, t1 = fmodf x
return t1 // t0 is unused
```
Expanded result:
```
ptr = alloca
ch0 = call modf ptr
t0, ch1 = copy_from_reg, ch0 // t0 unused
t1, ch2 = ldr ptr, ch1
return t1
```
So far things are alright, but the DAGCombiner optimizes this to:
```
ptr = alloca
ch0 = call modf ptr
// copy_from_reg optimized out
t1, ch1 = ldr ptr, ch0
return t1
```
On most targets this is fine. The optimized out `copy_from_reg` is
unused and is a NOP. However, x87 uses a floating-point stack, and if
the `copy_from_reg` is optimized out it won't emit a pop needed to
remove the unused result.
The prior solution for this was to attach the chain from the
`copy_from_reg` to the root, which did work, however, the root is not
always available (it's set to null during legalize types). So the
alternate solution in this patch is to replace the `copy_from_reg` with
an `X86ISD::POP_FROM_X87_REG` within the X86 call lowering. This node is
the same as `copy_from_reg` except this node makes it explicit that it
may lower to an x87 FPU stack pop. Optimizations should be more cautious
when handling this node than a normal CopyFromReg to avoid removing a
required FPU stack pop.
```
ptr = alloca
ch0 = call modf ptr
t0, ch1 = pop_from_x87_reg, ch0 // t0 unused
t1, ch2 = ldr ptr, ch1
return t1
```
Using this node ensures a required x87 FPU pop is not removed due to the
DAGCombiner.
This is an alternate solution for #127976.
Commit: f6212c1cd3d8b827c7d7e2f6cf54b135c27eacc6
https://github.com/llvm/llvm-project/commit/f6212c1cd3d8b827c7d7e2f6cf54b135c27eacc6
Author: Tobi <9053039+devtbi at users.noreply.github.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ByteProvider.h
M llvm/include/llvm/ProfileData/Coverage/MCDCTypes.h
M llvm/include/llvm/Support/thread.h
Log Message:
-----------
[llvm] Fix missing includes (#128000)
Compilation with `LLVM_ENABLE_MODULES:BOOL=ON` fails due to missing
includes. This patch adds these includes (+missing tuple include in
thread.h), fixing the module build for me.
Commit: 6abe148bac6f61850f80f3687d68a0d299a7ff35
https://github.com/llvm/llvm-project/commit/6abe148bac6f61850f80f3687d68a0d299a7ff35
Author: Vikram Hegde <115221833+vikramRH at users.noreply.github.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
A llvm/include/llvm/CodeGen/RemoveRedundantDebugValues.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/RemoveRedundantDebugValues.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/DebugInfo/MIR/X86/remove-redundant-dbg-vals.mir
Log Message:
-----------
[CodeGen][NewPM] Port "RemoveRedundantDebugValues" to NPM (#129005)
Commit: 3c9429f133e8624e572bb50d11348494a219a1a6
https://github.com/llvm/llvm-project/commit/3c9429f133e8624e572bb50d11348494a219a1a6
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/test/CodeGen/X86/apx/setzucc.ll
Log Message:
-----------
[X86] Remove redundant test after setzucc (#129506)
Patch #96594 substitutes setcc + zext pair with setzucc, but it results
in redundant test because X86FlagsCopyLowering doesn't recognize it.
This patch removes redundant test by reverting setzucc to setcc
(optimized) + zext.
Commit: 9b4ad2fe508d8e008bdfcc3036541026f2ad4ebf
https://github.com/llvm/llvm-project/commit/9b4ad2fe508d8e008bdfcc3036541026f2ad4ebf
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-fixed-order-recurrence.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
Log Message:
-----------
[LV][EVL] Support fixed-order recurrence idiom with EVL tail folding. (#124093)
This patch converts the llvm.vector.splice intrinsic to
llvm.experimental.vp.splice, ensuring that fixed-order recurrences
execute correctly when tail folding by EVL is enable.
Due to the non-VFxUF penultimate EVL issue, the EVL from the previous
iteration will be preserved and used in llvm.experimental.vp.splice.
Commit: 3dc799162f4f8e3a951041d453768a9975a719f1
https://github.com/llvm/llvm-project/commit/3dc799162f4f8e3a951041d453768a9975a719f1
Author: Sergey Kachkov <109674256+skachkov-sc at users.noreply.github.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
Log Message:
-----------
[RISCV] Add DAG combine to convert (iN reduce.add (zext (vXi1 A to vXiN)) into vcpop.m (#127497)
This patch combines (iN vector.reduce.add (zext (vXi1 A to vXiN)) into
vcpop.m instruction (similarly to bitcast + ctpop pattern). It can be
useful for counting number of set bits in scalable vector types, which
can't be expressed with bitcast + ctpop (this was previously discussed
here: https://github.com/llvm/llvm-project/pull/74294).
Commit: 50301052e9d65e55c90c652f2551f00f906cee2b
https://github.com/llvm/llvm-project/commit/50301052e9d65e55c90c652f2551f00f906cee2b
Author: Mats Petersson <mats.petersson at arm.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Lower/OpenMP/Todo/omp-declare-reduction-initsub.f90
M flang/test/Parser/OpenMP/declare-reduction-unparse.f90
A flang/test/Semantics/OpenMP/declare-reduction-error.f90
M flang/test/Semantics/OpenMP/declare-reduction.f90
Log Message:
-----------
[flang][OpenMP]Support for subroutine call for DECLARE REDUCTION init (#127889)
The DECLARE REDUCTION allows the initialization part to be either an
expression or a call to a subroutine.
This modifies the parsing and semantic analysis to allow the use of the
subroutine, in addition to the simple expression that was already
supported.
New tests in parser and semantics sections check that the generated
structure is as expected.
DECLARE REDUCTION lowering is not yet implemented, so will end in a
TODO. A new test with an init subroutine is added, that checks that this
variant also ends with a "Not yet implemented" message.
Commit: 5470dffda2a197f93bf46d69c8c048c236438ef4
https://github.com/llvm/llvm-project/commit/5470dffda2a197f93bf46d69c8c048c236438ef4
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/test/Transforms/Attributor/value-simplify.ll
Log Message:
-----------
[Attributor] Do not optimize away externally_initialized loads. (#128170)
Fixes SWDEV-515029
Commit: 9573c621147748e5ca07f545db0d995708c29435
https://github.com/llvm/llvm-project/commit/9573c621147748e5ca07f545db0d995708c29435
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Semantics/OpenMP/flush01.f90
A flang/test/Semantics/OpenMP/flush03.f90
Log Message:
-----------
[flang][OpenMP] Accept modern syntax of FLUSH construct (#128975)
The syntax with the object list following the memory-order clause has
been removed in OpenMP 5.2. Still, accept that syntax with versions >=
5.2, but treat it as deprecated (and emit a warning).
Commit: 439623797230e547d1aee77d4c56f664fbc5090a
https://github.com/llvm/llvm-project/commit/439623797230e547d1aee77d4c56f664fbc5090a
Author: Benjamin Chetioui <3920784+bchetioui at users.noreply.github.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Fix Bazel build after db0e7c72aff622849abbc92c3ed0d06efb8e2d16. (#129532)
db0e7c72aff622849abbc92c3ed0d06efb8e2d16.
Commit: 299be6123b8106dae31a8c7065d1e395b400cbe2
https://github.com/llvm/llvm-project/commit/299be6123b8106dae31a8c7065d1e395b400cbe2
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/Overload.h
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaCodeComplete.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/test/CXX/drs/cwg14xx.cpp
A clang/test/CodeCompletion/GH125500.cpp
Log Message:
-----------
[clang] Fix CodeComplete crash involving CWG1432 (#129436)
This skips the provisional resolution of CWG1432 just when ordering the
candidates for function call code completion, as otherwise this breaks
some assumptions the implementation makes about how closely related the
candidates are.
As a drive-by, deduplicate the implementation with the one used for
class template partial ordering, and strenghten an assertion which was
previosuly dependent on the order of candidates.
Also add a test for the fix for CWG1432 when partial ordering function
templates, which was otherwise untested.
Fixes #125500
Commit: dddfd77f653d7e88965b647e9bc38827cae8bf8a
https://github.com/llvm/llvm-project/commit/dddfd77f653d7e88965b647e9bc38827cae8bf8a
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/GVN.cpp
Log Message:
-----------
[GVN][NFC] Fix some variables as per coding standards (#129489)
Commit: 17857d92416da5997262318a6f62fccad9c5a156
https://github.com/llvm/llvm-project/commit/17857d92416da5997262318a6f62fccad9c5a156
Author: Abhishek Kaushik <abhishek.kaushik at intel.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/kmov.ll
M llvm/test/CodeGen/X86/pr78897.ll
Log Message:
-----------
[X86] Generate `kmov` for masking integers (#120593)
When we have an integer used as a bit mask the llvm ir looks something
like this
```
%1 = and <16 x i32> %.splat, <i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 512, i32 1024, i32 2048, i32 4096, i32 8192, i32 16384, i32 32768>
%cmp1 = icmp ne <16 x i32> %1, zeroinitializer
```
where `.splat` is vector containing the mask in all lanes. The assembly
generated for this looks like
```
vpbroadcastd %ecx, %zmm0
vptestmd .LCPI0_0(%rip), %zmm0, %k1
```
where we have a constant table of powers of 2.
Instead of doing this we could just move the relevant bits directly to
`k` registers using a `kmov` instruction.
```
kmovw %ecx, %k1
```
This is faster and also reduces code size.
Commit: a088b0ec7653f12e60d01959bc71ea4f7fd206f0
https://github.com/llvm/llvm-project/commit/a088b0ec7653f12e60d01959bc71ea4f7fd206f0
Author: Vy Nguyen <vyng at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M lldb/include/lldb/Core/Telemetry.h
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/Telemetry.cpp
M lldb/unittests/Core/TelemetryTest.cpp
Log Message:
-----------
[LLDB][Telemetry]Define DebuggerTelemetryInfo and related methods (#127696)
This type of entry is used to collect data about the debugger
startup/exit
Also introduced a helper ScopedDispatcher
---------
Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
Co-authored-by: Pavel Labath <pavel at labath.sk>
Commit: cb940306d4a3078b53141221985ca8893a9a2cb6
https://github.com/llvm/llvm-project/commit/cb940306d4a3078b53141221985ca8893a9a2cb6
Author: Dmitri Gribenko <gribozavr at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/test/tools/llc/new-pm/x86_64-regalloc-pipeline.mir
Log Message:
-----------
[test] Add '-o -' to llc command to avoid creating unnecessary temp files
Commit: d37a39207bc15507e602e41b7655f615c10c9a1d
https://github.com/llvm/llvm-project/commit/d37a39207bc15507e602e41b7655f615c10c9a1d
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/docs/HIPSupport.rst
M clang/lib/Sema/SemaCUDA.cpp
M clang/test/SemaCUDA/dtor.cu
Log Message:
-----------
[CUDA][HIP] fix virtual dtor host/device attr (#128926)
Currently if CUDA/HIP users use template class with virtual dtor
and std::string data member with C++20 and MSVC. When the template
class is explicitly instantiated, there is error about host
function called by host device function (used to be undefined
symbols in linking stage before member destructors were checked
by deferred diagnostics).
It was caused by clang inferring host/device attributes for
default dtors. Since all dtors of member and parent classes
have implicit host device attrs, clang infers the virtual dtor have
implicit host and device attrs. Since virtual dtor of
explicitly instantiated template class must be emitted,
this causes constexpr dtor of std::string emitted, which
calls a host function which was not emitted on device side.
This is a serious issue since it prevents users from
using std::string with C++20 on Windows.
When inferring host device attr of virtual dtor of explicit
template class instantiation, clang should be conservative
since it is sure to be emitted. Since an implicit host device
function may call a host function, clang cannot assume it is
always available on device. This guarantees dtors that
may call host functions not to have implicit device attr,
therefore will not be emitted on device side.
Fixes: https://github.com/llvm/llvm-project/issues/108548
Fixes: SWDEV-517435
Commit: 96336acb48562edcae59eb1d5d4acb0200efeded
https://github.com/llvm/llvm-project/commit/96336acb48562edcae59eb1d5d4acb0200efeded
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/new-delete.cpp
Log Message:
-----------
[clang][bytecode] Tighten double-destroy check (#129528)
The instance pointer of the current function being the same as the one
we're destroying is only relevant if said function is also a destructor.
Commit: bcce75415e52c8529e94f70c49b481e903381aaa
https://github.com/llvm/llvm-project/commit/bcce75415e52c8529e94f70c49b481e903381aaa
Author: Robert Konicar <xkonicar at fi.muni.cz>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
[MLIR][LLVMIR] Add suport for ptrmask intrinsic op (#129539)
Resolves #115805
This patch adds support for ptrmask intrinsic in LLVM dialect and
corresponding import/export tests.
Commit: bcb0c3a2917156e313dc5258fce0890a951ebabf
https://github.com/llvm/llvm-project/commit/bcb0c3a2917156e313dc5258fce0890a951ebabf
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
Log Message:
-----------
[CodeGen] Avoid repeated hash lookups (NFC) (#129465)
Commit: da6d5fa79a558b66c281bed3f5ce848a69a65208
https://github.com/llvm/llvm-project/commit/da6d5fa79a558b66c281bed3f5ce848a69a65208
Author: Lukas Bergdoll <lukas.bergdoll at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M libc/src/stdlib/qsort_pivot.h
Log Message:
-----------
Add missing LIBC_INLINE to qsort_pivot.h (#126249)
Fixes #111495
Commit: 95e460a3878555907ae8e8afe350b40ea8150005
https://github.com/llvm/llvm-project/commit/95e460a3878555907ae8e8afe350b40ea8150005
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M lldb/source/Core/Debugger.cpp
Log Message:
-----------
[lldb] Fix a warning
This patch fixes:
lldb/source/Core/Debugger.cpp:1002:10: error: lambda capture 'this'
is not used [-Werror,-Wunused-lambda-capture]
Commit: 396139a3b6fc9f1a06a010c1da4164527d1e14da
https://github.com/llvm/llvm-project/commit/396139a3b6fc9f1a06a010c1da4164527d1e14da
Author: wieDasDing <6884440+dingxiangfei2009 at users.noreply.github.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M lldb/bindings/python/CMakeLists.txt
M lldb/bindings/python/python.swig
Log Message:
-----------
Push down the swig module to avoid an import cycle (#129135)
Fix #92603
This replaces #113066. I finally came back to this issue and it seems
that this approach is still very promising.
As requested, I have added a short explanation as to why CPython module
should be moved into a submodule.
cc @JDevlieghere who reviewed on the previous PR earlier.
Commit: ccf1bfc1d50a70260d200a9137ab7924dac029a8
https://github.com/llvm/llvm-project/commit/ccf1bfc1d50a70260d200a9137ab7924dac029a8
Author: TatWai Chong <tatwai.chong at arm.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Dialect/Tosa/level_check.mlir
Log Message:
-----------
[mlir][tosa] Add several level checks (#128074)
Add the following types of level check to consolidate the level validity
- Complete rank level checks for operations.
- Add MAX_LOG2_SIZE level check: The maximum value is 63 when the
level is set to "none" and 31 when the level is set to "8K".
- Add MAX_TENSOR_LIST_SIZE level check : The maximum value is 256
when the level is set to "none" and 64 when the level is set to "8K".
- TOSA 1.0 spec does not allow operations with dynamic shapes, so
an error should be raised instead
Co-authored-by: TatWai Chong <tatwai.chong at arm.com>
Co-authored-by: Tai Ly <tai.ly at arm.com>
Commit: 5d7d66ba0d1ad6fcf1aefffd045eea88597f4614
https://github.com/llvm/llvm-project/commit/5d7d66ba0d1ad6fcf1aefffd045eea88597f4614
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
A clang/include/clang/AST/DeclOpenACC.h
M clang/include/clang/AST/DeclVisitor.h
M clang/include/clang/AST/JSONNodeDumper.h
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/TextNodeDumper.h
M clang/include/clang/Basic/DeclNodes.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/OpenACCClauses.def
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/SemaBase.h
M clang/include/clang/Sema/SemaOpenACC.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Serialization/ASTRecordReader.h
M clang/lib/AST/ASTStructuralEquivalence.cpp
M clang/lib/AST/CMakeLists.txt
M clang/lib/AST/DeclBase.cpp
A clang/lib/AST/DeclOpenACC.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/OpenACCClause.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/CodeGen/CGDecl.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Sema/SemaBase.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaOpenACCClause.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTCommon.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
A clang/test/AST/ast-print-openacc-declare-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-constructs.c
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
M clang/test/SemaOpenACC/compute-construct-device_type-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
A clang/test/SemaOpenACC/declare-construct-ast.cpp
A clang/test/SemaOpenACC/declare-construct.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/test/SemaOpenACC/unimplemented-construct.c
M clang/tools/libclang/CIndex.cpp
Log Message:
-----------
[OpenACC] Implement 'declare' construct AST/Sema
The 'declare' construct is the first of two 'declaration' level
constructs, so it is legal in any place a declaration is, including as a
statement, which this accomplishes by wrapping it in a DeclStmt. All
clauses on this have a 'same scope' requirement, which this enforces as
declaration context instead, which makes it possible to implement these
as a template.
The 'link' and 'device_resident' clauses are also added, which have some
similar/small restrictions, but are otherwise pretty rote.
This patch implements all of the above.
Commit: cb850fef2a564ea330e8a4878fafb4f5b4a7a98e
https://github.com/llvm/llvm-project/commit/cb850fef2a564ea330e8a4878fafb4f5b4a7a98e
Author: David Green <david.green at arm.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/16bit-float-promotion-with-nofp.ll
Log Message:
-----------
[AArch64] Don't try to custom lower fp16 selects with nofp (#129492)
If we do not have fp then we do not need to try and custom lower fp16
selects.
Fixes #129394.
Commit: 0735cece68abd7138474a62e0b023739830c4d17
https://github.com/llvm/llvm-project/commit/0735cece68abd7138474a62e0b023739830c4d17
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
A flang/test/Transforms/debug-associate-component.fir
Log Message:
-----------
[flang] Fixed fir.coordinate_of access in AddDebugInfo. (#129423)
The issue came up after #127231, when fir.coordinate_of, fed into
a declare, only has the field attribute and no coordinates.
Commit: ba9bd22e1b535a1669e3918fa77f6edaf6851d9a
https://github.com/llvm/llvm-project/commit/ba9bd22e1b535a1669e3918fa77f6edaf6851d9a
Author: Frederik Harwath <frederik.harwath at amd.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
A llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel-dst.mir
A llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel-src.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
M llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
Log Message:
-----------
[AMDGPU] Account for existing SDWA selections (#123221)
The si-peephole-sdwa pass adjusts the selections on sdwa instructions to
the selections on their operands during its conversions. For instance,
if an instruction selects `BYTE_0` and its operand selects `WORD_1`, the
combined selection should be `BYTE_2`, i.e. "`BYTE_0` of `WORD_1`". The
existing implementation does not always handle this correctly in some
complex situations with instructions across different basic blocks as
demonstrated by the test cases included in this PR.
This PR adds an additional selection combination step to the conversion
to fix this issue. It reverts the changes made by PR #123942 which had
disabled the conversion of preexisting SDWA instructions completely as a
quick fix.
---------
Co-authored-by: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: 0303fd2746dfc836507a5728cfc109316368894c
https://github.com/llvm/llvm-project/commit/0303fd2746dfc836507a5728cfc109316368894c
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrVSX.td
M llvm/test/CodeGen/PowerPC/licm-xxsplti.ll
M llvm/test/CodeGen/PowerPC/memset-tail.ll
Log Message:
-----------
[PowerPC] hoist xxspltib out of loop body (#127121)
Fixes https://github.com/llvm/llvm-project/issues/127119
Remove `hasSideEffects` from `xxspltib` since there is no special
restriction specified in the ISA that prevent it from being reordered,
move, CSE, or LICM. Removing this restriction will allow `xxspltib` to
be hoisted out of loop bodies.
Commit: 3dafa486a6a41bacd31b3b1661fa44fa5e71520a
https://github.com/llvm/llvm-project/commit/3dafa486a6a41bacd31b3b1661fa44fa5e71520a
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
A clang/test/AST/ByteCode/libcxx/deref-to-array.cpp
Log Message:
-----------
[clang][bytecode] Don't narrow() when dereferencing to array type (#129524)
It doesn't make sense to do this if the result is supposed to be an
array.
Commit: 24794792858ae76ea593d4c1d5ea45c73b4fd87e
https://github.com/llvm/llvm-project/commit/24794792858ae76ea593d4c1d5ea45c73b4fd87e
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.h
Log Message:
-----------
[AMDGPU] Extend ComputePGMRSrc3 to gfx10+. NFCI. (#129289)
ComputePGMRSrc3 exists since gfx90a and gfx10+. Current code
only expects gfx90a. This is NFCI since we do not fill it on
gfx10+ yet.
Commit: a3584fb13eebeb736aba20ed1d0dfa77fc73c552
https://github.com/llvm/llvm-project/commit/a3584fb13eebeb736aba20ed1d0dfa77fc73c552
Author: Chris B <chris.bieneman at me.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/test/Driver/sanitizer-ld.c
Log Message:
-----------
[NFC] Fix Windows after #121115 (#129534)
Commit: 705decc860f1e7aa73476463ad98ce2ea293f7da
https://github.com/llvm/llvm-project/commit/705decc860f1e7aa73476463ad98ce2ea293f7da
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M .github/workflows/build-metrics-container.yml
M .github/workflows/ci-post-commit-analyzer.yml
M .github/workflows/commit-access-review.yml
M .github/workflows/docs.yml
M .github/workflows/email-check.yaml
M .github/workflows/issue-release-workflow.yml
M .github/workflows/issue-subscriber.yml
M .github/workflows/issue-write.yml
M .github/workflows/libclang-abi-tests.yml
M .github/workflows/llvm-bugs.yml
M .github/workflows/llvm-project-tests.yml
M .github/workflows/llvm-tests.yml
M .github/workflows/merged-prs.yml
M .github/workflows/new-prs.yml
M .github/workflows/pr-code-format.yml
M .github/workflows/pr-subscriber.yml
M .github/workflows/release-binaries.yml
M .github/workflows/release-documentation.yml
M .github/workflows/release-doxygen.yml
M .github/workflows/release-lit.yml
M .github/workflows/version-check.yml
Log Message:
-----------
[Github] Hash Pin Actions in Most Workflows (#129486)
This patch haspins all actions in most of the LLVM Github workflows.
This is something we try to do, but no one has gone through and combed
through all of the workflows before this patch.
Notably, this patch does not bump any major versions of actions just in
case there are subtle breaking changes introduced between versions that
could impact us. Also, this patch omits the libc/libc++ workflows so
that they can be split into separate PRs for the respective subproject
maintainers to review.
Commit: c9aefe10d78276bf59780b6e7dd834fae9ea91e7
https://github.com/llvm/llvm-project/commit/c9aefe10d78276bf59780b6e7dd834fae9ea91e7
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M .github/workflows/libc-fullbuild-tests.yml
M .github/workflows/libc-overlay-tests.yml
Log Message:
-----------
[Github][libc] Hash Pin Actions in Workflows (#129487)
This patch has pins actions in the libc Github workflows. Hash pinning
is a best practice as it ensures we are getting an exact action version,
which can help with reproducibility/reliability. It additionally
alleviates security concerns as an attacker can modify release assets,
potentially giving them access to tokens in privileged workflows.
Commit: 47c255b3e7291fd8a7a6fb9d2a183eaad75d5adb
https://github.com/llvm/llvm-project/commit/47c255b3e7291fd8a7a6fb9d2a183eaad75d5adb
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Dialect/Tosa/level_check.mlir
Log Message:
-----------
Revert "[mlir][tosa] Add several level checks (#128074)" (#129549)
This reverts commit ccf1bfc1d50a70260d200a9137ab7924dac029a8.
Commit: 201208998f65c25eca7b8006b1fb8b05d4b21214
https://github.com/llvm/llvm-project/commit/201208998f65c25eca7b8006b1fb8b05d4b21214
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.h
M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVMCInstLower.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h
Log Message:
-----------
[SPIR-V] Stop using Register to represent target specific virtual registers. (#129362)
These were using the virtual register encoding in Register which
required including Register.h in MC layer code which is a layering
violation.
This also required converting Register with bit 31 set to MCRegister
which should be an error. Register with bit 31 set should only be used
for codegen virtual register. I'd like to add assertions to enforce
this.
Migrate to MCRegister and manually create an encoding with bit 31 set.
WebAssembly also does this.
We could consider adding interfaces to MCRegister for target specific
virtual registers.
Commit: 3ce92e1c4f5436d3fd93fffada520e6be72c7a1e
https://github.com/llvm/llvm-project/commit/3ce92e1c4f5436d3fd93fffada520e6be72c7a1e
Author: George Burgess IV <george.burgess.iv at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
github: fix empty continuation line; remove trailing whitespace (#129535)
- Trailing whitespace shows up as red on my editor, so remove.
- Docker on my machine warns that having line continuations like:
```
sudo \
foo
```
is deprecated, and will become an error, so fix that up ahead of time.
Commit: 86fc248ff615ae5ce9f2ad10bbf49c9616d0be36
https://github.com/llvm/llvm-project/commit/86fc248ff615ae5ce9f2ad10bbf49c9616d0be36
Author: Nico Weber <thakis at chromium.org>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Core/BUILD.gn
Log Message:
-----------
[gn] port 50317ca13f6ad9
Commit: f3d4d1154799b32512b0fed52c9938f76b9264b5
https://github.com/llvm/llvm-project/commit/f3d4d1154799b32512b0fed52c9938f76b9264b5
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/utils/perf-training/perf-helper.py
Log Message:
-----------
[clang][cmake] Fix support for dynamic libraries in CLANG_BOLT
Simpler detection of dynamic library operands as the readelf one seems
to be unreliable (works on my setup, not on buildbots).
This is a follow-up to #127020
Commit: 39197938891b954d199473a58e64e237d1da8d46
https://github.com/llvm/llvm-project/commit/39197938891b954d199473a58e64e237d1da8d46
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
Log Message:
-----------
[WebAssembly] Avoid repeated hash lookups (NFC) (#129469)
Commit: 7c580893ea662b513da71a3da9ae4ab1b2dafc6b
https://github.com/llvm/llvm-project/commit/7c580893ea662b513da71a3da9ae4ab1b2dafc6b
Author: Abhilash Majumder <30946547+abhilash1910 at users.noreply.github.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/discard.ll
Log Message:
-----------
[NVPTX] Add Intrinsics for discard.* (#128404)
[NVPTX] Add Intrinsics for discard.*
This PR adds intrinsics for all variations of discard.*
* These intrinsics supports generic or global for all variations.
* The lowering is handled from nvvm to nvptx tablegen directly.
* Lit tests are added as part of discard.ll
* The generated PTX is verified with a 12.3 ptxas executable.
* Added docs for these intrinsics in NVPTXUsage.rst.
For more information, refer to the PTX ISA
<https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-discard>_.
---------
Co-authored-by: abmajumder <abmajumder at nvidia.com>
Co-authored-by: gonzalobg <65027571+gonzalobg at users.noreply.github.com>
Commit: fc81e264f933aa428db46b57ae08af68942ad476
https://github.com/llvm/llvm-project/commit/fc81e264f933aa428db46b57ae08af68942ad476
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn
Log Message:
-----------
[gn build] Port 5d7d66ba0d1a
Commit: e93cd15f9e8ab89774152e26b17d9030d0fe20a5
https://github.com/llvm/llvm-project/commit/e93cd15f9e8ab89774152e26b17d9030d0fe20a5
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/test/CodeGen/MIR/AArch64/lit.local.cfg
Log Message:
-----------
[win] Enable test/CodeGen/MIR/AArch64 on Windows (#122832)
Not sure why this was disabled in the first place (dates back to
<https://github.com/llvm/llvm-project/commit/fbe9c04c5f72cf3eca39793aafc92071ef13c046>),
but it appears to be working for me.
Commit: 0739ce88efa4481fe03100aa2eee284bc5ff9d81
https://github.com/llvm/llvm-project/commit/0739ce88efa4481fe03100aa2eee284bc5ff9d81
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp
Log Message:
-----------
[MC] Port initializeVariantKinds to ARM COFF and SystemZ GOFF
... so that they use the target-specific variantKindDescs instead of the
generic MCExpr one (which will go away as it's error-prone).
Commit: d2c4d1ec48b7c723307121164099fb2fa7d959a9
https://github.com/llvm/llvm-project/commit/d2c4d1ec48b7c723307121164099fb2fa7d959a9
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/test/Driver/fmemprof.cpp
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
Log Message:
-----------
[memprof] Export __memprof_default_options_str on Darwin (#128920)
The `-memprof-runtime-default-options` LLVM flag introduced in
https://github.com/llvm/llvm-project/pull/118874 creates the
`__memprof_default_options_str` symbol with `WeakAnyLinkage` on Darwin.
https://github.com/ellishg/llvm-project/blob/fa0202169af23419c4bcbf66eabd1beb6b6e8e34/llvm/lib/Transforms/Instrumentation/MemProfiler.cpp#L573-L576
This ensures Darwin passes `-exported_symbol
___memprof_default_options_str` to the linker so that the runtime
library has visibility into this symbol.
This will replace the earlier PR
https://github.com/llvm/llvm-project/pull/128615
Commit: a704e6587bfd974af053712c6da01fa04d74c31b
https://github.com/llvm/llvm-project/commit/a704e6587bfd974af053712c6da01fa04d74c31b
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/HLFIRTools.h
M flang/lib/Optimizer/Builder/HLFIRTools.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/test/HLFIR/simplify-hlfir-intrinsics-cshift.fir
Log Message:
-----------
[flang] Added alternative inlining code for hlfir.cshift. (#129176)
Flang generates slower code for `CSHIFT(CSHIFT(PTR(:,:,I),sh1,1),sh2,2)`
pattern in facerec than other compilers. The first CSHIFT can be done
as two memcpy's wrapped in a loop for the second dimension.
This does require creating a temporary array, but it seems to be faster,
than the current hlfir.elemental inlining.
I started with modifying the new index computation in
hlfir.elemental inlining: the new arith.select approach does enable
some vectorization in LLVM, but on x86 it is using gathers/scatters
and does not give much speed-up.
I also experimented with LoopBoundSplitPass
and InductiveRangeCheckElimination for a simple (not chained) CSHIFT
case, but I could not adjust them to split the loop with a condition
on the value of the IV into two loops with disjoint iteration spaces.
I thought if I could do it, I would be able to keep the hlfir.elemental
inlining mostly untouched, and then adjust the hlfir.elemental inlining
heuristics for the facerec case.
Since I was not able to make these pass work for me, I added a special
case inlining for CSHIFT(ARRAY,SH,DIM=1) via hlfir.eval_in_mem.
If ARRAY is not statically known to have the contiguous leading
dimension, there is a dynamic check for contiguity, which allows
exposing it to LLVM and enabling the rewrite of the copy loops
into memcpys. This approach is stepping on the toes of LoopVersioning,
but it is helpful in facerec case.
I measured ~6% speed-up on grace, and ~4% on zen4.
Commit: 44badc9810ede7843c65ac3e32e0820c13eaec85
https://github.com/llvm/llvm-project/commit/44badc9810ede7843c65ac3e32e0820c13eaec85
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineConcatVectorOps - use isSplatValue helper instead of matching specific VBROADCAST opcodes. (#129556)
Commit: 64c26c8f16aeff3b4ef99f171c771c08353cfbdf
https://github.com/llvm/llvm-project/commit/64c26c8f16aeff3b4ef99f171c771c08353cfbdf
Author: jimingham <jingham at apple.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M lldb/source/Target/Target.cpp
M lldb/test/API/commands/target/stop-hooks/TestStopHooks.py
Log Message:
-----------
Fix a bug copying the stop hooks from the dummy target. (#129340)
We didn't also copy over the next stop hook id, which meant we would
overwrite the stop hooks from the dummy target with stop hooks set after
they are copied over.
Commit: 8f4ee42d59976a9343d7576ef9a1fe2cf482a057
https://github.com/llvm/llvm-project/commit/8f4ee42d59976a9343d7576ef9a1fe2cf482a057
Author: Paul Osmialowski <pawel.osmialowski at arm.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M libcxx/test/std/input.output/iostream.format/std.manip/setfill_wchar_max.pass.cpp
M libcxx/test/std/re/re.alg/re.alg.match/awk.locale.pass.cpp
M libcxx/test/std/re/re.alg/re.alg.match/basic.locale.pass.cpp
M libcxx/test/std/re/re.alg/re.alg.match/ecma.locale.pass.cpp
M libcxx/test/std/re/re.alg/re.alg.match/extended.locale.pass.cpp
M libcxx/test/std/re/re.alg/re.alg.search/awk.locale.pass.cpp
M libcxx/test/std/re/re.alg/re.alg.search/basic.locale.pass.cpp
M libcxx/test/std/re/re.alg/re.alg.search/ecma.locale.pass.cpp
M libcxx/test/std/re/re.alg/re.alg.search/extended.locale.pass.cpp
M libcxx/test/std/re/re.traits/lookup_collatename.pass.cpp
Log Message:
-----------
[libc++][test] extend XFAIL clauses to cover Amazon Linux too (#129377)
The default triple of Amazon Linux on AArch64 is aarch64-amazon-linux,
see issue highlighded by PR #109263, somewhat serious linker issues are
encountered if any other triple is being used.
Unfortunately, this makes XFAIL lines like
`XFAIL: target=aarch64{{.*}}-linux-gnu` ineffective, making it
impossible to complete all of the check-cxx on Amazon Linux without
failing.
Commit: a0671758eb6e52a758bd1b096a9b421eec60204c
https://github.com/llvm/llvm-project/commit/a0671758eb6e52a758bd1b096a9b421eec60204c
Author: Fangrui Song <i at maskray.me>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/include/llvm/MC/MCExpr.h
M llvm/lib/MC/MCAsmInfo.cpp
M llvm/lib/MC/MCExpr.cpp
Log Message:
-----------
Reapply [MCExpr] Remove generic getVariantKindName and getVariantKindForName
They are error-prone as MCParser may parse a variant kind,
which cannot be handled by the target.
The replacement in MCAsmInfo should be used instead.
Follow-up to f244b8eed37a12539fb11b76e19ec7a7eb41dccc
Commit: d9ac5d0be6798ed1219ed42db64d8c768547132c
https://github.com/llvm/llvm-project/commit/d9ac5d0be6798ed1219ed42db64d8c768547132c
Author: OverMighty <its.overmighty at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M libc/docs/talks.rst
Log Message:
-----------
[libc][docs] Add links to Peter Smith's FOSDEM 2025 talk (#129555)
Commit: f44c18a97d68ff91f76e9c707b92a0929abac88b
https://github.com/llvm/llvm-project/commit/f44c18a97d68ff91f76e9c707b92a0929abac88b
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/docs/CodingStandards.rst
Log Message:
-----------
[NFC][CodingStandard] Fix text style for C++ keywords (#128932)
Fix C++ keywords in Restrict Visibility section to use `` (inline
literal) markup to be consistent with the rest of the doc.
Commit: 6e59282235b2ba7b5bbae968cafb15bab9656cff
https://github.com/llvm/llvm-project/commit/6e59282235b2ba7b5bbae968cafb15bab9656cff
Author: ofri frishman <ofri4321 at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tensor/TransformOps/TensorTransformOps.td
M mlir/include/mlir/Dialect/Tensor/Transforms/Transforms.h
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Tensor/TransformOps/TensorTransformOps.cpp
M mlir/lib/Dialect/Tensor/Transforms/ReshapePatterns.cpp
M mlir/test/Dialect/Linalg/transform-op-fuse.mlir
A mlir/test/Dialect/Tensor/bubble-up-extract-slice-op.mlir
Log Message:
-----------
[MLIR] Add pattern to bubble up tensor.extract_slice (#126898)
Add a pattern that bubbles up tensor.extract_slice through
tensor.expand_shape, and add a transform op to tensor dialect
to directly use this pattern.
This pattern enables tiling and fusing op chains which contain
tensor.expand_shape if added as a cleanup pattern of tile and fuse
utility.
Without this pattern that would not be possible, as
tensor.expand_shape does not implement the tiling interface.
In addition, registering this pattern as a cleanup pattern for
transform.structured.fuse.
The pattern was first implement in IREE project by
Quinn Dawkins and is being upstreamed.
---------
Co-authored-by: Quinn Dawkins <quinn.dawkins at gmail.com>
Commit: af464c6d53c1873101e312048d35d1daed27e407
https://github.com/llvm/llvm-project/commit/af464c6d53c1873101e312048d35d1daed27e407
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/test/CXX/temp/temp.res/temp.local/p6.cpp
Log Message:
-----------
[Clang][diagnostics] Fix structured binding shadows template param loc (#129116)
Fix structured binding shadows template parameter location
Fixes: #129060
Commit: ab30df470af91427abf03f99f7f3517129464ca9
https://github.com/llvm/llvm-project/commit/ab30df470af91427abf03f99f7f3517129464ca9
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/test/CIR/func-simple.cpp
Log Message:
-----------
[CIR] Upstream floating point literal expressions (#129304)
This change adds support for floating point literal expressions
Commit: 079557c3d4b8f42d6691d4a131bd78963d0c77bd
https://github.com/llvm/llvm-project/commit/079557c3d4b8f42d6691d4a131bd78963d0c77bd
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-invalid.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
Log Message:
-----------
[mlir][tosa] Add verifiers for FFT2d and RFFT2d (#129273)
Adds checks for element types and input/output shapes.
Signed-off-by: Luke Hutton <luke.hutton at arm.com>
Commit: 4dd29ebb8dc563be37244612f44537e8eff33c32
https://github.com/llvm/llvm-project/commit/4dd29ebb8dc563be37244612f44537e8eff33c32
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/Descriptor.h
Log Message:
-----------
[clang][bytecode][NFC] Move incorrect LLVM_PREFERRED_TYPE attribute (#128740)
Looks like this was accidentally added after the bitfield and thus
didn't work.
Commit: 6c9a9d9fe2371e586be8ecba8b9a2d129d1c0226
https://github.com/llvm/llvm-project/commit/6c9a9d9fe2371e586be8ecba8b9a2d129d1c0226
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.h
A llvm/test/CodeGen/AMDGPU/inst-prefetch-hint.ll
Log Message:
-----------
[AMDGPU] Set inst_pref_size to maximum (#126981)
On gfx11 and gfx12 set initial instruction prefetch size to a
minimum of kernel size and maximum allowed value.
Fixes: SWDEV-513122
Commit: 70b95d16645dfe1e8d76bdf94e791d74ad36e780
https://github.com/llvm/llvm-project/commit/70b95d16645dfe1e8d76bdf94e791d74ad36e780
Author: Nirvedh Meshram <96096277+nirvedhmeshram at users.noreply.github.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/test/Dialect/Linalg/reshape_fusion.mlir
Log Message:
-----------
[mlir][linalg] Retain Op Type of linalg ops in fuseWithReshapeByExpansion pattern (#129128)
This PR preserve linalg Op types for certain named ops such as Fill,
Copy and Transpose instead of fusion always resulting in a generic Op.
---------
Signed-off-by: Nirvedh Meshram <nirvedh at gmail.com>
Commit: 28fc00b10ef72a3573905826ecdee693fd620959
https://github.com/llvm/llvm-project/commit/28fc00b10ef72a3573905826ecdee693fd620959
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/DebugInfo/GSYM/DwarfTransformer.cpp
M llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-merged-callsites-dsym.yaml
Log Message:
-----------
[GSYM] Use debug line offsets during GSYM creation (#129196)
This patch introduces support for the `DW_AT_LLVM_stmt_sequence`
attribute in the GSYM DWARF transformer. With this change, the DWARF
GSYM creation process can now accurately associate debug information
with the correct functions, even when multiple functions have been
merged together.
The `macho-gsym-merged-callsites-dsym.yaml` test data is regenerated to
include the fixes in the DWARF linker
(https://github.com/llvm/llvm-project/pull/128953) and the test is
updated to check that debug data is correctly associated for merged
functions.
Commit: dc1ff4145a3b3ab8d1bbe71fb05bfe15d8bbd4ae
https://github.com/llvm/llvm-project/commit/dc1ff4145a3b3ab8d1bbe71fb05bfe15d8bbd4ae
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/test/mlir-tblgen/constraint-unique.td
M mlir/test/mlir-tblgen/op-attribute.td
M mlir/test/mlir-tblgen/op-decl-and-defs.td
M mlir/test/mlir-tblgen/op-format.td
M mlir/test/mlir-tblgen/op-result.td
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
Log Message:
-----------
[mlir][tblgen] Migrate tests to properties for attributes, fix remove*Attr() (#123505)
The only in-tree user of `bit usePropertiesForAttributes = 0;` was a
series of tests for the output of -gen-op-{decls,defs}. This commit
updates those tests to match the rest of the repository.
In the short term, this is intended to enable testing upcoming updates
to collective builders. In the long term, this is a step in the removal
of usePropertiesForAttributes = 0.
One side effect of these tests updates was the realization that the
autogenerated implementations of removeFooAttr() were not returning the
value of the removed attribute. This issue has been addressed and the
tests have been updated to reflect the change. This is the only
functionality change in this PR.
Commit: 25713ed85fd327f4733b2ac6083c23464aa9c646
https://github.com/llvm/llvm-project/commit/25713ed85fd327f4733b2ac6083c23464aa9c646
Author: Sarah Spall <sarahspall at microsoft.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/test/CodeGenHLSL/builtins/max.hlsl
M clang/test/CodeGenHLSL/builtins/min.hlsl
Log Message:
-----------
[HLSL] Add additional overloads for min and max to allow for mixed scalar and vector arguments (#129334)
Add additional overloads for min and max to support
min(vector<T,N>, T) and min(T, vector<T,N>)
max(vector<T,N>, T) and max(T, vector<T,N>)
Add tests
Closes #128231
Commit: 41e58b6737ee8b5fbd019fb6a6986d94c5f40566
https://github.com/llvm/llvm-project/commit/41e58b6737ee8b5fbd019fb6a6986d94c5f40566
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/RISCV/spillcost.ll
Log Message:
-----------
[SLP][NFC]Add a test for 2 spilled vector values spilled in diamond shaped control flow
Commit: 4fd5d935a3d30d20aed7697be5d8bb76dae8eab6
https://github.com/llvm/llvm-project/commit/4fd5d935a3d30d20aed7697be5d8bb76dae8eab6
Author: Brendan Sweeney <brs at eecs.berkeley.edu>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
Log Message:
-----------
[RISCV] Emitting proper atomic ABI tag when Zalasr is enabled (#121017)
When Zalasr is enabled, it will emit the A7 atomic ABI tag. Zalasr is
the load-acquire and store-release extension, and the reason A7 (and
A6S) exists is to support it.
The A7 atomic ABI is compatible with A6S (which is what is currently
emitted as the tag), but A7 is not compatible with A6C, while A6C and
A6S are compatible.
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-atomic.adoc#risc-v-atomics-mappings
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_atomic_abi-14-uleb128version
Commit: 83f87212016c3be50484faee3c744a3417df175f
https://github.com/llvm/llvm-project/commit/83f87212016c3be50484faee3c744a3417df175f
Author: Kelvin Li <kkwli at users.noreply.github.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/Target.cpp
M flang/test/Fir/struct-passing-loongarch64-byreg.fir
A flang/test/Fir/struct-passing-powerpc64-aix-byval.fir
A flang/test/Fir/struct-passing-ppc64le-byval.fir
A flang/test/Fir/struct-return-powerpc64-aix.fir
A flang/test/Fir/struct-return-ppc64le.fir
Log Message:
-----------
[flang] handle passing bind(c) derived type by value for ppc64le and powerpc64-aix (#128780)
Commit: a9b2e31fb0fbb6ce3cbc4ae2b77301c95647b617
https://github.com/llvm/llvm-project/commit/a9b2e31fb0fbb6ce3cbc4ae2b77301c95647b617
Author: Jean-Didier PAILLEUX <jean-didier.pailleux at sipearl.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Semantics/check-call.cpp
M flang/test/Semantics/collectives05.f90
Log Message:
-----------
[flang] Define CO_REDUCE intrinsic procedure (#125115)
Define the intrinsic `CO_REDUCE` and add semantic checks.
A test was already present but was at `XFAIL`. It has been modified to
take new messages into the output.
Commit: 08dc81bd2917148e119819b3c668d0c870f96bb5
https://github.com/llvm/llvm-project/commit/08dc81bd2917148e119819b3c668d0c870f96bb5
Author: Augie Fackler <augie at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/llvm-config.h
Log Message:
-----------
[bazel] fixes to make Telemetry work in lldb
Previously telemetry was optional at build-time in such a way that none
of it was built at all, but llvm/llvm-project at 159b872b3736 changed that
and now it's optional in a different way so we need to have it available
in the bazel BUILD graph.
Commit: 1fc49ff59354ba6f6262018d52ff4e88a54372f8
https://github.com/llvm/llvm-project/commit/1fc49ff59354ba6f6262018d52ff4e88a54372f8
Author: Mirza Halilčević <109971222+mirza-halilcevic at users.noreply.github.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/include/mlir/Dialect/AMDGPU/Utils/Chipset.h
M mlir/include/mlir/IR/Types.h
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/ArithToAMDGPU/ArithToAMDGPU.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/lib/IR/Types.cpp
A mlir/test/Conversion/AMDGPUToROCDL/8-bit-floats-ocp.mlir
A mlir/test/Conversion/ArithToAMDGPU/8-bit-float-saturation-ocp.mlir
A mlir/test/Conversion/ArithToAMDGPU/8-bit-floats-ocp.mlir
Log Message:
-----------
[MLIR][AMDGPU] Add OCP FP8 support for new hardware (#127728)
(Continuing from #106160)
This PR addresses remaining review comments from the original PR.
Original PR Description
---
Upcoming hardware (gfx12 and some future gfx9) will support the OCP
8-bit float formats for their matrix multiplication intrinsics and
conversion operations, retaining existing opcodes and compiler builtins.
This commit adds support for these types to the MLIR wrappers around
such operations, ensuring that the OCP types aren't used to generate
those builtins on hardware that doesn't expect that format and,
conversely, to ensure that the pre-OCP formats aren't used on new
hardware.
---------
Signed-off-by: Mirza Halilcevic <mirza.halilcevic at amd.com>
Co-authored-by: Paul Fuqua <pf at acm.org>
Co-authored-by: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Commit: 4ca8ea8c972ae05a891687eda6704ec607184fae
https://github.com/llvm/llvm-project/commit/4ca8ea8c972ae05a891687eda6704ec607184fae
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/Headers/amdgpuintrin.h
M clang/lib/Headers/nvptxintrin.h
Log Message:
-----------
[Clang] Fix GPU intrinsic helpers incorrectly sign extending (#129560)
Summary:
These return values are actually signed, meaning that casting will
extend it and then all the bits will be one.
Commit: 39402cde6149b5a9f5d48455959df350dfe63017
https://github.com/llvm/llvm-project/commit/39402cde6149b5a9f5d48455959df350dfe63017
Author: Alexander Shaposhnikov <ashaposhnikov at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M compiler-rt/test/ubsan/TestCases/Float/cast-overflow.cpp
Log Message:
-----------
[compiler-rt][ubsan] Refactor cast-overflow test (#129460)
This PR cleans up cast-overflow.cpp, more specifically:
1. avoid using undefined value as an exit code (old case `9`)
2. narrowing conversions are allowed to produce `inf` and they are
well-defined. Remove dead code (old case `8`)
3. the same applies to the conversion int -> float16. Remove dead code
(old case `7`)
See also
https://clang.llvm.org/docs/UndefinedBehaviorSanitizer.html#:~:text=%2Dfsanitize%3Dfloat%2Dcast,to%20integer%20types.
Currently ubsan doesn't properly detect UB on float16 -> int casts, I
have a fix for that (will send as a separate PR).
Commit: b971d4d7c80821d648015281b7926ee6f93dccc9
https://github.com/llvm/llvm-project/commit/b971d4d7c80821d648015281b7926ee6f93dccc9
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
A bolt/lib/Target/AArch64/AArch64MCSymbolizer.cpp
A bolt/lib/Target/AArch64/AArch64MCSymbolizer.h
M bolt/lib/Target/AArch64/CMakeLists.txt
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
Log Message:
-----------
[BOLT][AArch64] Add symbolizer for AArch64 disassembler. NFCI (#127969)
Add AArch64MCSymbolizer that symbolizes `MCInst` operands during
disassembly. The symbolization was previously done in
`BinaryFunction::disassemble()`, but it is also required by
`scanExternalRefs()` for "lite" mode functionality. Hence, similar to
x86, I've implemented the symbolizer interface that uses
`BinaryFunction` relocations to properly create instruction operands. I
expect the result of the disassembly to be identical after the change.
AArch64 disassembler was not calling `tryAddingSymbolicOperand()` for
`MOV` instructions. Fix that. Additionally, the disassembler marks `ldr`
instructions as branches by setting `IsBranch` parameter to true. Ignore
the parameter and rely on `MCPlusBuilder` interface instead.
I've modified `--check-encoding` flag to check symolization of operands
of instructions that have relocations against them.
Commit: 9f879dea2e35a8f4147c64ebcb6d4b61167a110a
https://github.com/llvm/llvm-project/commit/9f879dea2e35a8f4147c64ebcb6d4b61167a110a
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/utils/gn/secondary/bolt/lib/Target/AArch64/BUILD.gn
Log Message:
-----------
[gn build] Port b971d4d7c808
Commit: 87f837cb26f6ab543d70c42f1961b125102bff2c
https://github.com/llvm/llvm-project/commit/87f837cb26f6ab543d70c42f1961b125102bff2c
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Remove unneeded classof with VPHeaderRecipe args (NFC).
The extra classof implementation is not needed any longer.
Commit: 2b509ecf2dadcd5ea81b15c85f116c20b9b1f649
https://github.com/llvm/llvm-project/commit/2b509ecf2dadcd5ea81b15c85f116c20b9b1f649
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/include/clang/AST/Type.h
Log Message:
-----------
[AST] Reorder fields in FunctionTypeBitfields to avoid splitting a field across 32 bit boundary
Fixes #129521.
Commit: 36a2d7bf1bd91f4c611c60708f8637bff18ecdbc
https://github.com/llvm/llvm-project/commit/36a2d7bf1bd91f4c611c60708f8637bff18ecdbc
Author: JP Hafer <146973677+jph-13 at users.noreply.github.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/IR/AsmWriter.cpp
Log Message:
-----------
[AsmWriter] Combine IsConstant and GetConstant (NFCI) (#129288)
There was an assert in GetConstant checked if Bound is constant.
However, GetConstant was only called when IsConstant==true.
This refactor attempts to get rid of the assert by combining GetConstant
and IsContstant.
Commit: 2cb7b4e0cdd2b7439618622b9dcf2bb8b330fd6a
https://github.com/llvm/llvm-project/commit/2cb7b4e0cdd2b7439618622b9dcf2bb8b330fd6a
Author: Augie Fackler <augie at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[bazel] fix missing dep on //llvm:config in //lldb:Core
Commit: eee3db5421040cfc3eae6e92ed714650a6f741fa
https://github.com/llvm/llvm-project/commit/eee3db5421040cfc3eae6e92ed714650a6f741fa
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZInstrInfo.td
Log Message:
-----------
[SystemZ] Change operand type for CKSM intrstruction. (#129572)
The current definition of the CKSM instruction uses GR64 for the first
operand. However, according to the Principles Of Operation the bits 0-31
of the first operand always remain unchanged. This PR changes the first
operand to GR32 to model this.
This has no further implication as this instruction is not used during
code generation.
Commit: 1c4e0f6a54538972741ab1c7a5fcc5e5efd3d90c
https://github.com/llvm/llvm-project/commit/1c4e0f6a54538972741ab1c7a5fcc5e5efd3d90c
Author: Michael Spencer <bigcheesegs at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/lib/Lex/Pragma.cpp
A clang/test/Modules/clang-pragmas.c
Log Message:
-----------
[clang] Add #pragma clang __debug module_lookup (#129158)
This can be used to trigger implicit module map lookup without also
importing the module. This can be useful for debugging as it avoids
loading the module map from the AST file, which has slightly different
semantics.
Commit: 8f971ca1d939d65ca077ec5f86cd33652d09feee
https://github.com/llvm/llvm-project/commit/8f971ca1d939d65ca077ec5f86cd33652d09feee
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
R flang/include/flang/Lower/DumpEvaluateExpr.h
A flang/include/flang/Semantics/dump-expr.h
M flang/lib/Lower/CMakeLists.txt
M flang/lib/Lower/ConvertExpr.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
R flang/lib/Lower/DumpEvaluateExpr.cpp
M flang/lib/Semantics/CMakeLists.txt
A flang/lib/Semantics/dump-expr.cpp
Log Message:
-----------
[flang] Move DumpEvaluateExpr from Lower to Semantics (#128723)
Since evaluate::Expr can show up in the parse tree in the semantic
analysis step, make it possible to dump its structure in the Semantics
module.
The Lower module depends on Semantics, so the code is still accessible
in it.
Commit: 2d0eb5df4fb4e028e86310e631789b65cb009bf1
https://github.com/llvm/llvm-project/commit/2d0eb5df4fb4e028e86310e631789b65cb009bf1
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M lld/COFF/Driver.cpp
M lld/test/COFF/arm64x-includeoptional.s
Log Message:
-----------
[LLD][COFF] Add support for -includeglob on ARM64X (#129515)
Include symbols from both symbol tables.
Commit: fd9a882ce31cb0a53dba63528c15d76f088854b7
https://github.com/llvm/llvm-project/commit/fd9a882ce31cb0a53dba63528c15d76f088854b7
Author: Augie Fackler <augie at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/bolt/BUILD.bazel
Log Message:
-----------
[bazel] add missing header to bolt build file
Commit: 7d650bf3318b51cee7f89c4792e0f9b36bcdcc46
https://github.com/llvm/llvm-project/commit/7d650bf3318b51cee7f89c4792e0f9b36bcdcc46
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeDepthwise.cpp
M mlir/test/Dialect/Tosa/tosa-decompose-depthwise.mlir
Log Message:
-----------
[mlir][tosa] Fix several bugs in `DepthwiseConv2DIsMul` (#129210)
This PR fixes several bugs in `DepthwiseConv2DIsMul`:
- The DepthwiseConv2DOp should restrict the types to integer or float to
prevent a crash.
- `notifyMatchFailure` should be called before creating the new
operations.
Commit: f2473bc31eee20bb55afa2890490887541501724
https://github.com/llvm/llvm-project/commit/f2473bc31eee20bb55afa2890490887541501724
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M lld/COFF/Config.h
M lld/COFF/Driver.cpp
M lld/COFF/Driver.h
M lld/COFF/DriverUtils.cpp
M lld/COFF/SymbolTable.cpp
M lld/COFF/SymbolTable.h
A lld/test/COFF/arm64x-comm.s
Log Message:
-----------
[LLD][COFF] Support -aligncomm directives on ARM64X (#129513)
Commit: a21ae2f04f529b6b62d83786e867e9d7dc169369
https://github.com/llvm/llvm-project/commit/a21ae2f04f529b6b62d83786e867e9d7dc169369
Author: Mats Jun Larsen <mats at jun.codes>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/CodeGen/CGObjCGNU.cpp
Log Message:
-----------
[CodeGen][ObjCGNU] Replace PointerType::getUnqual(Type) with opaque pointer version (NFC) (#128715)
Follow-up to #123569
Commit: d6599fc3b9e1cf1659999e8a755ae1d68bc3b4b3
https://github.com/llvm/llvm-project/commit/d6599fc3b9e1cf1659999e8a755ae1d68bc3b4b3
Author: Thurston Dang <thurston at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-st1.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-st1_lane.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-st1_origins.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-tbl.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
R llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_tbl.ll
R llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
R llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst.ll
R llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_lane.ll
R llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_origins.ll
Log Message:
-----------
[msan][NFC] Rename NEON tests and fix comment (#127926)
This renames the neon_* tests to be more consistent with the original files that they were forked from. This makes it easier for maintainers to see which test files may need to be ported to MSan.
It also fixes the header comment for llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt.ll (instrumentation was updated in #126136 aka e9e6ba6a5e2a4ca7386861136196903febb9968b, but the comment was not).
Commit: d5cec386c14ac46ee252da29f5bd766db0adb6d0
https://github.com/llvm/llvm-project/commit/d5cec386c14ac46ee252da29f5bd766db0adb6d0
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/include/clang-c/Index.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/AST/TextNodeDumper.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/StmtNodes.td
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/SemaOpenACC.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Sema/SemaExceptionSpec.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
A clang/test/AST/ast-print-openacc-cache-construct.cpp
M clang/test/ParserOpenACC/parse-cache-construct.c
M clang/test/ParserOpenACC/parse-cache-construct.cpp
A clang/test/SemaOpenACC/cache-construct-ast.cpp
A clang/test/SemaOpenACC/cache-construct.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CXCursor.cpp
Log Message:
-----------
[OpenACC] Implement 'cache' construct AST/Sema
This statement level construct takes no clauses and has no associated
statement, and simply labels a number of array elements as valid for
caching. The implementation here is pretty simple, but it is a touch of
a special case for parsing, so the parsing code reflects that.
Commit: 94fad113070878c37f00699ca9d74b6216910af5
https://github.com/llvm/llvm-project/commit/94fad113070878c37f00699ca9d74b6216910af5
Author: Mats Jun Larsen <mats at jun.codes>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/CodeGen/ABIInfoImpl.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.h
M clang/lib/CodeGen/ItaniumCXXABI.cpp
Log Message:
-----------
[CodeGen] Replace PointerType::getUnqual(Type) with opaque pointer version (NFC) (#128711)
pointer version (NFC)
Follow-up to #123569
Commit: 8179bcfe56ef3361827a644a1ab4f515ad2583aa
https://github.com/llvm/llvm-project/commit/8179bcfe56ef3361827a644a1ab4f515ad2583aa
Author: Peng Sun <peng.sun at arm.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-invalid.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/lib/Dialect/Tosa/TosaTestPasses.cpp
Log Message:
-----------
[mlir][tosa] Make RESCALE op input_unsigned and output_unsigned attributes required (#129339)
Previously, the input_unsigned and output_unsigned attributes on the
RESCALE op were optional. This commit updates them to be required,
ensuring compliance with the TOSA V1.0 Specification.
Signed-off-by: Peng Sun <peng.sun at arm.com>
Co-authored-by: James Ward <james.ward at arm.com>
Commit: 3ff6fb68d7aadf570a15a8a068ce7b24851e136d
https://github.com/llvm/llvm-project/commit/3ff6fb68d7aadf570a15a8a068ce7b24851e136d
Author: Jacob Lalonde <jalalonde at fb.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M lldb/bindings/interface/SBProgressDocstrings.i
M lldb/include/lldb/API/SBProgress.h
M lldb/source/API/SBProgress.cpp
M lldb/test/API/python_api/sbprogress/TestSBProgress.py
Log Message:
-----------
[LLDB][SBProgress] Add a finalize method (#128966)
This patch adds a finalize method which destroys the underlying RAII
SBProgress. My primary motivation for this is so I can write better
tests that are non-flaky, but after discussing with @clayborg in my DAP
message improvement patch (#124648) this is probably an essential API
despite that I originally argued it wasn't.
Commit: f9338db2cbd219fb9819d30531dafd3a24e0e00d
https://github.com/llvm/llvm-project/commit/f9338db2cbd219fb9819d30531dafd3a24e0e00d
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M lldb/unittests/SymbolFile/DWARF/XcodeSDKModuleTests.cpp
Log Message:
-----------
[lldb][test] XcodeSDKModuleTests: remove non-deterministic source mapping checks (#129526)
This assertion was added to check that `RegisterXcodeSDK` will correctly
update the source mappings of the module. However, the source mapping
will only get updated if the `Host::RunShellCommand` call to `xcrun`
succeeded. Even if `xcrun` failed to find an SDK, the source mappings
would get an entry. But if the shell invocation itself failed, then the
mappings are not updated (see
https://github.com/llvm/llvm-project/blob/f6212c1cd3d8b827c7d7e2f6cf54b135c27eacc6/lldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm#L424-L444).
This means depending on how slow `xcrun` is on a given host, this test
may fail. On my machine this happens consistently in debug and release
builds.
This patch removes this flakey assertion. We unfortunately lost some
test coverage here but I'm not sure there's great alternatives unless we
either:
1. Mock the `xcrun` call somehow (we could maybe pass a callable around
which defaults to `xcrun` in non-test code?)
2. Make a `xcrun` time-out not an error either?
Commit: da293b850be3fc5b2047769f55823e41b07625c9
https://github.com/llvm/llvm-project/commit/da293b850be3fc5b2047769f55823e41b07625c9
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M lldb/include/lldb/Host/macosx/HostInfoMacOSX.h
M lldb/include/lldb/Utility/XcodeSDK.h
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Utility/XcodeSDK.cpp
M lldb/unittests/SymbolFile/DWARF/XcodeSDKModuleTests.cpp
M lldb/unittests/Utility/XcodeSDKTest.cpp
Log Message:
-----------
[lldb][HostInfoMacOSX] Try to use DW_AT_LLVM_sysroot instead of xcrun when looking up SDK (#128712)
`GetSDKRoot` uses `xcrun` to find an SDK root path for a given SDK
version string. But if the SDK doesn't exist in the Xcode installations,
but instead lives in the `CommandLineTools`, `xcrun` will fail to find
it. Negative searches for an SDK path cost a lot (a few seconds) each
time `xcrun` is invoked. We do cache negative results in
`find_cached_path` inside LLDB, but we would still pay the price on
every new debug session the first time we evaluate an expression. This
doesn't only cause a noticable delay in running the expression, but also
generates following error:
```
error: Error while searching for Xcode SDK: timed out waiting for shell command to complete
(int) $0 = 42
```
In this patch we avoid these possibly expensive calls to `xcrun` by
checking the `DW_AT_LLVM_sysroot`, and if it exists, using that as the
SDK path. We need an explicit check for the `CommandLineTools` path
before we call `RegisterXcodeSDK`, because that will try to call
`xcrun`. This won't prevent other uses of `GetSDKRoot` popping up that
cause us to make expensive `xcrun` calls, but for now this addresses the
regression in the expression evaluator. We also had to adjust the
`XcodeSDK::Merge` logic to update the sysroot. There is one case for
which this wouldn't make sense: if a CU was compiled with
`CommandLineTools` and a different one with an older internal SDK, in
that case we would update the `CommandLineTools` sysroot with a
`.Internal.sdk` prefix, which won't possibly exist for
`CommandLineTools`. I added a unit-test for this. Not sure if we want to
explicitly detect and disallow this, given it's quite a niche scenario.
rdar://113619904
rdar://113619723
Commit: 186ae8c06ae00d439e5ac4e2a6b80d5aeac7a187
https://github.com/llvm/llvm-project/commit/186ae8c06ae00d439e5ac4e2a6b80d5aeac7a187
Author: Nirvedh Meshram <96096277+nirvedhmeshram at users.noreply.github.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
Log Message:
-----------
[NFC][mlir][linalg] Make conv_3d_ncdhw_fcdhw consistent with 2D variant (#129547)
Other convolutions such as conv_2d_nchw_fchw have a output affine map
with no permutations and the input and the filter map are adjusted
accordingly. This makes conv_3d_ncdhw_fcdhw a stand out so this PR
changes the affine map to be consistent with other variants.
Commit: f98718c9a169d90e676f877c5b6761b22f424b73
https://github.com/llvm/llvm-project/commit/f98718c9a169d90e676f877c5b6761b22f424b73
Author: Mats Jun Larsen <mats at jun.codes>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
Log Message:
-----------
Remove leftover unused variable from #128711
Commit: f457c56240ee293c7ac72c7e6fc8150adb0a4a36
https://github.com/llvm/llvm-project/commit/f457c56240ee293c7ac72c7e6fc8150adb0a4a36
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/RISCV/spillcost.ll
Log Message:
-----------
[SLP][NFC]Update the test to check correctly the spill cost
Commit: 3ce67a81fac301e7a308c7c6c08e0abd883972e9
https://github.com/llvm/llvm-project/commit/3ce67a81fac301e7a308c7c6c08e0abd883972e9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[TableGen] Remove unnecessary use of utostr to print a byte. NFC
We can cast to unsigned instead.
Commit: efb880de11f8fa3646c04032c0a2c9bded1935d7
https://github.com/llvm/llvm-project/commit/efb880de11f8fa3646c04032c0a2c9bded1935d7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[TableGen] Fix incorrect comment. NFC
Commit: 313b71fc1a9ae17ea5ecba8afcb4e5b80e1f4043
https://github.com/llvm/llvm-project/commit/313b71fc1a9ae17ea5ecba8afcb4e5b80e1f4043
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
Log Message:
-----------
[RISCV] Simplify tracking of tracking and encoding of push/pop in RISCVFrameLowering. NFC (#129343)
Previously we calculated the max register id. Then converted it to the number
of registers and encoding. Then converted number of registers to stack
size. Then saved number of registers, encoding, and stack size to
MachineFunctionInfo.
This patch removes the calculation of max register id, and instead
calculates the number of registers. The encoding is removed from
MachineFunctionInfo in favor of converting the number of registers to
encoding at the time of use.
Commit: 3c90c900ba5ef9f0cb5808c73c388d3ee21cb683
https://github.com/llvm/llvm-project/commit/3c90c900ba5ef9f0cb5808c73c388d3ee21cb683
Author: TatWai Chong <tatwai.chong at arm.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Dialect/Tosa/level_check.mlir
Log Message:
-----------
[mlir][tosa] Add several level checks (#129580)
Add the following types of level check to consolidate the level validity
- Complete rank level checks for operations.
- Add MAX_LOG2_SIZE level check: The maximum value is 63 when the level
is set to "none" and 31 when the level is set to "8K".
- Add MAX_TENSOR_LIST_SIZE level check : The maximum value is 256 when
the level is set to "none" and 64 when the level is set to "8K".
- TOSA 1.0 spec does not allow operations with dynamic shapes, so an
error should be raised instead.
Co-authored-by: Tai Ly <tai.ly at arm.com>
Commit: dfc5f37e3a62a93ce16935cea1d9822bec649a2b
https://github.com/llvm/llvm-project/commit/dfc5f37e3a62a93ce16935cea1d9822bec649a2b
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Move onlyFirstLaneUsed to VPWidenInductionRecipe (NFC).
Move onlyFirstLaneUsed from VPWidenIntOrFpInductionRecipe and
VPWidenPointerInduction to VPWidenInductionRecipe. Also mark step value
as having only its first lane used.
Commit: b2ba43a9c1193f1d90ad9d30dada85caebd2c56d
https://github.com/llvm/llvm-project/commit/b2ba43a9c1193f1d90ad9d30dada85caebd2c56d
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M flang/lib/Semantics/check-declarations.cpp
A flang/test/Semantics/generic13.f90
Log Message:
-----------
[flang] Refine checking of type-bound generics (#129292)
I merged a patch yesterday
(https://github.com/llvm/llvm-project/pull/128980) that strengthened
error detection of indistinguishable specific procedures in a type-bound
generic procedure, and broke a couple of tests. Refine the check so that
it doesn't flag valid cases of overridden bindings, and add a thorough
test with all of the boundary cases that I can think of.
Commit: 79a25e11fe119520e7cb70118df18e199217c891
https://github.com/llvm/llvm-project/commit/79a25e11fe119520e7cb70118df18e199217c891
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M flang/include/flang/Evaluate/characteristics.h
M flang/include/flang/Evaluate/tools.h
M flang/lib/Evaluate/check-expression.cpp
M flang/lib/Evaluate/fold-logical.cpp
M flang/lib/Evaluate/fold.cpp
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Evaluate/shape.cpp
M flang/lib/Evaluate/tools.cpp
M flang/lib/Lower/ConvertConstant.cpp
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/data-to-inits.cpp
M flang/lib/Semantics/definable.cpp
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/pointer-assignment.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Evaluate/folding06.f90
M flang/test/Lower/HLFIR/null.f90
M flang/test/Semantics/associated.f90
M flang/test/Semantics/call27.f90
M flang/test/Semantics/null01.f90
Log Message:
-----------
[flang] Further work on NULL(MOLD=allocatable) (#129345)
Refine handling of NULL(...) in semantics to properly distinguish
NULL(), NULL(objectPointer), NULL(procPointer), and NULL(allocatable)
from each other in relevant contexts.
Add IsNullAllocatable() and IsNullPointerOrAllocatable() utility
functions. IsNullAllocatable() is true only for NULL(allocatable); it is
false for a bare NULL(), which can be detected independently with
IsBareNullPointer().
IsNullPointer() now returns false for NULL(allocatable).
ALLOCATED(NULL(allocatable)) now works, and folds to .FALSE.
These utilities were modified to accept const pointer arguments rather
than const references; I usually prefer this style when the result
should clearly be false for a null argument (in the C sense), and it
helped me find all of their use sites in the code.
Commit: f6e83664e01e8dcb9bf241dd0154ff3adcc2e876
https://github.com/llvm/llvm-project/commit/f6e83664e01e8dcb9bf241dd0154ff3adcc2e876
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M flang/lib/Semantics/check-declarations.cpp
M flang/test/Semantics/coarrays02.f90
M flang/test/Semantics/init01.f90
Log Message:
-----------
[flang] Improve two coarray error messages (#129597)
Two messages that complain about local variables mention that they don't
have the SAVE attribute; in both cases, it would be okay if they were
ALLOCATABLE instead. Clarify the messages.
Commit: edb7292a511171fb1fe75f85fc85464b91130a8f
https://github.com/llvm/llvm-project/commit/edb7292a511171fb1fe75f85fc85464b91130a8f
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/include/mlir/IR/OperationSupport.h
M mlir/lib/IR/AsmPrinter.cpp
M mlir/unittests/IR/OperationSupportTest.cpp
Log Message:
-----------
[mlir] Add use nameloc to OpPrintingFlags (#129584)
Commit: cb4f24b0e5c4e7c463e59120af4f13ab81519047
https://github.com/llvm/llvm-project/commit/cb4f24b0e5c4e7c463e59120af4f13ab81519047
Author: TatWai Chong <tatwai.chong at arm.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Dialect/Tosa/level_check.mlir
Log Message:
-----------
Revert "[mlir][tosa] Add several level checks" (#129602)
Reverts llvm/llvm-project#129580
There is a lit test failure reported in
https://lab.llvm.org/buildbot/#/builders/116/builds/11023
Commit: e1fd681837b85563e186f3739623cfa6653a722c
https://github.com/llvm/llvm-project/commit/e1fd681837b85563e186f3739623cfa6653a722c
Author: Douglas Gliner <Douglas.Gliner at sony.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticIDs.h
Log Message:
-----------
Bump DIAG_SIZE_LEX since we've hit the limit downstream as of 1c4e0f6.
Commit: 829401fe3ca1486285f5ef32865d189747a91305
https://github.com/llvm/llvm-project/commit/829401fe3ca1486285f5ef32865d189747a91305
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
A llvm/docs/CIBestPractices.rst
M llvm/docs/Reference.rst
Log Message:
-----------
[Github][Docs] Add CI Best Practices Docs (#129462)
This is something that Tom and I have discussed briefly for a while now,
a doc that lists out all of the best practices we want to adhere to
surrounding CI things along with their associated motivations/any other
relevant info. This patch adds that doc along with three best practices
surrounding Github Workflows that we try and adhere to (although more
work needs to be done to get 100% adherance).
Commit: ee09df8e73d8575542283d8cfe351764af290f96
https://github.com/llvm/llvm-project/commit/ee09df8e73d8575542283d8cfe351764af290f96
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M mlir/include/mlir/Dialect/Affine/Passes.td
M mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp
M mlir/test/Dialect/Affine/affine-data-copy.mlir
M mlir/test/Dialect/Affine/dma-generate.mlir
Log Message:
-----------
[MLIR][Affine] Switch default option for affine data copy generate pass (#129445)
The more common use of this pass for testing and other purposes is the
pointwise copy generation as opposed to DMA generation. Switch the
default pass option to pointwise copy generation for easier testing. NFC
otherwise.
Users who were relying on `generate-dma` to be on by default will have
to pass it explicitly: `-affine-data-copy-generate='generate-dma=1'`.
Commit: b44fbdee00bbead186baf4109ea7ca440bd8a0b3
https://github.com/llvm/llvm-project/commit/b44fbdee00bbead186baf4109ea7ca440bd8a0b3
Author: Petr Penzin <penzin.dev at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
M llvm/test/CodeGen/RISCV/features-info.ll
Log Message:
-----------
[RISCV] Tune flag for fast vrgather.vv (#124664)
Add tune knob for N*Log2(N) vrgather.vv cost.
Commit: a59b17c8adde34e26b0f101fc2942637b945e1e5
https://github.com/llvm/llvm-project/commit/a59b17c8adde34e26b0f101fc2942637b945e1e5
Author: Derek Schuff <dschuff at chromium.org>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M lld/test/wasm/emit-relocs.s
M lld/wasm/InputChunks.cpp
M lld/wasm/InputChunks.h
M lld/wasm/OutputSections.cpp
M lld/wasm/OutputSections.h
M lld/wasm/Symbols.cpp
Log Message:
-----------
[lld][WebAssembly] Do not emit relocs against dead symbols (#129346)
When emitting relocs with linked output (i.e. --emit-relocs)
skip relocs against dead symbols (which do not appear in the output)
and do not emit them.
Commit: cf05b6e25ac8dcbf6e0ea1524d86bc6d190bf8c0
https://github.com/llvm/llvm-project/commit/cf05b6e25ac8dcbf6e0ea1524d86bc6d190bf8c0
Author: JaydeepChauhan14 <chauhan.jaydeep.ashwinbhai at intel.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrFragments.td
M llvm/lib/Target/X86/X86InstrOperands.td
A llvm/test/CodeGen/X86/lea-16bit.ll
A llvm/test/CodeGen/X86/lea-8bit.ll
M llvm/utils/TableGen/X86RecognizableInstr.cpp
Log Message:
-----------
[X86] Added support for 8 and 16bit LEA instructions (#122102)
Commit: 4bd34273210329047a7829f1ea4f54c171000c68
https://github.com/llvm/llvm-project/commit/4bd34273210329047a7829f1ea4f54c171000c68
Author: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M llvm/include/llvm/IR/IRBuilder.h
Log Message:
-----------
IRBuilder: Add FMFSource parameter to CreateMaxNum/CreateMinNum (#129173)
In https://github.com/llvm/llvm-project/pull/112852, we claimed that
llvm.minnum and llvm.maxnum should treat +0.0>-0.0, while libc doesn't
require fmin(3)/fmax(3) for it.
Let's add FMFSource parameter to CreateMaxNum and CreateMinNum, so that
they can be used by CodeGenFunction::EmitBuiltinExpr of Clang.
Commit: c1aebd495be0e468044f716a3a0ff98fccccb2be
https://github.com/llvm/llvm-project/commit/c1aebd495be0e468044f716a3a0ff98fccccb2be
Author: Victor Mustya <victor.mustya at intel.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/Headers/opencl-c.h
Log Message:
-----------
[Clang][OpenCL] Wrap image functions with the macro (#129177)
According to the OpenCL C spec, the image functions are optional.
For OpenCL C 1.2, the image functions are guarded by the
`__IMAGE_SUPPORT__` macro. For the OpenCL C 3.0 and later, the
`__opencl_c_images` macro is used.
Commit: 6041c745f32e8fd60ed24e29e7d919d8d1c87ca6
https://github.com/llvm/llvm-project/commit/6041c745f32e8fd60ed24e29e7d919d8d1c87ca6
Author: Augusto Noronha <anoronha at apple.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M lldb/include/lldb/Host/macosx/HostInfoMacOSX.h
M lldb/include/lldb/Utility/XcodeSDK.h
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Utility/XcodeSDK.cpp
M lldb/unittests/SymbolFile/DWARF/XcodeSDKModuleTests.cpp
M lldb/unittests/Utility/XcodeSDKTest.cpp
Log Message:
-----------
Revert "[lldb][HostInfoMacOSX] Try to use DW_AT_LLVM_sysroot instead of xcrun when looking up SDK" (#129621)
Reverts llvm/llvm-project#128712
```
******************** TEST 'lldb-unit :: SymbolFile/DWARF/./SymbolFileDWARFTests/10/14' FAILED ********************
Script(shard):
--
GTEST_OUTPUT=json:/Users/ec2-user/jenkins/workspace/llvm.org/as-lldb-cmake/lldb-build/tools/lldb/unittests/SymbolFile/DWARF/./SymbolFileDWARFTests-lldb-unit-1021-10-14.json GTEST_SHUFFLE=1 GTEST_TOTAL_SHARDS=14 GTEST_SHARD_INDEX=10 GTEST_RANDOM_SEED=62233 /Users/ec2-user/jenkins/workspace/llvm.org/as-lldb-cmake/lldb-build/tools/lldb/unittests/SymbolFile/DWARF/./SymbolFileDWARFTests
--
Script:
--
/Users/ec2-user/jenkins/workspace/llvm.org/as-lldb-cmake/lldb-build/tools/lldb/unittests/SymbolFile/DWARF/./SymbolFileDWARFTests --gtest_filter=SDKPathParsingTests/SDKPathParsingMultiparamTests.TestSDKPathFromDebugInfo/6
--
/Users/ec2-user/jenkins/workspace/llvm.org/as-lldb-cmake/llvm-project/lldb/unittests/SymbolFile/DWARF/XcodeSDKModuleTests.cpp:265: Failure
Expected equality of these values:
found_mismatch
Which is: true
expect_mismatch
Which is: false
/Users/ec2-user/jenkins/workspace/llvm.org/as-lldb-cmake/llvm-project/lldb/unittests/SymbolFile/DWARF/XcodeSDKModuleTests.cpp:265
Expected equality of these values:
found_mismatch
Which is: true
expect_mismatch
Which is: false
```
Commit: d654d37c86a4f0dc99c65cbef0624b5533ed724c
https://github.com/llvm/llvm-project/commit/d654d37c86a4f0dc99c65cbef0624b5533ed724c
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M lldb/test/API/tools/lldb-dap/breakpoint-events/TestDAP_breakpointEvents.py
M lldb/tools/lldb-dap/Handler/InitializeRequestHandler.cpp
Log Message:
-----------
[lldb-dap] Correctly report breakpoints as resolved on macOS (#129589)
On macOS, breakpoints are briefly unresolved between process launch and
when the dynamic loader has informed us about the loaded libraries. This
information was being forwarded by lldb-dap, but only partially. In the
event handler, we were listening for the `LocationsAdded` and
`LocationsRemoved` breakpoint events. For the scenario described above,
the latter would trigger and we'd send an event reporting the breakpoint
as unresolved. The problem is that when the breakpoint location is
resolved again, you receive a `LocationsResolved` event, not a
`LocationsAdded` event. As a result, the breakpoint would continue to
show up as unresolved in the DAP client.
I found a test that tried to test part of this behavior, but the test
was broken and disabled. I revived the test and added coverage for the
situation described above.
Fixes #112629
rdar://137968318
Commit: 5bf1f03d1fb4fd4c16029355d5814ebce61ed939
https://github.com/llvm/llvm-project/commit/5bf1f03d1fb4fd4c16029355d5814ebce61ed939
Author: A. Jiang <de34 at live.cn>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M libcxx/include/__vector/vector.h
M libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_range.pass.cpp
Log Message:
-----------
[libc++] Fix assignment in insertion into `vector` (#116001)
Changes:
- Avoid direct assignment in iterator-pair `insert` overload and
`insert_range`, except when the assignment is move assignment.
Commit: f44fb56f62aafff93cd337d8818ead0ad7794d35
https://github.com/llvm/llvm-project/commit/f44fb56f62aafff93cd337d8818ead0ad7794d35
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M flang-rt/cmake/modules/AddFlangRTOffload.cmake
Log Message:
-----------
[flang-rt] Set CUDA_SEPARABLE_COMPILATION for PTX library. (#129563)
`CUDA_SEPARABLE_COMPILATION` adds `-rdc=true`, which is needed
for the PTX library build.
Commit: f57756a6406f93b3f579ce4da2b8be3fe211952f
https://github.com/llvm/llvm-project/commit/f57756a6406f93b3f579ce4da2b8be3fe211952f
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M flang/include/flang/Common/erfc-scaled.h
Log Message:
-----------
[flang-rt] Use RT_API_ATTRS for ErfcScaled. (#129598)
As long as it is a host-only function, it cannot be referenced
by the flang-rt's ErfcScaled entry points. With the markup in place,
it is compiling properly by a CUDA compiler.
Commit: bf9bf291a3174a3c7b50ec37ddf5782767827c61
https://github.com/llvm/llvm-project/commit/bf9bf291a3174a3c7b50ec37ddf5782767827c61
Author: A. Jiang <de34 at live.cn>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M libcxx/include/__algorithm/stable_partition.h
M libcxx/include/algorithm
M libcxx/test/std/algorithms/alg.modifying.operations/alg.partitions/stable_partition.pass.cpp
M libcxx/test/std/algorithms/robust_against_proxy_iterators_lifetime_bugs.pass.cpp
M libcxx/test/std/algorithms/robust_re_difference_type.compile.pass.cpp
Log Message:
-----------
[libc++] Implement part of P2562R1: constexpr `std::stable_partition` (#128868)
Drive-by changes:
- Enables no-memory case for Clang.
- Enables `robust_re_difference_type.compile.pass.cpp` and
`robust_against_proxy_iterators_lifetime_bugs.pass.cpp` test coverage
for `std::stable_sort` in constant evaluation since C++26. The changes
were missing in the PR making `std::stable_sort` `constexpr`.
Commit: 3963d2148292145543cf83b13ff839a63995fdc2
https://github.com/llvm/llvm-project/commit/3963d2148292145543cf83b13ff839a63995fdc2
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/test/CodeGen/AMDGPU/machine-sink-cycle.mir
Log Message:
-----------
[MachineSink] Fix typo in loop sinking (#127133)
Failure to sink a candidate should not block us from attempting to sink
other candidates. There are mechanisms in place to handle the case where
the failed to be sunk instruction uses an instruction that gets sunk (we
do not delete the original instruction corresponding with the sunk
instruction if it still has uses).
Commit: f38ce27c13760d166fda41dbb0ad815f40e4e874
https://github.com/llvm/llvm-project/commit/f38ce27c13760d166fda41dbb0ad815f40e4e874
Author: Jie Fu <jiefu at tencent.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Log Message:
-----------
[X86] Fix an unused variable warning (NFC)
/llvm-project/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:3090:7:
error: unused variable 'IndexType' [-Werror,-Wunused-variable]
EVT IndexType = Index.getValueType();
^
1 error generated.
Commit: 415f89905fa04bdee2f0f5a8886706756699d06e
https://github.com/llvm/llvm-project/commit/415f89905fa04bdee2f0f5a8886706756699d06e
Author: Daniel Zabawa <daniel.zabawa at intel.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc.ll
Log Message:
-----------
[X86] Remove single-use checks when combining xor and vfmulc/vcfmulc. (#128910)
The current implementation to combine xor patterns for conjugation with
complex multiplies will not perform the transformation when either the
conjugate xor result or other multiplicand have other uses. This change
eliminates both single-use checks.
The transformation will eliminate the xor dependence and hence should be
profitable even if the conjugate is used elsewhere - and more profitable
if the xor is used in multiple fmulc/fcmulc instructions, eventually
going dead.
The check of the other multiplicand isn't required for correctness and
has no apparent performance implications.
Commit: 0ed2945a596991b75e4ca090fe04240abba6012b
https://github.com/llvm/llvm-project/commit/0ed2945a596991b75e4ca090fe04240abba6012b
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/Format/Format.cpp
M clang/unittests/Format/SortIncludesTest.cpp
Log Message:
-----------
[clang-format] Don't sort includes for C# (#129369)
Fixes #106194
Commit: 136f2574ddfe81e73376ada0ea299b67170caf2c
https://github.com/llvm/llvm-project/commit/136f2574ddfe81e73376ada0ea299b67170caf2c
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/Format/Format.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Lex C++ only keywords as identifiers in C (#129426)
Fix #128847
Commit: 2ca085505996ca16cc79090dbc66d06ac46ed262
https://github.com/llvm/llvm-project/commit/2ca085505996ca16cc79090dbc66d06ac46ed262
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Fix a bug in wrapping function return type (#129374)
Fixes #113766
Commit: 956e56fa6d3d62e1ef1a27bdc9f6be3c0544b9c7
https://github.com/llvm/llvm-project/commit/956e56fa6d3d62e1ef1a27bdc9f6be3c0544b9c7
Author: TatWai Chong <tatwai.chong at arm.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Dialect/Tosa/level_check.mlir
Log Message:
-----------
[mlir][tosa] Add several level checks (#129580) (#129613)
Add the following types of level check to consolidate the level validity
- Complete rank level checks for operations.
- Add MAX_LOG2_SIZE level check: The maximum value is 63 when the
level is set to "none" and 31 when the level is set to "8K".
- Add MAX_TENSOR_LIST_SIZE level check : The maximum value is 256
when the level is set to "none" and 64 when the level is set to "8K".
- TOSA 1.0 spec does not allow operations with dynamic shapes, so an
error should be raised instead.
Co-authored-by: Tai Ly <tai.ly at arm.com>
Commit: ce1a18e2c714f39fe72cd46aa04faed29ad23cb6
https://github.com/llvm/llvm-project/commit/ce1a18e2c714f39fe72cd46aa04faed29ad23cb6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/tools/c-index-test/c-index-test.c
Log Message:
-----------
clang-tools: Fix sprintf is deprecated warnings (#120517)
Commit: 8476a5d480304bf7bd934c660a159e1c6906a69d
https://github.com/llvm/llvm-project/commit/8476a5d480304bf7bd934c660a159e1c6906a69d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/lib/CodeGen/SplitKit.h
A llvm/test/CodeGen/AMDGPU/splitkit-do-not-undo-subclass-split-with-remat.mir
M llvm/test/CodeGen/X86/eq-or-eq-range-of-2.ll
M llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll
M llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll
M llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
Log Message:
-----------
SplitKit: Fix rematerialization undoing subclass based split (#122110)
This fixes an allocation failure in the new test.
In cases where getLargestLegalSuperClass can inflate the register class,
rematerialization could effectively undo a split which was done to
inflate
the register class, if the defining instruction can only write a
subclass
and the use can read the superclass.
Some of the x86 tests changes look like improvements, but some are
likely regressions.
I'm not entirely sure this is the correct place to fix this. It also
seems more complicated than necessary, but the decision to change
the register class is far removed from the point where the decision
to split the virtual register is made. I'm also also not sure if this
should be considering the register classes of all the use indexes
in getUseSlots, rather than just checking if this use index instruction
reads the register.
Commit: 12b38c3e39512344b9c951406c5023b8a5549182
https://github.com/llvm/llvm-project/commit/12b38c3e39512344b9c951406c5023b8a5549182
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
Log Message:
-----------
TableGen: Fix comment typo
Commit: 4670f0d8275a7eacfba46a17d88d3e2d947f5a61
https://github.com/llvm/llvm-project/commit/4670f0d8275a7eacfba46a17d88d3e2d947f5a61
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
Log Message:
-----------
MachineVerifier: Print name of failing subregister index (#129491)
I'm not sure of a good example to test the "does not fully support"
case.
Commit: 50ff49ebbcdc88301070e94b04cb158d040db276
https://github.com/llvm/llvm-project/commit/50ff49ebbcdc88301070e94b04cb158d040db276
Author: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
Log Message:
-----------
Clang: ExprConstant use maxnum/minnum for fmax/fmin (#129630)
In APFloat, we have defined maxnum and minnum, so let's use them
directly here.
In `maxnum`/`minnum` of APFloat, we process sNaN, signed-zero as
strictly as possible.
Commit: 3aab3fe56fbd60b49a47ae0f90d96de2cd09fc18
https://github.com/llvm/llvm-project/commit/3aab3fe56fbd60b49a47ae0f90d96de2cd09fc18
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/include/llvm/IR/Analysis.h
M llvm/lib/CodeGen/MachineScheduler.cpp
Log Message:
-----------
[NPM][NFC] Chain PreservedAnalyses methods (#129505)
Commit: 82d111e8202328d3a04d923cdae19ad29bc79dbc
https://github.com/llvm/llvm-project/commit/82d111e8202328d3a04d923cdae19ad29bc79dbc
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
Log Message:
-----------
[clang][bytecode][NFC] Minor cleanups (#129553)
Pull local variables in to the closest scope, remove some unnecessary
calls to getLocation() and remove an outdated comment.
Commit: 6c87ec4f4d083a85ebcfbbda166ad4ba41d5da8d
https://github.com/llvm/llvm-project/commit/6c87ec4f4d083a85ebcfbbda166ad4ba41d5da8d
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIModeRegister.cpp
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
M llvm/test/CodeGen/AMDGPU/mode-register.mir
Log Message:
-----------
[AMDGPU][NPM] Port SIModeRegister to NPM (#129014)
Commit: af4ec59f8d2ec127425ed45c0ff67c51679f99ad
https://github.com/llvm/llvm-project/commit/af4ec59f8d2ec127425ed45c0ff67c51679f99ad
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
A llvm/include/llvm/CodeGen/ExpandPostRAPseudos.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/AArch64/seqpaircopy.mir
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
M llvm/test/CodeGen/SystemZ/copy-phys-reg-gr64-to-fp64.mir
Log Message:
-----------
[CodeGen][NPM] Port ExpandPostRAPseudos to NPM (#129509)
Commit: e9fe95acf3b9ead924a6f059c8ca8a8aabc55575
https://github.com/llvm/llvm-project/commit/e9fe95acf3b9ead924a6f059c8ca8a8aabc55575
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
Log Message:
-----------
[clang][bytecode][NFC] Use maxnum/minnum for fmax/fmin (#129643)
Equivalent of https://github.com/llvm/llvm-project/pull/129630 for the
bytecode interpreter.
Commit: 41473162fd886d7db548fb288cf3620570f73c17
https://github.com/llvm/llvm-project/commit/41473162fd886d7db548fb288cf3620570f73c17
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/include/llvm/CodeGen/RegAllocGreedyPass.h
Log Message:
-----------
[CodeGen][NPM]RAGreedy: Put up include guard in the header (#129510)
Commit: 4fb31e44017bd9ad914fc4c814fbaa60cc18d5b4
https://github.com/llvm/llvm-project/commit/4fb31e44017bd9ad914fc4c814fbaa60cc18d5b4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Log Message:
-----------
AMDGPU: Use const reference for DebugLoc
Commit: b3d5056c79b5496fc8751630ddd0ac0071cab0af
https://github.com/llvm/llvm-project/commit/b3d5056c79b5496fc8751630ddd0ac0071cab0af
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/acc-ldst.ll
A llvm/test/CodeGen/AMDGPU/coalesces-better.mir
A llvm/test/CodeGen/AMDGPU/coalesces-worse.mir
M llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
M llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll
M llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
Log Message:
-----------
AMDGPU: Try to perform copy to agpr from reg_sequence at the copy (#129463)
SIFoldOperands is frustratingly written in a def-folds-into-use
iteration pattern, with a few random cases starting at the uses.
We were handling this case by looking at the reg_sequence, and finding
the copy. This did not work for the most basic pattern of materializing
a vector constant that started in SGPRs. It just happens there is an
optimization bug in SelectionDAG that produced the expected pattern.
Perform an additional attempt at the fold rooted at the copy. This
mostly shows test improvements. There were some tricky updates to
perform. remaining-virtual-register-operands.ll managed to stop failing
the allocator, so needed to be tricked into failing again. I also do
not understand what schedule-xdl-resource.ll is trying to do for the test
so this changes it to some random output that exists in the debug output.
Commit: 39bf765bb671fa7df3fe6c164cc9532fcb8653bd
https://github.com/llvm/llvm-project/commit/39bf765bb671fa7df3fe6c164cc9532fcb8653bd
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nondeterminism.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mmra.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
Log Message:
-----------
DAG: Use phi to create vregs instead of the constant input (#129464)
For most targets, the register class comes from the type so this
makes no difference. For AMDGPU, the selected register class depends
on the divergence of the value. For a constant phi input, this will
always be false. The heuristic for whether to treat the value as
a scalar or vector constant based on the uses would then incorrectly
think this is a scalar use, when really the phi is a copy from S to V.
This avoids an intermediate s_mov_b32 plus a copy in some cases. These
would often, but not always, fold out in mi passes.
This only adjusts the constant input case. It may make sense to do
this for the non-constant case as well.
Commit: 9084d2a0a11d8e12ac02f8870c418073985c2e59
https://github.com/llvm/llvm-project/commit/9084d2a0a11d8e12ac02f8870c418073985c2e59
Author: Dmitri Gribenko <gribozavr at gmail.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M libc/src/stdlib/qsort_pivot.h
Log Message:
-----------
[libc] Add a missing include
This is a fixup for
https://github.com/llvm/llvm-project/commit/da6d5fa79a558b66c281bed3f5ce848a69a65208.
Commit: 2127af80fa46709a563ad7ecc400209f1640f96e
https://github.com/llvm/llvm-project/commit/2127af80fa46709a563ad7ecc400209f1640f96e
Author: Alexander Shaposhnikov <ashaposhnikov at google.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M compiler-rt/test/ubsan/TestCases/Float/cast-overflow.cpp
Log Message:
-----------
[compiler-rt][ubsa] Reformat cast-overflow test. NFC (#129662)
Reformat cast-overflow test. NFC
Commit: a5bbfcf0c9dd48e13951fdb35362e2e3d545dbad
https://github.com/llvm/llvm-project/commit/a5bbfcf0c9dd48e13951fdb35362e2e3d545dbad
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
Log Message:
-----------
[GlobalISel] Avoid repeated hash lookups (NFC) (#129653)
Commit: c61c88862805905dfa8a2c2f8c9f8ef7e1874720
https://github.com/llvm/llvm-project/commit/c61c88862805905dfa8a2c2f8c9f8ef7e1874720
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/tools/llvm-mca/CodeRegion.cpp
Log Message:
-----------
[llvm-mca] Avoid repeated hash lookups (NFC) (#129656)
Commit: a619a2e53a9ba09ba18a047b8389bf4dd1912b72
https://github.com/llvm/llvm-project/commit/a619a2e53a9ba09ba18a047b8389bf4dd1912b72
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
A clang/test/CodeGen/arm-neon-endianness.c
M clang/utils/TableGen/NeonEmitter.cpp
Log Message:
-----------
[ARM] Fix lane ordering for AdvSIMD intrinsics on big-endian targets (#127068)
In arm-neon.h, we insert shufflevectors around each intrinsic when the
target is big-endian, to compensate for the difference between the
ABI-defined memory format of vectors (with the whole vector stored as
one big-endian access) and LLVM's target-independent expectations (with
the lowest-numbered lane in the lowest address). However, this code was
written for the AArch64 ABI, and the AArch32 ABI differs slightly: it
requires that vectors are stored in memory as-if stored with VSTM, which
does a series of 64-bit accesses, instead of the AArch64 VSTR, which
does a single 128-bit access. This means that for AArch32 we need to
reverse the lanes in each 64-bit chunk of the vector, instead of in the
whole vector.
Since there are only a small number of different shufflevector orderings
needed, I've split them out into macros, so that this doesn't need
separate conditions in each intrinsic definition.
Commit: d6942d54f677000cf713d2b0eba57b641452beb4
https://github.com/llvm/llvm-project/commit/d6942d54f677000cf713d2b0eba57b641452beb4
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/VTableBuilder.h
M clang/include/clang/Basic/ABI.h
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/MicrosoftMangle.cpp
M clang/lib/AST/VTableBuilder.cpp
M clang/lib/CodeGen/CGCXX.cpp
M clang/lib/CodeGen/CGCXXABI.cpp
M clang/lib/CodeGen/CGCXXABI.h
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CGVTables.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/CodeGen/MicrosoftCXXABI.cpp
M clang/test/CodeGenCXX/debug-info-windows-dtor.cpp
M clang/test/CodeGenCXX/dllexport.cpp
M clang/test/CodeGenCXX/microsoft-abi-extern-template.cpp
M clang/test/CodeGenCXX/microsoft-abi-structors.cpp
M clang/test/CodeGenCXX/microsoft-abi-thunks.cpp
M clang/test/CodeGenCXX/microsoft-abi-vftables.cpp
M clang/test/CodeGenCXX/microsoft-abi-virtual-inheritance.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-multiple-nonvirtual-inheritance-vdtors.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-return-thunks.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-single-inheritance.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-virtual-inheritance-vtordisps.cpp
M clang/test/CodeGenCXX/microsoft-abi-vtables-virtual-inheritance.cpp
M clang/test/CodeGenCXX/microsoft-no-rtti-data.cpp
A clang/test/CodeGenCXX/microsoft-vector-deleting-dtors.cpp
M clang/test/CodeGenCXX/vtable-consteval.cpp
M clang/test/Modules/vtable-windows.cppm
M clang/test/Profile/cxx-abc-deleting-dtor.cpp
Log Message:
-----------
[MS][clang] Add support for vector deleting destructors (#126240)
Whereas it is UB in terms of the standard to delete an array of objects
via pointer whose static type doesn't match its dynamic type, MSVC
supports an extension allowing to do it.
Aside from array deletion not working correctly in the mentioned case,
currently not having this extension implemented causes clang to generate
code that is not compatible with the code generated by MSVC, because
clang always puts scalar deleting destructor to the vftable. This PR
aims to resolve these problems.
Fixes https://github.com/llvm/llvm-project/issues/19772
Commit: aa37a698d4066058d03016ea467230bd039c1eb1
https://github.com/llvm/llvm-project/commit/aa37a698d4066058d03016ea467230bd039c1eb1
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
Log Message:
-----------
[LoopInterchange] Move some processes to another function (NFC) (#129514)
Some post-processing involved in exchanging a pair of loops has been
done separately from `processLoop`, which is a main function that does
the transformation. It's better to consolidate these processes into the
same function. This patch is a preparation of #127474.
Commit: 15770a1e9d0983ee59a8850f2ddd7b57e46dcc5a
https://github.com/llvm/llvm-project/commit/15770a1e9d0983ee59a8850f2ddd7b57e46dcc5a
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Remove dead recipes in entry when merging regions. (NFC)
Also remove recipes in the entry of the region that will be removed.
This makes sure we don't leave any dead users around. NFC at the moment,
but avoids causing issues in the future.
Commit: 23a30e68888e764b2f4d32e51d415b50fa5f5cac
https://github.com/llvm/llvm-project/commit/23a30e68888e764b2f4d32e51d415b50fa5f5cac
Author: Alexander Shaposhnikov <ashaposhnikov at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M compiler-rt/lib/ubsan/ubsan_value.cpp
M compiler-rt/test/ubsan/TestCases/Float/cast-overflow.cpp
Log Message:
-----------
[compiler-rt][ubsan] Add support for f16 (#129624)
LLVM supports long double <-> f16 conversions so we can remove the old FIXME.
Commit: 80bdfcd411cd8197b0a8b6139b89a87d3a4528fa
https://github.com/llvm/llvm-project/commit/80bdfcd411cd8197b0a8b6139b89a87d3a4528fa
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_estimated_tc.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_memcheck_cost.ll
Log Message:
-----------
[LoopUtils] Don't wrap in getLoopEstimatedTripCount (#129080)
getLoopEstimatedTripCount returns the trip count based on profiling
data, and its documentation says that it could return 0 when the trip
count is zero, but this is not the case: a valid trip count can never be
zero, and it returns 0 when the unsigned ExitCount is incremented by 1
and wraps. Some callers are careful about checking for this zero value
in an std::optional, but it makes for an API with footguns, as a
std::optional return value indicates that a non-nullopt value would be a
valid trip count. Fix this by explicitly returning std::nullopt when the
return value would wrap, and strip additional checks in callers. This
also fixes a minor bug in LoopVectorize.
Commit: 8266cd9f84b5a7d334ade7ff41393458b3789047
https://github.com/llvm/llvm-project/commit/8266cd9f84b5a7d334ade7ff41393458b3789047
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang-tools-extra/clangd/TidyProvider.cpp
M clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp
Log Message:
-----------
[clangd] Disable cppcoreguidelines-macro-to-enum clang-tidy checker (#129478)
Clangd does not support its checker because the checker relies on having
seen preprocessor conditionals that occur in the preamble, and clangd
does not currently replay those.
This checker was already disabled under its main name,
modernize-macro-to-enum (https://github.com/clangd/clangd/issues/1464).
This commit disables it under the alternative name
cppcoreguidelines-macro-to-enum as well.
Fixes https://github.com/llvm/llvm-project/issues/127965
Commit: 47fb9c4bb9b057ab45c5228937a2c1fbf51c4f72
https://github.com/llvm/llvm-project/commit/47fb9c4bb9b057ab45c5228937a2c1fbf51c4f72
Author: Luke Lau <luke at igalia.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanHCFGBuilder.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Add Name argument to VPWidenPHIRecipe. NFC (#129527)
This allows a different IR name for the generated phi to be used. This
is split off from #118638 and helps remove some of the diffs in it.
Commit: 03505a004ff6909c46d6b8c498a9ffccd47d88a0
https://github.com/llvm/llvm-project/commit/03505a004ff6909c46d6b8c498a9ffccd47d88a0
Author: Jim Lin <jim at andestech.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll
Log Message:
-----------
[RISCV] Enable scalable loop vectorization for fmax/fmin reductions with f16/bf16 type for zvfhmin/zvfbfmin (#129629)
This PR enable scalable loop vectorization for fmax and fmin reductions
with f16/bf16 type when only zvfhmin/zvfbfmin are enabled.
After https://github.com/llvm/llvm-project/pull/128800, we can promote
the fmax/fmin reductions with f16/bf16 type to f32 reductions for
zvfhmin/zvfbfmin.
Commit: 0eaca0412501da82d7f23811003f64624e17cba6
https://github.com/llvm/llvm-project/commit/0eaca0412501da82d7f23811003f64624e17cba6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Log Message:
-----------
AMDGPU: Remove repeated define in base info header
The identical define is repeated on the previous line.
Commit: b7f31044f34036d277f5c6e21ef3a126b5972508
https://github.com/llvm/llvm-project/commit/b7f31044f34036d277f5c6e21ef3a126b5972508
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/test/Transforms/GVN/opt-remarks.ll
Log Message:
-----------
[GVN][NFC] Remove unnecessary assembly output from test (#129670)
This test doesn't check any output from opt, so it can be safely
`disable-output` and thus less redirections.
Commit: a32d5438ac50ef509af9e688f9cd93f1e98d929d
https://github.com/llvm/llvm-project/commit/a32d5438ac50ef509af9e688f9cd93f1e98d929d
Author: Alexander Shaposhnikov <ashaposhnikov at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M compiler-rt/lib/ubsan/ubsan_value.cpp
M compiler-rt/test/ubsan/TestCases/Float/cast-overflow.cpp
Log Message:
-----------
Revert "[compiler-rt][ubsan] Add support for f16 (#129624)"
This reverts commit 23a30e68888e764b2f4d32e51d415b50fa5f5cac.
The commit has broken some build bots.
Commit: 2bef21f24ba932a757a644470358c340f4bcd113
https://github.com/llvm/llvm-project/commit/2bef21f24ba932a757a644470358c340f4bcd113
Author: James Chesterman <James.Chesterman at arm.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
Log Message:
-----------
[DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (#127083)
Add generic DAG combine for ISD::PARTIAL_REDUCE_U/SMLA nodes. Transforms
the DAG from:
PARTIAL_REDUCE_MLA(Acc, MUL(EXT(MulOpLHS), EXT(MulOpRHS)), Splat(1)) to
PARTIAL_REDUCE_MLA(Acc, MulOpLHS, MulOpRHS).
Commit: 7c8b1275bc87f6b5983788a6e603504725b490c9
https://github.com/llvm/llvm-project/commit/7c8b1275bc87f6b5983788a6e603504725b490c9
Author: Nathan Gauër <brioche at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/SPIRV.h
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
A llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
A llvm/test/CodeGen/SPIRV/pointers/array-skips-gep.ll
A llvm/test/CodeGen/SPIRV/pointers/getelementptr-downcast-vector.ll
Log Message:
-----------
[SPIR-V] Add pass to remove spv_ptrcast intrinsics (#128896)
OpenCL is allowed to cast pointers, meaning they can resolve some type
mismatches this way. In logical SPIR-V, those are restricted. This new
pass legalizes such pointer cast when targeting logical SPIR-V.
For now, this pass supports 3 cases we witnessed:
- loading a vec3 from a vec4*.
- loading a scalar from a vec*.
- loading the 1st element of an array.
---------
Co-authored-by: Steven Perron <stevenperron at google.com>
Commit: 7a06681398a33d53ba6d661777be8b4c1d19acb7
https://github.com/llvm/llvm-project/commit/7a06681398a33d53ba6d661777be8b4c1d19acb7
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
Log Message:
-----------
Revert "[DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (#127083)"
This reverts commit 2bef21f24ba932a757a644470358c340f4bcd113.
Multiple builtbot failures have been reported:
https://github.com/llvm/llvm-project/pull/127083
Commit: ef94d8a0f2d885d1753cd39c1ea76fe21a69d93b
https://github.com/llvm/llvm-project/commit/ef94d8a0f2d885d1753cd39c1ea76fe21a69d93b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
Log Message:
-----------
[CodeGen] Avoid repeated hash lookups (NFC) (#129652)
Commit: 9372d1d72ab287d5121ca1961dd416cf51224e62
https://github.com/llvm/llvm-project/commit/9372d1d72ab287d5121ca1961dd416cf51224e62
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
Log Message:
-----------
[TableGen] Avoid repeated hash lookups (NFC) (#129655)
Commit: 65330e20b189c38ddbb38eb63b15f93262385e73
https://github.com/llvm/llvm-project/commit/65330e20b189c38ddbb38eb63b15f93262385e73
Author: Kazu Hirata <kazu at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/tools/llvm-readobj/COFFDumper.cpp
Log Message:
-----------
[llvm-readobj] Avoid repeated hash lookups (NFC) (#129657)
Commit: f319a6546613d65661e1ad1ef1a2a648cefee84b
https://github.com/llvm/llvm-project/commit/f319a6546613d65661e1ad1ef1a2a648cefee84b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
Log Message:
-----------
AMDGPU: Fix broken broken negative test for gfx950 assembler (#129667)
Fix's not rejecting global_load_lds_dwordx3 and x4 on other targets.
The encoded versions of instructions should not touch SubtargetPredicate,
and only AssemblerPredicate.
Commit: 45901ccfcc528849a7079319f1b8ee26939202f0
https://github.com/llvm/llvm-project/commit/45901ccfcc528849a7079319f1b8ee26939202f0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/FLATInstructions.td
Log Message:
-----------
AMDGPU: Remove some overrides of SubtargetPredicate on real instructions (#129668)
AssemblerPredicate is the hack to use for cases where the encoding
change doesn't nicely line up with the subtarget predicate.
Commit: e187fc0ff780c2f6a8e495f9a5d70fbac2341b3b
https://github.com/llvm/llvm-project/commit/e187fc0ff780c2f6a8e495f9a5d70fbac2341b3b
Author: Adam Siemieniuk <adam.siemieniuk at intel.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M mlir/docs/Dialects/Linalg/_index.md
M mlir/include/mlir/Dialect/Linalg/IR/LinalgDoc.td
Log Message:
-----------
[mlir][linalg] Fix linalg.pack/unpack docs (#129559)
Adds missing relayout ops to Linalg docs tablegen.
Follow-up to #127729
Commit: d0eeeab5575d88498149a66096fda2815c132e3a
https://github.com/llvm/llvm-project/commit/d0eeeab5575d88498149a66096fda2815c132e3a
Author: Sushant Gokhale <sgokhale at nvidia.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
Log Message:
-----------
[NFC] test for usdot with multiple zext users (#129650)
Currently, usdot is not being generated in loop when zext has multiple. Subsequent patch will improve
this.
Commit: 0fcbf148df9c6d4f1a12eed356697cda665852e5
https://github.com/llvm/llvm-project/commit/0fcbf148df9c6d4f1a12eed356697cda665852e5
Author: AnastasiyaChernikova <anastasiya.chernikova at syntacore.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
A llvm/test/tools/llvm-exegesis/RISCV/latency-by-load.s
M llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp
Log Message:
-----------
[Exegesis] Implemented strategy for load operation (#113458)
This fix helps to map operand memory to destination registers. If
instruction is load, we can self-alias it in case when instruction
overrides whole address register. For that we use provided scratch
memory.
Commit: e0eb4edad66b3ea3c621c8c9f3298f2d64697bd7
https://github.com/llvm/llvm-project/commit/e0eb4edad66b3ea3c621c8c9f3298f2d64697bd7
Author: Vikram Hegde <115221833+vikramRH at users.noreply.github.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
A llvm/include/llvm/CodeGen/FixupStatepointCallerSaved.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/X86/statepoint-fixup-call.mir
M llvm/test/CodeGen/X86/statepoint-fixup-copy-prop-neg.mir
M llvm/test/CodeGen/X86/statepoint-fixup-copy-prop.mir
M llvm/test/CodeGen/X86/statepoint-fixup-invoke.mir
M llvm/test/CodeGen/X86/statepoint-fixup-shared-ehpad.mir
M llvm/test/CodeGen/X86/statepoint-fixup-undef-def.mir
M llvm/test/CodeGen/X86/statepoint-fixup-undef.mir
Log Message:
-----------
[CodeGen][NewPM] Port "FixupStatepointCallerSaved" pass to NPM (#129541)
Commit: 77a8770d4976e086f36004a6b8bf09e76d981451
https://github.com/llvm/llvm-project/commit/77a8770d4976e086f36004a6b8bf09e76d981451
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M lldb/include/lldb/Host/macosx/HostInfoMacOSX.h
M lldb/include/lldb/Utility/XcodeSDK.h
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Utility/XcodeSDK.cpp
M lldb/unittests/SymbolFile/DWARF/XcodeSDKModuleTests.cpp
M lldb/unittests/Utility/XcodeSDKTest.cpp
Log Message:
-----------
Reland "[lldb][HostInfoMacOSX] Try to use DW_AT_LLVM_sysroot instead of xcrun when looking up SDK" (#129621)"
This reverts commit 6041c745f32e8fd60ed24e29e7d919d8d1c87ca6.
Relands the original patch with the test-case data fixed. Weirldy the PR CI
didn't seem to run the unit-tests? In any case, the problem was an
incorrect expectation in the test-case data. Since we have both public
and internal SDK in that test-case, we should `expect_mismatch` to be
`true`.
Commit: e27b8b2eda767eb59d3d605d288e733b154a48c5
https://github.com/llvm/llvm-project/commit/e27b8b2eda767eb59d3d605d288e733b154a48c5
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M flang/lib/Optimizer/Dialect/FIRType.cpp
A flang/test/Integration/debug-cyclic-derived-type-4.f90
Log Message:
-----------
[flang][debug] Improve handling of cyclic derived types with classes. (#129588)
While checking if a type should be cached or not, we use
`getDerivedType` to peel outer layers and get to the base type. This
function did not peel the `fir.class` which caused the algorithm to
fail.
Fixes #128606.
Commit: 680391f07a45272bb9bfd385cf4c6846b8be32dd
https://github.com/llvm/llvm-project/commit/680391f07a45272bb9bfd385cf4c6846b8be32dd
Author: Discookie <viktor.cseh at ericsson.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/Analysis/FlowSensitive/Transfer.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
Log Message:
-----------
[clang][dataflow] Fix unsupported types always being equal (#129502)
Previously when the framework encountered unsupported values (such as
enum classes), they were always treated as equal when comparing with
`==`, regardless of their actual values being different.
Now the two sides are only equal if there's a Value assigned to them.
Added a Value assignment for `nullptr`, to handle the special case of
`nullptr == nullptr`.
Commit: c7dbf20e66606e7e26a28ad567ff75f3a493d3bd
https://github.com/llvm/llvm-project/commit/c7dbf20e66606e7e26a28ad567ff75f3a493d3bd
Author: Da-Viper <57949090+Da-Viper at users.noreply.github.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M lldb/test/API/tools/lldb-dap/variables/children/TestDAP_variables_children.py
Log Message:
-----------
[lldb-dap] Test: disable children return test for all arm architectures (#129409)
amd64 and aarch64 are treated differently
Follows up #106907
Commit: e3c8e17b073bf38e900014ed47230882c407dab8
https://github.com/llvm/llvm-project/commit/e3c8e17b073bf38e900014ed47230882c407dab8
Author: James Chesterman <james.chesterman at arm.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
Log Message:
-----------
Reland "[DAGCombiner] Add generic DAG combine for ISD::PARTIAL_REDUCE_MLA (#127083)"
This relands commit 7a06681398a33d53ba6d661777be8b4c1d19acb7.
Commit: ec54ec65e5172b624f34a801012fe471ccf5d261
https://github.com/llvm/llvm-project/commit/ec54ec65e5172b624f34a801012fe471ccf5d261
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M mlir/include/mlir/Analysis/FlatLinearValueConstraints.h
M mlir/include/mlir/Analysis/Presburger/IntegerRelation.h
M mlir/include/mlir/Dialect/Affine/Analysis/Utils.h
M mlir/lib/Analysis/FlatLinearValueConstraints.cpp
M mlir/lib/Analysis/Presburger/IntegerRelation.cpp
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/test/Dialect/Affine/dma-generate.mlir
M mlir/test/Dialect/Affine/loop-fusion-3.mlir
M mlir/test/Dialect/Affine/loop-fusion.mlir
Log Message:
-----------
[MLIR][Affine] Improve memref region bounding size and shape computation (#129009)
Improve memref region utility (`getConstantBoundingSizeAndShape`) to get
its constant bounding size and shape using affine expressions/maps by
also considering local variables in the system. Leads to significantly
precise and tighter bounding size and shape in the presence of div/mod
expressions (as evident from the test cases). The approach is now more
robust, proper, and complete. For affine fusion, this leads to private
memrefs of accurate size in several cases. This also impacts other
affine analysis-based passes like data copy generation that use memref
regions.
With contributions from `Vinayaka Bandishti <vinayaka at polymagelabs.com>`
on `getConstantBoundingSizeAndShape` and getConstantBoundOnDimSize`.
Fixes: https://github.com/llvm/llvm-project/issues/46317
Co-authored-by: Vinayaka Bandishti <vinayaka at polymagelabs.com>
Commit: 1e1781bca92c2c6ee05867702b26e88fe3227307
https://github.com/llvm/llvm-project/commit/1e1781bca92c2c6ee05867702b26e88fe3227307
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/sve-fcvt.ll
M llvm/test/CodeGen/AArch64/sve-split-fcvt.ll
Log Message:
-----------
[LLVM][SVE] Improve code generation for i1 based int_to_fp operations. (#129229)
Rather than extending the predicate we can use it directly to select
between the two possible results.
Commit: c711c65e57fe5e09b8321a675075dac9dbd12f82
https://github.com/llvm/llvm-project/commit/c711c65e57fe5e09b8321a675075dac9dbd12f82
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll
Log Message:
-----------
[X86] combineINSERT_SUBVECTOR - attempt to constant fold from constant pool loads (if we're not widening). (#129682)
Commit: da4cbeca6c5e147e7a3e19f1020befa8b119985e
https://github.com/llvm/llvm-project/commit/da4cbeca6c5e147e7a3e19f1020befa8b119985e
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/CodeGen/AArch64/sve-fcvt.ll
Log Message:
-----------
[LLVM][SVE] Implement isel for fptoi half/float/double to i1. (#129269)
Also adds an assert that SVE support for strict_fp fp<->int operations
is missing.
The added costs are to maintain the existing values expected by
Analysis/CostModel/AArch64/sve-cast.ll.
Commit: 25479a3c9c55af0f1651bf43b0ad5ec7d572ff34
https://github.com/llvm/llvm-project/commit/25479a3c9c55af0f1651bf43b0ad5ec7d572ff34
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/test/CodeGen/X86/setcc-lowering.ll
Log Message:
-----------
[X86] setcc-lowering.ll - regenerate VPTERNLOG comment
Commit: 06fc7d68ff816090ea8654a5a0240a4444a8eb6f
https://github.com/llvm/llvm-project/commit/06fc7d68ff816090ea8654a5a0240a4444a8eb6f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Descriptor.cpp
M clang/lib/AST/ByteCode/Descriptor.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Program.cpp
M clang/test/AST/ByteCode/records.cpp
Log Message:
-----------
[clang][bytecode] Don't error out on incomplete declarations (#129685)
Later operations on these are invalid, but the declaration is fine, if
extern.
Commit: 323112a38de04e4e7b8b7d8406575816f38507ac
https://github.com/llvm/llvm-project/commit/323112a38de04e4e7b8b7d8406575816f38507ac
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/sve-vector-splat.ll
Log Message:
-----------
[LLVM][SVE] Add isel for bfloat based constant splats. (#129550)
There are no dedicated bfloat MOV instructions but we can use the half
variants when the encoding allows (e.g. f16(1.875) == bf16(1.0)).
Commit: 607485f81c8bbfcf91ecb5a71a6323fb2bc367d9
https://github.com/llvm/llvm-project/commit/607485f81c8bbfcf91ecb5a71a6323fb2bc367d9
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Log Message:
-----------
[LLVM][SVE] Lower bfloat extends the same as other types. (#129544)
Commit: d9fb3cef5de1d1cd1261ae1753a578df1b9817de
https://github.com/llvm/llvm-project/commit/d9fb3cef5de1d1cd1261ae1753a578df1b9817de
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
R llvm/test/CodeGen/AMDGPU/coalesces-better.mir
R llvm/test/CodeGen/AMDGPU/coalesces-worse.mir
Log Message:
-----------
AMDGPU: Remove accidentally committed tests
Commit: 43ec9e18938930546e63db41ecda26d3de30e4ea
https://github.com/llvm/llvm-project/commit/43ec9e18938930546e63db41ecda26d3de30e4ea
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/www/cxx_status.html
Log Message:
-----------
[Clang] Mark that P2280R4 was approved as a dr in the status page
Commit: b25b38412807615d2e54702435f67b5c5b7170c0
https://github.com/llvm/llvm-project/commit/b25b38412807615d2e54702435f67b5c5b7170c0
Author: Adrian Kuegel <akuegel at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M mlir/lib/Conversion/MPIToLLVM/MPIToLLVM.cpp
Log Message:
-----------
[mlir] Apply ClangTidy finding (NFC)
prefer using 'override' or (rarely) 'final' instead of 'virtual'
Commit: 66d4294a77dc9ba7a5b94b3d3279a1e76ae026d1
https://github.com/llvm/llvm-project/commit/66d4294a77dc9ba7a5b94b3d3279a1e76ae026d1
Author: Adrian Kuegel <akuegel at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M mlir/lib/Conversion/MPIToLLVM/MPIToLLVM.cpp
Log Message:
-----------
Revert "[mlir] Apply ClangTidy finding (NFC)"
This reverts commit b25b38412807615d2e54702435f67b5c5b7170c0.
Applied the finding manually and got it wrong.
Commit: cd4c10afea7eaaf87c1830e340863f0bf8745b0b
https://github.com/llvm/llvm-project/commit/cd4c10afea7eaaf87c1830e340863f0bf8745b0b
Author: Adrian Kuegel <akuegel at google.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M mlir/lib/Conversion/MPIToLLVM/MPIToLLVM.cpp
Log Message:
-----------
[mlir] Apply ClangTidy finding (NFC)
prefer using 'override' or (rarely) 'final' instead of 'virtual'
second attempt
Commit: 53d433e702736f9edfee57ec2c1628c729336866
https://github.com/llvm/llvm-project/commit/53d433e702736f9edfee57ec2c1628c729336866
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/functions.cpp
Log Message:
-----------
[clang][bytecode] Only emit literal_comparison for string literals (#129691)
This is what the current interpreter does as well.
Commit: 22d8ba3dbc732fdf4acf830e741d972be282f827
https://github.com/llvm/llvm-project/commit/22d8ba3dbc732fdf4acf830e741d972be282f827
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] getConstVector - use APInt::extractBits instead of shift+mask. NFC.
Commit: b2d70e8796ab68a80567fb794079ee07bb243f6e
https://github.com/llvm/llvm-project/commit/b2d70e8796ab68a80567fb794079ee07bb243f6e
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Use Builder to create cast recipes in VPlanTransforms (NFC).
Use VPBuilder in a few more places. This avoids manual insertions and
will make changing the cast recipe easier in the future.
Commit: f838a5e96cb15f3cd70b2f26db0b520004350c7e
https://github.com/llvm/llvm-project/commit/f838a5e96cb15f3cd70b2f26db0b520004350c7e
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
[clang][bytecode] Fix diagnostic difference with opaque call cmps (#129702)
Try to dig out the call expression and diagnose this as an opaque call.
Commit: b2e1758bba1a04f3e4b4ca2e6ff50a879763166b
https://github.com/llvm/llvm-project/commit/b2e1758bba1a04f3e4b4ca2e6ff50a879763166b
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-03-04 (Tue, 04 Mar 2025)
Changed paths:
M .ci/metrics/metrics.py
M .github/workflows/build-metrics-container.yml
M .github/workflows/ci-post-commit-analyzer.yml
M .github/workflows/commit-access-review.yml
M .github/workflows/containers/github-action-ci/Dockerfile
M .github/workflows/docs.yml
M .github/workflows/email-check.yaml
M .github/workflows/issue-release-workflow.yml
M .github/workflows/issue-subscriber.yml
M .github/workflows/issue-write.yml
M .github/workflows/libc-fullbuild-tests.yml
M .github/workflows/libc-overlay-tests.yml
M .github/workflows/libclang-abi-tests.yml
M .github/workflows/llvm-bugs.yml
M .github/workflows/llvm-project-tests.yml
M .github/workflows/llvm-tests.yml
M .github/workflows/merged-prs.yml
M .github/workflows/new-prs.yml
M .github/workflows/pr-code-format.yml
M .github/workflows/pr-subscriber.yml
M .github/workflows/release-binaries.yml
M .github/workflows/release-documentation.yml
M .github/workflows/release-doxygen.yml
M .github/workflows/release-lit.yml
M .github/workflows/version-check.yml
M bolt/include/bolt/Core/BinaryContext.h
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/include/bolt/Passes/PatchEntries.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Passes/ADRRelaxationPass.cpp
M bolt/lib/Passes/PatchEntries.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
A bolt/lib/Target/AArch64/AArch64MCSymbolizer.cpp
A bolt/lib/Target/AArch64/AArch64MCSymbolizer.h
M bolt/lib/Target/AArch64/CMakeLists.txt
M bolt/test/X86/Inputs/define_bar.s
M clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.cpp
M clang-tools-extra/clangd/TidyProvider.cpp
M clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-values.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/unused-using-decls.cpp
M clang/bindings/python/clang/cindex.py
M clang/bindings/python/tests/cindex/test_type.py
M clang/cmake/caches/BOLT.cmake
M clang/docs/HIPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/UndefinedBehaviorSanitizer.rst
M clang/docs/analyzer/checkers.rst
M clang/include/clang-c/Index.h
A clang/include/clang/AST/DeclOpenACC.h
M clang/include/clang/AST/DeclVisitor.h
M clang/include/clang/AST/JSONNodeDumper.h
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/AST/TextNodeDumper.h
M clang/include/clang/AST/Type.h
M clang/include/clang/AST/VTableBuilder.h
M clang/include/clang/Basic/ABI.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DeclNodes.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticIDs.h
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/OpenACCClauses.def
M clang/include/clang/Basic/Sanitizers.def
M clang/include/clang/Basic/Specifiers.h
M clang/include/clang/Basic/StmtNodes.td
R clang/include/clang/CIR/Dialect/IR/CIRAttrVisitor.h
M clang/include/clang/Driver/Options.td
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M clang/include/clang/Sema/Overload.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaBase.h
M clang/include/clang/Sema/SemaOpenACC.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Serialization/ASTRecordReader.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
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M clang/lib/AST/ByteCode/Descriptor.cpp
M clang/lib/AST/ByteCode/Descriptor.h
M clang/lib/AST/ByteCode/DynamicAllocator.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
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M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/CMakeLists.txt
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A clang/lib/AST/DeclOpenACC.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/MicrosoftMangle.cpp
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M clang/lib/Driver/ToolChains/Arch/ARM.cpp
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M clang/lib/Driver/ToolChains/Flang.cpp
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M clang/lib/Driver/ToolChains/WebAssembly.cpp
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M clang/test/SemaOpenACC/data-construct.cpp
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M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/test/SemaOpenACC/unimplemented-construct.c
M clang/tools/c-index-test/c-index-test.c
M clang/tools/driver/CMakeLists.txt
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CIndexCXX.cpp
M clang/tools/libclang/CXCursor.cpp
M clang/tools/libclang/CXType.cpp
M clang/tools/libclang/libclang.map
M clang/unittests/AST/ByteCode/toAPValue.cpp
M clang/unittests/Analysis/ExprMutationAnalyzerTest.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/SortIncludesTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M clang/utils/perf-training/perf-helper.py
M clang/www/cxx_status.html
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/test/ubsan/TestCases/Float/cast-overflow.cpp
M flang-rt/cmake/modules/AddFlangRTOffload.cmake
M flang-rt/lib/cuda/memory.cpp
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M flang/include/flang/Evaluate/tools.h
R flang/include/flang/Lower/DumpEvaluateExpr.h
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A flang/include/flang/Semantics/dump-expr.h
M flang/lib/Evaluate/check-expression.cpp
M flang/lib/Evaluate/fold-logical.cpp
M flang/lib/Evaluate/fold.cpp
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Evaluate/shape.cpp
M flang/lib/Evaluate/tools.cpp
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/CMakeLists.txt
M flang/lib/Lower/ConvertConstant.cpp
M flang/lib/Lower/ConvertExpr.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
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M flang/lib/Optimizer/Builder/HLFIRTools.cpp
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M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/lib/Parser/openmp-parsers.cpp
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M flang/lib/Semantics/data-to-inits.cpp
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A flang/lib/Semantics/dump-expr.cpp
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/pointer-assignment.cpp
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M libc/utils/MPCWrapper/MPCUtils.h
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M libcxx/docs/Status/Cxx23Issues.csv
M libcxx/docs/Status/Cxx2cIssues.csv
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M libcxx/include/__iterator/istream_iterator.h
M libcxx/include/__vector/vector.h
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M libcxx/include/chrono
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M libcxx/test/std/algorithms/alg.modifying.operations/alg.partitions/stable_partition.pass.cpp
M libcxx/test/std/algorithms/robust_against_proxy_iterators_lifetime_bugs.pass.cpp
M libcxx/test/std/algorithms/robust_re_difference_type.compile.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_range.pass.cpp
M libcxx/test/std/input.output/iostream.format/std.manip/setfill_wchar_max.pass.cpp
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A libcxx/test/std/language.support/support.initlist/support.initlist.syn/specialization.verify.cpp
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M libcxx/test/std/localization/locale.categories/category.monetary/locale.money.get/locale.money.get.members/get_long_double_ru_RU.pass.cpp
M libcxx/test/std/localization/locale.categories/category.monetary/locale.money.put/locale.money.put.members/put_long_double_fr_FR.pass.cpp
M libcxx/test/std/localization/locale.categories/category.monetary/locale.money.put/locale.money.put.members/put_long_double_ru_RU.pass.cpp
M libcxx/test/std/localization/locale.categories/category.monetary/locale.moneypunct.byname/thousands_sep.pass.cpp
M libcxx/test/std/localization/locale.categories/facet.numpunct/locale.numpunct.byname/thousands_sep.pass.cpp
M libcxx/test/std/numerics/numeric.ops/numeric.ops.gcd/gcd.pass.cpp
M libcxx/test/std/re/re.alg/re.alg.match/awk.locale.pass.cpp
M libcxx/test/std/re/re.alg/re.alg.match/basic.locale.pass.cpp
M libcxx/test/std/re/re.alg/re.alg.match/ecma.locale.pass.cpp
M libcxx/test/std/re/re.alg/re.alg.match/extended.locale.pass.cpp
M libcxx/test/std/re/re.alg/re.alg.search/awk.locale.pass.cpp
M libcxx/test/std/re/re.alg/re.alg.search/basic.locale.pass.cpp
M libcxx/test/std/re/re.alg/re.alg.search/ecma.locale.pass.cpp
M libcxx/test/std/re/re.alg/re.alg.search/extended.locale.pass.cpp
M libcxx/test/std/re/re.traits/lookup_collatename.pass.cpp
M libcxx/test/std/thread/futures/futures.async/thread_create_failure.pass.cpp
M libcxx/test/std/time/time.duration/time.duration.nonmember/ostream.pass.cpp
M libcxx/test/std/utilities/format/format.formattable/concept.formattable.compile.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.locking/enable_nonlocking_formatter_optimization.compile.pass.cpp
M libcxx/test/support/locale_helpers.h
M libcxx/utils/libcxx/test/features.py
M lld/COFF/Config.h
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M lld/COFF/DriverUtils.cpp
M lld/COFF/SymbolTable.cpp
M lld/COFF/SymbolTable.h
M lld/COFF/Writer.cpp
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M llvm/include/llvm/ADT/SCCIterator.h
M llvm/include/llvm/AsmParser/LLToken.h
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M llvm/include/llvm/CodeGen/ByteProvider.h
M llvm/include/llvm/CodeGen/CalcSpillWeights.h
M llvm/include/llvm/CodeGen/CallingConvLower.h
A llvm/include/llvm/CodeGen/ExpandPostRAPseudos.h
M llvm/include/llvm/CodeGen/FastISel.h
A llvm/include/llvm/CodeGen/FixupStatepointCallerSaved.h
M llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
M llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
M llvm/include/llvm/CodeGen/LiveInterval.h
M llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
M llvm/include/llvm/CodeGen/MachineFrameInfo.h
A llvm/include/llvm/CodeGen/MachineSink.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/CodeGen/RegAllocGreedyPass.h
M llvm/include/llvm/CodeGen/Register.h
M llvm/include/llvm/CodeGen/RegisterPressure.h
A llvm/include/llvm/CodeGen/RemoveRedundantDebugValues.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/Analysis.h
M llvm/include/llvm/IR/CallingConv.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/MC/MCAsmInfo.h
M llvm/include/llvm/MC/MCAsmMacro.h
M llvm/include/llvm/MC/MCExpr.h
M llvm/include/llvm/MC/MCFixup.h
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/include/llvm/MC/MCParser/MCAsmParser.h
M llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/ProfileData/Coverage/MCDCTypes.h
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/SandboxIR/Region.h
M llvm/include/llvm/Support/thread.h
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/include/llvm/TargetParser/ARMTargetParser.h
M llvm/include/llvm/Transforms/IPO/ProfiledCallGraph.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h
A llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Debug.h
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
M llvm/lib/Analysis/FunctionPropertiesAnalysis.cpp
M llvm/lib/Analysis/IRSimilarityIdentifier.cpp
M llvm/lib/Analysis/InlineSizeEstimatorAnalysis.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/MemoryProfileInfo.cpp
M llvm/lib/Analysis/ProfileSummaryInfo.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/CGData/CodeGenData.cpp
M llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
M llvm/lib/CodeGen/AggressiveAntiDepBreaker.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
M llvm/lib/CodeGen/BranchFolding.cpp
M llvm/lib/CodeGen/CFIInstrInserter.cpp
M llvm/lib/CodeGen/CalcSpillWeights.cpp
M llvm/lib/CodeGen/CallingConvLower.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
M llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/CodeGen/IfConversion.cpp
M llvm/lib/CodeGen/InlineSpiller.cpp
M llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
M llvm/lib/CodeGen/LiveDebugVariables.cpp
M llvm/lib/CodeGen/LiveVariables.cpp
M llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineBasicBlock.cpp
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/CodeGen/MachineCSE.cpp
M llvm/lib/CodeGen/MachineCycleAnalysis.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineTraceMetrics.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/PHIElimination.cpp
M llvm/lib/CodeGen/PHIEliminationUtils.cpp
M llvm/lib/CodeGen/PHIEliminationUtils.h
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/ReachingDefAnalysis.cpp
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/RegisterScavenging.cpp
M llvm/lib/CodeGen/RemoveRedundantDebugValues.cpp
M llvm/lib/CodeGen/RenameIndependentSubregs.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
M llvm/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/lib/CodeGen/SplitKit.h
M llvm/lib/CodeGen/StackMaps.cpp
M llvm/lib/CodeGen/TailDuplicator.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/lib/CodeGen/WindowScheduler.cpp
M llvm/lib/DebugInfo/GSYM/DwarfTransformer.cpp
M llvm/lib/ExecutionEngine/Orc/Layer.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/EHPersonalities.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/LTO/LTOCodeGenerator.cpp
M llvm/lib/MC/MCAsmBackend.cpp
M llvm/lib/MC/MCAsmInfo.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCELFStreamer.cpp
M llvm/lib/MC/MCExpr.cpp
M llvm/lib/MC/MCNullStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCParser/AsmLexer.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCParser/ELFAsmParser.cpp
M llvm/lib/MC/MCParser/MCAsmLexer.cpp
M llvm/lib/MC/MCParser/MCAsmParserExtension.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIModeRegister.cpp
M llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
M llvm/lib/Target/ARM/MVELaneInterleavingPass.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.cpp
M llvm/lib/Target/Hexagon/HexagonCopyHoisting.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/M68k/MCTargetDesc/M68kMCAsmInfo.cpp
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.h
M llvm/lib/Target/Mips/Mips16ISelLowering.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.h
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
M llvm/lib/Target/NVPTX/CMakeLists.txt
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h
M llvm/lib/Target/NVPTX/NVPTX.h
A llvm/lib/Target/NVPTX/NVPTXForwardParams.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrFormats.td
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCInstrVSX.td
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
M llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.h
M llvm/lib/Target/SPIRV/SPIRV.h
M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
A llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/lib/Target/SPIRV/SPIRVMCInstLower.cpp
M llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.td
M llvm/lib/Target/VE/MCTargetDesc/VEMCAsmInfo.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86FixupKinds.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFTargetStreamer.cpp
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrFragments.td
M llvm/lib/Target/X86/X86InstrOperands.td
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/lib/Transforms/IPO/ElimAvailExtern.cpp
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/IPO/ModuleInliner.cpp
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/TransactionAcceptOrRevert.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/TransactionSave.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SeedCollector.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanHCFGBuilder.cpp
M llvm/lib/Transforms/Vectorize/VPlanHCFGBuilder.h
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
A llvm/test/Assembler/riscv_vls_cc.ll
M llvm/test/Bitcode/compatibility.ll
M llvm/test/CodeGen/AArch64/16bit-float-promotion-with-nofp.ll
A llvm/test/CodeGen/AArch64/GlobalISel/emutls-fallback.ll
A llvm/test/CodeGen/AArch64/arm64ec-eh.ll
M llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir
M llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir
M llvm/test/CodeGen/AArch64/loop-sink.mir
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/pr51516.mir
M llvm/test/CodeGen/AArch64/seqpaircopy.mir
M llvm/test/CodeGen/AArch64/sink-and-fold-preserve-debugloc.mir
M llvm/test/CodeGen/AArch64/spill-fold.mir
M llvm/test/CodeGen/AArch64/sve-fcvt.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-split-fcvt.ll
M llvm/test/CodeGen/AArch64/sve-vector-splat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/acc-ldst.ll
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nondeterminism.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
A llvm/test/CodeGen/AMDGPU/inst-prefetch-hint.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-unoptimized-debug-data.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-cycle.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/mmra.ll
M llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
M llvm/test/CodeGen/AMDGPU/mode-register.mir
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
M llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll
M llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
A llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel-dst.mir
A llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel-src.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
A llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
A llvm/test/CodeGen/AMDGPU/splitkit-do-not-undo-subclass-split-with-remat.mir
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/ARM/machine-sink-multidef.mir
M llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir
M llvm/test/CodeGen/LoongArch/lsx/vec-sext.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll
M llvm/test/CodeGen/MIR/AArch64/lit.local.cfg
M llvm/test/CodeGen/MIR/Generic/runPass.mir
A llvm/test/CodeGen/NVPTX/discard.ll
A llvm/test/CodeGen/NVPTX/forward-ld-param.ll
M llvm/test/CodeGen/NVPTX/i128-array.ll
M llvm/test/CodeGen/NVPTX/lower-args-gridconstant.ll
M llvm/test/CodeGen/NVPTX/lower-args.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
M llvm/test/CodeGen/PowerPC/licm-xxsplti.ll
M llvm/test/CodeGen/PowerPC/llvm.modf.ll
M llvm/test/CodeGen/PowerPC/memset-tail.ll
M llvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir
M llvm/test/CodeGen/RISCV/MachineSink-implicit-x0.mir
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/features-info.ll
A llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
M llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
A llvm/test/CodeGen/RISCV/rvv/zvbb-demanded-bits.ll
A llvm/test/CodeGen/SPIRV/pointers/array-skips-gep.ll
A llvm/test/CodeGen/SPIRV/pointers/getelementptr-downcast-vector.ll
M llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir
M llvm/test/CodeGen/SystemZ/copy-phys-reg-gr64-to-fp64.mir
M llvm/test/CodeGen/SystemZ/machinesink-dead-cc.mir
M llvm/test/CodeGen/Thumb/high-reg-clobber.mir
M llvm/test/CodeGen/X86/apx/setzucc.ll
M llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc.ll
M llvm/test/CodeGen/X86/combine-i64-trunc-srl-add.ll
M llvm/test/CodeGen/X86/cycle-info.mir
M llvm/test/CodeGen/X86/eq-or-eq-range-of-2.ll
M llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll
M llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll
A llvm/test/CodeGen/X86/kmov.ll
A llvm/test/CodeGen/X86/lea-16bit.ll
A llvm/test/CodeGen/X86/lea-8bit.ll
M llvm/test/CodeGen/X86/limit-split-cost.mir
M llvm/test/CodeGen/X86/machinesink-debug-inv-0.mir
M llvm/test/CodeGen/X86/pr78897.ll
M llvm/test/CodeGen/X86/setcc-lowering.ll
M llvm/test/CodeGen/X86/statepoint-fixup-call.mir
M llvm/test/CodeGen/X86/statepoint-fixup-copy-prop-neg.mir
M llvm/test/CodeGen/X86/statepoint-fixup-copy-prop.mir
M llvm/test/CodeGen/X86/statepoint-fixup-invoke.mir
M llvm/test/CodeGen/X86/statepoint-fixup-shared-ehpad.mir
M llvm/test/CodeGen/X86/statepoint-fixup-undef-def.mir
M llvm/test/CodeGen/X86/statepoint-fixup-undef.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
M llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll
M llvm/test/CodeGen/X86/vselect-constants.ll
M llvm/test/DebugInfo/ARM/tls.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/after-inlining.ll
M llvm/test/DebugInfo/MIR/X86/remove-redundant-dbg-vals.mir
M llvm/test/DebugInfo/MIR/X86/sink-leaves-undef.mir
M llvm/test/DebugInfo/X86/undef-dbg-val.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-st1.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-st1_lane.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-st1_origins.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-tbl.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt.ll
A llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmul.ll
R llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_tbl.ll
R llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vmul.ll
R llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst.ll
R llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_lane.ll
R llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_origins.ll
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AsmParser/directive_loc.s
M llvm/test/MC/COFF/cv-errors.s
M llvm/test/MC/ELF/elf_directive_section.s
M llvm/test/MC/Mips/expr1.s
A llvm/test/MC/Mips/fixup-expr.s
M llvm/test/MC/Mips/imm-operand-err.s
M llvm/test/MC/Mips/macro-aliases-invalid-wrong-error.s
M llvm/test/MC/Mips/relocation.s
M llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
M llvm/test/Transforms/Attributor/value-simplify.ll
M llvm/test/Transforms/GVN/opt-remarks.ll
M llvm/test/Transforms/InstCombine/load.ll
M llvm/test/Transforms/InstSimplify/icmp-monotonic.ll
M llvm/test/Transforms/LoopDeletion/diundef.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_estimated_tc.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_memcheck_cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-fixed-order-recurrence.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/MergeFunc/mergefunc-preserve-debug-info.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/spillcost.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-cast-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-cast.ll
M llvm/test/Transforms/SLPVectorizer/X86/debug-info-salvage.ll
M llvm/test/Transforms/SROA/alignment.ll
M llvm/test/Transforms/SROA/vector-promotion.ll
M llvm/test/Transforms/SafeStack/X86/debug-loc2.ll
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
M llvm/test/Transforms/VectorCombine/X86/load-extractelement-scalarization.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/nvptx-basic.ll.expected
A llvm/test/tools/llc/new-pm/x86_64-regalloc-pipeline.mir
A llvm/test/tools/llvm-exegesis/RISCV/latency-by-load.s
M llvm/test/tools/llvm-exegesis/RISCV/rvv/explicit-sew.test
M llvm/test/tools/llvm-exegesis/RISCV/rvv/filter.test
M llvm/test/tools/llvm-exegesis/RISCV/rvv/reduction.test
M llvm/test/tools/llvm-exegesis/RISCV/rvv/skip-rm.test
M llvm/test/tools/llvm-exegesis/RISCV/rvv/valid-sew-zvk.test
M llvm/test/tools/llvm-exegesis/RISCV/rvv/valid-sew.test
M llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-merged-callsites-dsym.yaml
M llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlseg-vsseg.s
M llvm/test/tools/llvm-rc/windres-preproc.test
M llvm/tools/bugpoint/ExecutionDriver.cpp
M llvm/tools/bugpoint/OptimizerDriver.cpp
M llvm/tools/llc/NewPMDriver.cpp
M llvm/tools/llvm-as/llvm-as.cpp
M llvm/tools/llvm-cat/llvm-cat.cpp
M llvm/tools/llvm-cfi-verify/llvm-cfi-verify.cpp
M llvm/tools/llvm-cxxdump/llvm-cxxdump.cpp
M llvm/tools/llvm-cxxmap/llvm-cxxmap.cpp
M llvm/tools/llvm-diff/llvm-diff.cpp
M llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp
M llvm/tools/llvm-extract/llvm-extract.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/tools/llvm-lto/llvm-lto.cpp
M llvm/tools/llvm-lto2/llvm-lto2.cpp
M llvm/tools/llvm-mca/CodeRegion.cpp
M llvm/tools/llvm-mca/CodeRegionGenerator.h
M llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/tools/llvm-readobj/COFFDumper.cpp
M llvm/tools/llvm-undname/llvm-undname.cpp
M llvm/tools/reduce-chunk-list/reduce-chunk-list.cpp
M llvm/tools/yaml2obj/yaml2obj.cpp
M llvm/unittests/SandboxIR/RegionTest.cpp
M llvm/unittests/Support/ProgramTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
M llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/TableGen/FastISelEmitter.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
M llvm/utils/TableGen/X86RecognizableInstr.cpp
M llvm/utils/gn/secondary/bolt/lib/Target/AArch64/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Core/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/NVPTX/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCA/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-exegesis/lib/RISCV/BUILD.gn
M llvm/utils/yaml-bench/YAMLBench.cpp
M mlir/docs/Dialects/Linalg/_index.md
M mlir/include/mlir/Analysis/FlatLinearValueConstraints.h
M mlir/include/mlir/Analysis/Presburger/IntegerRelation.h
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/include/mlir/Dialect/AMDGPU/Utils/Chipset.h
M mlir/include/mlir/Dialect/Affine/Analysis/AffineStructures.h
M mlir/include/mlir/Dialect/Affine/Analysis/Utils.h
M mlir/include/mlir/Dialect/Affine/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgDoc.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
M mlir/include/mlir/Dialect/SCF/Utils/Utils.h
M mlir/include/mlir/Dialect/Tensor/TransformOps/TensorTransformOps.td
M mlir/include/mlir/Dialect/Tensor/Transforms/Transforms.h
M mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/IR/OperationSupport.h
M mlir/include/mlir/IR/Types.h
M mlir/include/mlir/Target/LLVMIR/LLVMImportInterface.h
M mlir/lib/Analysis/FlatLinearValueConstraints.cpp
M mlir/lib/Analysis/Presburger/IntegerRelation.cpp
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/ArithToAMDGPU/ArithToAMDGPU.cpp
M mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/MPIToLLVM/MPIToLLVM.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/lib/Dialect/Affine/Analysis/AffineStructures.cpp
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/SCF/Utils/Utils.cpp
M mlir/lib/Dialect/Tensor/TransformOps/TensorTransformOps.cpp
M mlir/lib/Dialect/Tensor/Transforms/ReshapePatterns.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeDepthwise.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/lib/IR/AffineExpr.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/Types.cpp
M mlir/lib/Target/LLVMIR/CMakeLists.txt
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/lib/Target/LLVMIR/LLVMImportInterface.cpp
A mlir/test/Conversion/AMDGPUToROCDL/8-bit-floats-ocp.mlir
A mlir/test/Conversion/ArithToAMDGPU/8-bit-float-saturation-ocp.mlir
A mlir/test/Conversion/ArithToAMDGPU/8-bit-floats-ocp.mlir
M mlir/test/Conversion/GPUCommon/lower-memcpy-to-gpu-runtime-calls.mlir
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-invalid.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Dialect/Affine/affine-data-copy.mlir
M mlir/test/Dialect/Affine/dma-generate.mlir
M mlir/test/Dialect/Affine/loop-fusion-3.mlir
M mlir/test/Dialect/Affine/loop-fusion.mlir
M mlir/test/Dialect/Affine/parallelize.mlir
M mlir/test/Dialect/Affine/simplify-structures.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Dialect/Linalg/reshape_fusion.mlir
M mlir/test/Dialect/Linalg/transform-op-fuse.mlir
A mlir/test/Dialect/Tensor/bubble-up-extract-slice-op.mlir
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-depthwise.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-using-interface.mlir
M mlir/test/Target/LLVMIR/Import/import-failure.ll
A mlir/test/Target/LLVMIR/Import/intrinsic-unregistered.ll
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
M mlir/test/Target/LLVMIR/openmp-target-private-allocatable.mlir
M mlir/test/lib/Dialect/Tosa/TosaTestPasses.cpp
M mlir/test/mlir-tblgen/constraint-unique.td
M mlir/test/mlir-tblgen/op-attribute.td
M mlir/test/mlir-tblgen/op-decl-and-defs.td
M mlir/test/mlir-tblgen/op-format.td
M mlir/test/mlir-tblgen/op-result.td
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/unittests/IR/OperationSupportTest.cpp
M offload/cmake/caches/AMDGPUBot.cmake
M openmp/runtime/src/kmp_taskdeps.cpp
M utils/bazel/llvm-project-overlay/bolt/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/llvm-config.h
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Rebase, address comments
Created using spr 1.3.5
Compare: https://github.com/llvm/llvm-project/compare/45f17fa983d6...b2e1758bba1a
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