[all-commits] [llvm/llvm-project] 0fcbf1: [Exegesis] Implemented strategy for load operation...

[AnastasiyaChernikova via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0fcbf148df9c6d4f1a12eed356697cda665852e5
      https://github.com/llvm/llvm-project/commit/0fcbf148df9c6d4f1a12eed356697cda665852e5
  Author: AnastasiyaChernikova <anastasiya.chernikova at syntacore.com>
  Date:   2025-03-04 (Tue, 04 Mar 2025)

  Changed paths:
    A llvm/test/tools/llvm-exegesis/RISCV/latency-by-load.s
    M llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp

  Log Message:
  -----------
  [Exegesis] Implemented strategy for load operation (#113458)

This fix helps to map operand memory to destination registers. If
instruction is load, we can self-alias it in case when instruction
overrides whole address register. For that we use provided scratch
memory.



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