[all-commits] [llvm/llvm-project] a619a2: [ARM] Fix lane ordering for AdvSIMD intrinsics on ...

[Oliver Stannard via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a619a2e53a9ba09ba18a047b8389bf4dd1912b72
      https://github.com/llvm/llvm-project/commit/a619a2e53a9ba09ba18a047b8389bf4dd1912b72
  Author: Oliver Stannard <oliver.stannard at arm.com>
  Date:   2025-03-04 (Tue, 04 Mar 2025)

  Changed paths:
    A clang/test/CodeGen/arm-neon-endianness.c
    M clang/utils/TableGen/NeonEmitter.cpp

  Log Message:
  -----------
  [ARM] Fix lane ordering for AdvSIMD intrinsics on big-endian targets (#127068)

In arm-neon.h, we insert shufflevectors around each intrinsic when the
target is big-endian, to compensate for the difference between the
ABI-defined memory format of vectors (with the whole vector stored as
one big-endian access) and LLVM's target-independent expectations (with
the lowest-numbered lane in the lowest address). However, this code was
written for the AArch64 ABI, and the AArch32 ABI differs slightly: it
requires that vectors are stored in memory as-if stored with VSTM, which
does a series of 64-bit accesses, instead of the AArch64 VSTR, which
does a single 128-bit access. This means that for AArch32 we need to
reverse the lanes in each 64-bit chunk of the vector, instead of in the
whole vector.

Since there are only a small number of different shufflevector orderings
needed, I've split them out into macros, so that this doesn't need
separate conditions in each intrinsic definition.



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