[all-commits] [llvm/llvm-project] 201208: [SPIR-V] Stop using Register to represent target s...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 201208998f65c25eca7b8006b1fb8b05d4b21214
      https://github.com/llvm/llvm-project/commit/201208998f65c25eca7b8006b1fb8b05d4b21214
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-03-03 (Mon, 03 Mar 2025)

  Changed paths:
    M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
    M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
    M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.h
    M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
    M llvm/lib/Target/SPIRV/SPIRVMCInstLower.cpp
    M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
    M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h

  Log Message:
  -----------
  [SPIR-V] Stop using Register to represent target specific virtual registers. (#129362)

These were using the virtual register encoding in Register which
required including Register.h in MC layer code which is a layering
violation.

This also required converting Register with bit 31 set to MCRegister
which should be an error. Register with bit 31 set should only be used
for codegen virtual register. I'd like to add assertions to enforce
this.

Migrate to MCRegister and manually create an encoding with bit 31 set.
WebAssembly also does this.

We could consider adding interfaces to MCRegister for target specific
virtual registers.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications