[all-commits] [llvm/llvm-project] 32dffd: [RISCV][MCA] Pick the correct VPseudo sched class ...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 32dffdce0511a9e2358842b8856da1b4103d72cb
      https://github.com/llvm/llvm-project/commit/32dffdce0511a9e2358842b8856da1b4103d72cb
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-02-28 (Fri, 28 Feb 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlseg-vsseg.s

  Log Message:
  -----------
  [RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (#128978)

It seems like we had been picking the wrong VPseudo scheduling class for
indexed memory operations in RISCVMCACustomBehavior: the VPseudo opcode
of indexed memory ops encode two EMULs, one for index and the other for
data. However, in RISCVInversePseudoTable, we're only able to look up
against one of them, yielding an incorrect VPseudo opcode with the wrong
data EEW (index EEW is encoded in the opcode). Since scheduling classes
for indexed memory ops uses data EMUL / EEW in their scheduling class,
we would eventually fetch the wrong scheduling classes with faulty data
EEW.

This patch fixes this issue by deducting the correct index EMUL with
LMUL (data EMUL), SEW (data EEW), and index EEW. With these parameters
we can thus fetch the correct VPseudo opcode with `getVLXPseudo` /
`getVLXSEGPseudo` and friends.

The new search table, RISCVBaseVXMemOpTable, is created to extract the
NF and index EEW info from MC opcode. Otherwise we need to write a
gigantic switch statement to decode this info.



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