[all-commits] [llvm/llvm-project] 813877: [RISCV] Add VL and VTYPE to implicit uses on MC ve...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 81387754c3ebdb0591f6886a5a426fd00703c905
      https://github.com/llvm/llvm-project/commit/81387754c3ebdb0591f6886a5a426fd00703c905
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-02-27 (Thu, 27 Feb 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
    M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/div.s

  Log Message:
  -----------
  [RISCV] Add VL and VTYPE to implicit uses on MC vector instructions that also use FRM (#129130)

We accidentally overwote the VL, VTYPE uses from the base class on any
instruction that also uses FRM.

Not sure why the llvm-mca test changed cycle time.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications