[all-commits] [llvm/llvm-project] d7b360: [libc++] Updates ostream's println LWG status. (#1...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Thu Feb 27 04:21:33 PST 2025
Branch: refs/heads/users/alexey-bataev/spr/slpreduce-number-of-alternate-instruction-where-possible-1
Home: https://github.com/llvm/llvm-project
Commit: d7b3606f7f8665af6b16263c27b132966e0345b2
https://github.com/llvm/llvm-project/commit/d7b3606f7f8665af6b16263c27b132966e0345b2
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M libcxx/docs/Status/Cxx2cIssues.csv
Log Message:
-----------
[libc++] Updates ostream's println LWG status. (#128214)
std::println was originally implemented with support for LWG4088 by
mistake (in 2fd4084fca0c).
The tests already validate the behaviour required by LWG4088.
Fixes: #118348
Commit: a841cf91b3e07000e4397f401630dbbd9556d1c2
https://github.com/llvm/llvm-project/commit/a841cf91b3e07000e4397f401630dbbd9556d1c2
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M libcxx/include/__ostream/print.h
M libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/print.pass.cpp
M libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/vprint_nonunicode.pass.cpp
M libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/vprint_unicode.pass.cpp
Log Message:
-----------
[lib++][print] Don't pad the ostream output. (#128354)
Per [ostream.formatted.reqmts]/3 padding should only be done when
explicitly stated.
Fixes: #116054
Commit: 26be07b8511b703326f2e10864486b5bb9e76196
https://github.com/llvm/llvm-project/commit/26be07b8511b703326f2e10864486b5bb9e76196
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/include/__format/formatter.h
M libcxx/include/__format/formatter_string.h
M libcxx/test/std/utilities/format/format.formattable/concept.formattable.compile.pass.cpp
Log Message:
-----------
[libc++][format] Disables narrow string to wide string formatters. (#128355)
Implements LWG3944: Formatters converting sequences of char to sequences
of wchar_t
Fixes: #105342
Commit: dfda75f2e55ae4536f48e20a1ba71a3c79af1d97
https://github.com/llvm/llvm-project/commit/dfda75f2e55ae4536f48e20a1ba71a3c79af1d97
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
Log Message:
-----------
[AMDGPU][True16][CodeGen] fix test for true16 codegen valu op (#128905)
This is a NFC change. Update the test file and fix the build
https://github.com/llvm/llvm-project/pull/124797 is causing a build
issue
Commit: 8039f8e139aa52561d3482d61328fe7f370056e7
https://github.com/llvm/llvm-project/commit/8039f8e139aa52561d3482d61328fe7f370056e7
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
A llvm/test/MC/RISCV/xrivosvisni-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV][MC] Add assembler support for XRivosVisni (#128773)
This implements assembler support for the XRivosVisni custom/vendor
extension from Rivos Inc. which is defined in:
https://github.com/rivosinc/rivos-custom-extensions (See
src/xrivosvisni.adoc)
Codegen support will follow in separate changes.
Commit: f161b1b5265baadc443506b88bd1084adccaef90
https://github.com/llvm/llvm-project/commit/f161b1b5265baadc443506b88bd1084adccaef90
Author: Peng Liu <winner245 at hotmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M libcxx/test/std/algorithms/alg.modifying.operations/alg.rotate/pstl.rotate_copy.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.rotate/ranges.rotate_copy.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.rotate/ranges_rotate.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.rotate/rotate.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.rotate/rotate_copy.pass.cpp
Log Message:
-----------
[libc++][test] Refactor tests for rotate and rotate_copy (#126458)
This PR refactors the tests and fix some problems:
- Refactor similar tests using `types::for_each` to remove redundant code;
- Explicitly include the missing header `type_algorithms.h` instead of relying
on a transitive include;
- Fix the incorrect constexpr declaration in `rotate.pass.cpp`, where
the `test()` function is incorrectly defined as `TEST_CONSTEXPR_CXX17`,
which is wrong since `std::rotate()` becomes constexpr only since C++20.
Commit: 8ffda96dbedeeaf8c000ec7ee2a156d1d6e3fd2a
https://github.com/llvm/llvm-project/commit/8ffda96dbedeeaf8c000ec7ee2a156d1d6e3fd2a
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
M llvm/test/tools/llvm-mca/RISCV/SiFiveP400/div.s
M llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/div.s
Log Message:
-----------
[RISCV] Update MicroOpBufferSize in P400 & P600 scheduling models (#128786)
The numbers we previously picked for MicroOpBufferSize in both P400 and
P600's scheduling models turned out to be too conservative and didn't
properly reflect the characteristics of our microarchitectures. This
patch updates these numbers to be more faithful to our hardware.
This is unlikely to have any significant impact on MachineScheduler as
it only uses MicroOpBufferSize in few places. That said, it is supposed
to improve the accuracy of llvm-mca.
Commit: c0abae33d6e73356389295a6d897a21630fcff58
https://github.com/llvm/llvm-project/commit/c0abae33d6e73356389295a6d897a21630fcff58
Author: Kiran Chandramohan <kiran.chandramohan at arm.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-private.mlir
Log Message:
-----------
[MLIR][OPENMP] Relax requirement about branches as terminator of private alloc (#128481)
Fixes #126966
Commit: 7ffeab3121c984cc00f79b0a78f372a4f7526e3b
https://github.com/llvm/llvm-project/commit/7ffeab3121c984cc00f79b0a78f372a4f7526e3b
Author: Daniel Thornburgh <dthorn at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M lld/ELF/Writer.cpp
M lld/test/ELF/linkerscript/symbol-assign-many-passes2.test
Log Message:
-----------
[LLD][ELF] Generically report "address assignment did not converge" (#128774)
There are considerable number of changes done in the address assignment
fixed point loop, and errors in any of them could cause address
assignment not to converge. However, this is reported to the user as
either "thunk creation not converged" or "relaxation not converged".
We saw a confused bug about this in the wild when spilling failed to
converge. (I'm working on a fix for that.)
We may eventually want a complete reason system when reporting address
assignment taking too many passes, but in the interim it seems prudent
to generalize the error message to "address assignment did not
converge".
Commit: 7717a549e91c4fb554b78fce38e75b0147fb6cac
https://github.com/llvm/llvm-project/commit/7717a549e91c4fb554b78fce38e75b0147fb6cac
Author: Peng Liu <winner245 at hotmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M libcxx/docs/ReleaseNotes/21.rst
M libcxx/include/__algorithm/equal.h
M libcxx/include/__bit_reference
M libcxx/include/__vector/comparison.h
M libcxx/include/bitset
M libcxx/test/benchmarks/algorithms/equal.bench.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.equal/equal.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.equal/ranges.equal.pass.cpp
Log Message:
-----------
[libc++] Optimize ranges::equal for vector<bool>::iterator (#121084)
This PR optimizes the performance of `std::ranges::equal` for
`vector<bool>::iterator`, addressing a subtask outlined in issue #64038.
The optimizations yield performance improvements of up to 188x for
aligned equality comparison and 82x for unaligned equality
comparison. Moreover, comprehensive tests covering up to 4 storage words
(256 bytes) with odd and even bit sizes are provided, which validate the
proposed optimizations in this patch.
Commit: 722c7c0b0f9a3f74cb6755fa40d9b88e77d79495
https://github.com/llvm/llvm-project/commit/722c7c0b0f9a3f74cb6755fa40d9b88e77d79495
Author: Iñaki Amatria Barral <140811900+inaki-amatria at users.noreply.github.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M flang/lib/Semantics/mod-file.cpp
A flang/test/Semantics/Inputs/modfile72.f90
A flang/test/Semantics/modfile72.f90
Log Message:
-----------
[flang][Semantics] Ensure deterministic mod file output (#128655)
This PR adds a test to ensure deterministic ordering in `.mod` files. It
also includes related changes to prevent non-deterministic symbol
ordering caused by pointers outside the cooked source. This issue is
particularly noticeable when using Flang as a library and compiling the
same files multiple times.
Commit: 5d501c6137976ff1f14f3b0e2e593fb9740d0146
https://github.com/llvm/llvm-project/commit/5d501c6137976ff1f14f3b0e2e593fb9740d0146
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/docs/RISCVUsage.rst
Log Message:
-----------
[RISCV][Docs] RISCV -> RISC-V in RISCVUsage.rst. NFC (#128906)
Commit: 870b376f0059458df382de0f2cfa712a20e710dc
https://github.com/llvm/llvm-project/commit/870b376f0059458df382de0f2cfa712a20e710dc
Author: Justin Bogner <mail at justinbogner.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/docs/DirectX/DXILResources.rst
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILOpBuilder.cpp
M llvm/lib/Target/DirectX/DXILOpBuilder.h
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
A llvm/test/CodeGen/DirectX/CBufferLoadLegacy-errors.ll
A llvm/test/CodeGen/DirectX/CBufferLoadLegacy.ll
M llvm/utils/TableGen/DXILEmitter.cpp
Log Message:
-----------
[DirectX] Support the CBufferLoadLegacy operation (#128699)
Fixes #112992
Commit: 317461ed61002de7f6e54ab0a26780c6d2726bb0
https://github.com/llvm/llvm-project/commit/317461ed61002de7f6e54ab0a26780c6d2726bb0
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Avoid a std::string allocation for the help output (NFC)
Don't create a temporary `std::string` for the help output, just write
it to `llvm::outs()` directly.
Commit: 159b872b37363511a359c800bcc9230bb09f2457
https://github.com/llvm/llvm-project/commit/159b872b37363511a359c800bcc9230bb09f2457
Author: Vy Nguyen <vyng at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M lldb/source/Core/CMakeLists.txt
M lldb/source/Core/Telemetry.cpp
M lldb/unittests/Core/CMakeLists.txt
M lldb/unittests/Core/TelemetryTest.cpp
M llvm/CMakeLists.txt
M llvm/cmake/modules/LLVMConfig.cmake.in
M llvm/include/llvm/Config/llvm-config.h.cmake
M llvm/include/llvm/Telemetry/Telemetry.h
M llvm/lib/CMakeLists.txt
M llvm/lib/Telemetry/Telemetry.cpp
M llvm/unittests/CMakeLists.txt
M llvm/unittests/Telemetry/TelemetryTest.cpp
M llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn
M utils/bazel/llvm_configs/llvm-config.h.cmake
Log Message:
-----------
[llvm][telemetry]Change Telemetry-disabling mechanism. (#128534)
Details:
- Previously, we used the LLVM_BUILD_TELEMETRY flag to control whether
any Telemetry code will be built. This has proven to cause more nuisance
to both users of the Telemetry and any further extension of it. (Eg., we
needed to put #ifdef around caller/user code)
- So the new approach is to:
+ Remove this flag and introduce LLVM_ENABLE_TELEMETRY which would be
true by default.
+ If LLVM_ENABLE_TELEMETRY is set to FALSE (at buildtime), the library
would still be built BUT Telemetry cannot be enabled. And no data can be
collected.
The benefit of this is that it simplifies user (and extension) code
since we just need to put the check on Config::EnableTelemetry. Besides,
the Telemetry library itself is very small, hence the additional code to
be built would not cause any difference in build performance.
---------
Co-authored-by: Pavel Labath <pavel at labath.sk>
Commit: 4059faf61355f15818d4bb800e8a3337658f3b97
https://github.com/llvm/llvm-project/commit/4059faf61355f15818d4bb800e8a3337658f3b97
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[TableGen] Update comment for size of NumToSkip field in DecoderEmitter. NFC
NumToSkip is 24 bits. It used to be 16 bits.
Commit: 5a5a9e79369ae6cf320fc7b79a48d3e8b60f19a9
https://github.com/llvm/llvm-project/commit/5a5a9e79369ae6cf320fc7b79a48d3e8b60f19a9
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/include/llvm/Telemetry/Telemetry.h
Log Message:
-----------
[Telemetry] Fix a warning
This patch fixes:
llvm/include/llvm/Telemetry/Telemetry.h:66:8: error:
'llvm::telemetry::Config' has virtual functions but non-virtual
destructor [-Werror,-Wnon-virtual-dtor]
Commit: 74306afe87b85cb9b5734044eb6c74b8290098b3
https://github.com/llvm/llvm-project/commit/74306afe87b85cb9b5734044eb6c74b8290098b3
Author: AdityaK <hiraditya at msn.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/docs/GettingInvolved.rst
Log Message:
-----------
Fix the schedule of vectorizer improvement monthly sync
Commit: c690b3065d58168c2da0b580cfd770ea256d2f82
https://github.com/llvm/llvm-project/commit/c690b3065d58168c2da0b580cfd770ea256d2f82
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[Bazel] Port 128541 (#128809)
Commit: 1be48fdf8bb25f82889aa75ca130e7aaf86295fe
https://github.com/llvm/llvm-project/commit/1be48fdf8bb25f82889aa75ca130e7aaf86295fe
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-invalid.mlir
Log Message:
-----------
[mlir][TosaToLinalg] Fix TosaToLinalg to restrict `tosa.cast` types to integer or float (#128859)
This PR fixes a bug where `TosaToLinalg` incorrectly allows `tosa.cast`
to accept types other than integer or float.
Fixes #116342.
Commit: f6703a4ff56972ed6bd1693cdb51cc3bd5848582
https://github.com/llvm/llvm-project/commit/f6703a4ff56972ed6bd1693cdb51cc3bd5848582
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/include/llvm/Transforms/Instrumentation/PGOCtxProfLowering.h
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/Instrumentation/PGOCtxProfLowering.cpp
A llvm/test/Transforms/PGOProfile/ctx-instrumentation-block-inline.ll
Log Message:
-----------
[ctxprof] don't inline weak symbols after instrumentation (#128811)
Contextual profiling identifies functions by GUID. Functions that may get overridden by the linker with a prevailing copy may have, during instrumentation, different variants in different modules. If these variants get inlined before linking (here I assume thinlto), they will identify themselves to the ctxprof runtime as their GUID, leading to issues - they may have different counter counts, for instance.
If we block their inlining in the pre-thinlink compilation, only the prevailing copy will survive post-thinlink and the confusion is avoided.
The change introduces a small pass just for this purpose, which marks any symbols that could be affected by the above as `noinline` (even if they were `alwaysinline`). We already carried out some inlining (via the preinliner), before instrumenting, so technically the `alwaysinline` directives were honored.
We could later (different patch) choose to mark them back to their original attribute (none or `alwaysinline`) post-thinlink, if we want to - but experimentally that doesn't really change much of the performance of the instrumented binary.
Commit: cfdeca394e8c212bf0ff38e5bb8a8ed36954132c
https://github.com/llvm/llvm-project/commit/cfdeca394e8c212bf0ff38e5bb8a8ed36954132c
Author: Nico Weber <thakis at chromium.org>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/utils/TableGen/BUILD.gn
Log Message:
-----------
[gn build] Port 8dd8e5f7d692 (BuiltinTemplates.td)
Commit: 1e246704e23e3dcae16adbf68cc10b668a8db680
https://github.com/llvm/llvm-project/commit/1e246704e23e3dcae16adbf68cc10b668a8db680
Author: John Harrison <harjohn at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/IOStream.cpp
M lldb/tools/lldb-dap/IOStream.h
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Use existing lldb::IOObjectSP for DAP IO (NFC). (#128750)
This simplifies the IOStream.cpp implementation by building on top of
the existing lldb::IOObjectSP.
Additionally, this should help ensure clients connected of a
`--connection` specifier properly detect shutdown requests when the
Socket is closed. Previously, the StreamDescriptor was just accessing
the underlying native handle and was not aware of the `Close()` call to
the Socket itself.
This is both nice to have for simplifying the existing code and this
unblocks an upcoming refactor to support the cancel request.
---------
Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
Commit: 2c36411ed26e9ad0cc7e20bac11a34461682bccf
https://github.com/llvm/llvm-project/commit/2c36411ed26e9ad0cc7e20bac11a34461682bccf
Author: elhewaty <mohamedatef1698 at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/include/forward_list
M libcxx/include/list
A libcxx/test/libcxx/containers/sequences/forwardlist/bool-conversion.pass.cpp
A libcxx/test/libcxx/containers/sequences/list/list.modifiers/bool-conversion.pass.cpp
Log Message:
-----------
[libcxx] Add LWG4135: The helper lambda of std::erase for list should specify return type as bool (#128358)
Fixes https://github.com/llvm/llvm-project/issues/118355
Commit: be28365ca78ed305c66b824075323e839f042e4a
https://github.com/llvm/llvm-project/commit/be28365ca78ed305c66b824075323e839f042e4a
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/if-conversion.ll
Log Message:
-----------
[LV] Generate check lines for if-conversion.ll
The limited check lines make it difficult to reason about test changes
in https://github.com/llvm/llvm-project/pull/128375.
Commit: ca5bb238d05e2ab1e0d6a705f2366beec5ab047f
https://github.com/llvm/llvm-project/commit/ca5bb238d05e2ab1e0d6a705f2366beec5ab047f
Author: Tai Ly <tai.ly at arm.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.h
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeDepthwise.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeTransposeConv.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/profile_all_unsupported.mlir
M mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-depthwise.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-transpose-conv.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/tosa-reduce-transposes.mlir
Log Message:
-----------
[mlir][tosa] Change zero points of convolution ops to required inputs (#127679)
This patch changes the input_zp and weight_zp for convolution operators
to be required inputs
in order to align with the TOSA Spec 1.0.
Convolution operators affected are:
CONV2D, CONV3D, DEPTHWISE_CONV2D, and TRANSPOSE_CONV2D.
Signed-off-by: Tai Ly <tai.ly at arm.com>
Commit: 177ede2122b8a913b1a86d86cb3acf17cdd93a86
https://github.com/llvm/llvm-project/commit/177ede2122b8a913b1a86d86cb3acf17cdd93a86
Author: Tai Ly <tai.ly at arm.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaFolders.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/constant-op-fold.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
Log Message:
-----------
[mlir][tosa] Rename ReduceProd to ReduceProduct (#128751)
This patch renames TOSA ReduceProd operator to ReduceProduct to align
with the TOSA Spec 1.0
Signed-off-by: Tai Ly <tai.ly at arm.com>
Commit: 579ead1a69f2ba1cb5614f6d942b14bc5e6b8dec
https://github.com/llvm/llvm-project/commit/579ead1a69f2ba1cb5614f6d942b14bc5e6b8dec
Author: Michael Jones <michaelrj at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl
A utils/bazel/llvm-project-overlay/libc/test/src/stdbit/BUILD.bazel
Log Message:
-----------
[libc][bazel] Add targets for stdbit functions (#128934)
Adds targets for the stdbit functions. Since the names follow a strict
pattern, this is done via list comprehensions. I don't want to handwrite
all 50.
Commit: 7b6abd827ff25eacdea14a09d1b74e0eeece854a
https://github.com/llvm/llvm-project/commit/7b6abd827ff25eacdea14a09d1b74e0eeece854a
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/if-conversion.ll
Log Message:
-----------
[LV] Remove stray check lines after be28365ca78.
Commit: 364b97f23b4de7732179023220ff23a24bec4919
https://github.com/llvm/llvm-project/commit/364b97f23b4de7732179023220ff23a24bec4919
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
A llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir
A llvm/test/CodeGen/AMDGPU/spillv16.ll
A llvm/test/CodeGen/AMDGPU/spillv16.mir
Log Message:
-----------
[AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (#128060)
Enables 16-bit values to be spilled to scratch.
Note, the memory instructions used are defined as reading and writing
VGPR_32, but do not clobber the unspecified 16-bits of those registers,
and so spills and reloads of lo and hi halves of the registers work.
Commit: 7f482aa848c5f136d2b32431f91f88492c78c709
https://github.com/llvm/llvm-project/commit/7f482aa848c5f136d2b32431f91f88492c78c709
Author: Qiongsi Wu <qiongsiwu at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/include/clang/Tooling/DependencyScanning/ModuleDepCollector.h
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
A clang/test/ClangScanDeps/modules-debug-dir.c
Log Message:
-----------
[clang modules] Setting `DebugCompilationDir` when it is safe to ignore current working directory (#128446)
This PR explicitly sets `DebugCompilationDir` to the system's root
directory if it is safe to ignore the current working directory.
This fixes a problem where a PCM file's embedded debug information can
lead to compilation failure. The compiler may have decided it is indeed
safe to ignore the current working directory. In this case, the PCM
file's content is functionally correct regardless of the current working
directory because no inputs use relative paths (see
https://github.com/llvm/llvm-project/pull/124786). However, a PCM may
contain debug info. If debug info is requested, the compiler uses the
current working directory value to set `DW_AT_comp_dir`. This may lead
to the following situation:
1. Two different compilations need the same PCM file.
2. The PCM file is compiled assuming a working directory, which is
embedded in the debug info, but otherwise has no effect.
3. The second compilation assumes a different working directory, and
expects an identically-sized pcm file. However, it cannot find such a
PCM, because the existing PCM file has been compiled assuming a
different `DW_AT_comp_dir `, which is embedded in the debug info.
This PR resets the `DebugCompilationDir` if it is functionally safe to
ignore the working directory so the above situation is avoided, since
all debug information will share the same working directory.
rdar://145249881
Commit: 418a9872851ef5342b29baa36dd672129f129953
https://github.com/llvm/llvm-project/commit/418a9872851ef5342b29baa36dd672129f129953
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/buildvector-reused-with-bv-subvector.ll
Log Message:
-----------
[SLP]Do not use node, if it is a subvector or buildvector node
If the buildvector has some matches with another node, which is
a subvector of another buildvector node, need to check for this and
cancel matching to avoid incorrect ordering of the nodes.
Fixes #128770
Commit: eb84c1181eee5c0aad3981f629a8ca9d9d637d1d
https://github.com/llvm/llvm-project/commit/eb84c1181eee5c0aad3981f629a8ca9d9d637d1d
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M flang/module/cudadevice.f90
Log Message:
-----------
[flang][cuda] Add more math intrinsic interfaces in cudadevice (#128931)
Commit: 7371f691b97986fd3f32d8618131ca40788c7b8b
https://github.com/llvm/llvm-project/commit/7371f691b97986fd3f32d8618131ca40788c7b8b
Author: Benoit Jacob <jacob.benoit.1 at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm-interface.mlir
Log Message:
-----------
[MLIR][Vector]: Generalize conversion of `vector.insert` to LLVM in line with `vector.extract` (#128915)
This is doing the same as
https://github.com/llvm/llvm-project/pull/117731 did for
`vector.extract`, but for `vector.insert`.
It is a bit more complicated as the insertion destination may itself
need to be extracted.
As the test shows, this fixes two previously unsupported cases:
- Dynamic indices
- 0-D vectors.
---------
Signed-off-by: Benoit Jacob <jacob.benoit.1 at gmail.com>
Commit: 42526d240cc953963ea48bae0b4c2ab548e9d897
https://github.com/llvm/llvm-project/commit/42526d240cc953963ea48bae0b4c2ab548e9d897
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/include/mlir/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.h
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUDialect.h
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.h
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.td
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/CMakeLists.txt
A mlir/lib/Dialect/AMDGPU/Transforms/ResolveStridedMetadata.cpp
M mlir/test/Conversion/AMDGPUToROCDL/amdgpu-to-rocdl.mlir
A mlir/test/Dialect/AMDGPU/amdgpu-resolve-strided-metadata.mlir
M mlir/test/Dialect/AMDGPU/invalid.mlir
M mlir/test/Dialect/AMDGPU/ops.mlir
Log Message:
-----------
[mlir][AMDGPU] Plumb address space 7 through MLIR, add address_space attr. (#125594)
This commit adds support for casting memrefs into fat raw buffer
pointers to the AMDGPU dialect.
Fat raw buffer pointers - or, in LLVM terms, ptr addrspcae(7), allow
encapsulating a buffer descriptor (as produced by the make.buffer.rsrc
intrinsic or provided from some API) into a pointer that supports
ordinary pointer operations like load or store. This allows people to
take advantage of the additional semantics that buffer_load and similar
instructions provide without forcing the use of entirely separate
amdgpu.raw_buffer_* operations.
Operations on fat raw buffer pointers are translated to the
corresponding LLVM intrinsics by the backend.
This commit also goes and and defines a #amdgpu.address_space<>
attribute so that AMDGPU-specific memory spaces can be represented. Only
#amdgpu.address_space<fat_raw_buffer> will work correctly with the
memref dialect, but the other possible address spaces are included for
completeness.
---------
Co-authored-by: Jakub Kuderski <kubakuderski at gmail.com>
Co-authored-by: Prashant Kumar <pk5561 at gmail.com>
Commit: 469757efafebdd5772d993fca4dc0dfa7cbda17c
https://github.com/llvm/llvm-project/commit/469757efafebdd5772d993fca4dc0dfa7cbda17c
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
A llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
A llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-mem-transfer.ll
Log Message:
-----------
[AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (#126621)
Since LowerBufferFatPointers runs before PreISelIntrinsicLowering, which
normally handles unsupported memcpy()s,, and since you can't have a
`noalias {ptr addrspace(8), i32}` becasue it crashes later passes,
manually expand memcpy()s involving buffer fat pointers to loops.
Additionally, though they're unlikely to be used, this commit adds
support for memset().
This commit doesn't implement writing direct-to-LDS loads as the
intrinsics, but leaves the option in the future.
Commit: 147d9d6915cd64d9f4b8c752a6f149a7ffb29e3b
https://github.com/llvm/llvm-project/commit/147d9d6915cd64d9f4b8c752a6f149a7ffb29e3b
Author: Sam Clegg <sbc at chromium.org>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/test/CodeGen/WebAssembly/lower-em-ehsjlj-options.ll
M llvm/test/CodeGen/WebAssembly/lower-em-sjlj.ll
M llvm/test/CodeGen/WebAssembly/lower-wasm-ehsjlj.ll
Log Message:
-----------
[WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (#128564)
This change effectively reverts 296ccef
(https://reviews.llvm.org/D77192)
Most of these symbols are just normal C symbols that get imported from
wither libcompiler-rt or from emscripten's JS library code. In most
cases it should not be necessary to give them explicit import names.
The advantage of doing this is that we can wasm-ld can/will fail with a
useful error message when these symbols are missing. As opposed to today
where it will simply import them and defer errors until later (when they
are less specific).
Commit: 02128342d2818e5a65846fec4179ed5344045102
https://github.com/llvm/llvm-project/commit/02128342d2818e5a65846fec4179ed5344045102
Author: Daniel Thornburgh <dthorn at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AMDGPU/shl64_reduce.ll
Log Message:
-----------
Revert "DAG: Preserve range metadata when load is narrowed" (#128948)
Reverts llvm/llvm-project#128144
Breaks clang prod x64 build (seen in Fuchsia toolchain)
Commit: 39bab1de33333ee3c62b586c4e8d26f8c443bc60
https://github.com/llvm/llvm-project/commit/39bab1de33333ee3c62b586c4e8d26f8c443bc60
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/reduction-with-removed-extracts.ll
Log Message:
-----------
[SLP]Check if the operand for removal is the reduction operand, awaiting for the reduction
If the operand of the instruction-to-be-removed is a reduction value,
which is not reduced yet, and, thus, it has no users, it may be removed
during operands analysis.
Fixes #128736
Commit: 8fb88f568011fb916cda9d7927ac97c6751a8b89
https://github.com/llvm/llvm-project/commit/8fb88f568011fb916cda9d7927ac97c6751a8b89
Author: Michael Spencer <bigcheesegs at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Basic/Module.h
M clang/include/clang/Lex/ModuleMap.h
A clang/include/clang/Lex/ModuleMapFile.h
M clang/lib/Lex/CMakeLists.txt
M clang/lib/Lex/ModuleMap.cpp
A clang/lib/Lex/ModuleMapFile.cpp
M clang/test/Modules/Inputs/export_as_test.modulemap
M clang/test/Modules/diagnostics.modulemap
M clang/test/Modules/export_as_test.c
Log Message:
-----------
[clang][modules] Separate parsing of modulemaps (#119740)
This separates out parsing of modulemaps from updating the
`clang::ModuleMap` information.
Currently this has no effect other than slightly changing diagnostics.
Upcoming changes will use this to allow searching for modules without
fully processing modulemaps.
This creates a new `modulemap` namespace because there are too many
things called ModuleMap* right now that mean different things. I'd like
to clean this up, but I'm not sure yet what I want to call everything.
This also drops the `SourceLocation` from `moduleMapFileRead`. This is
never used in tree, and in future patches I plan to make the modulemap
parser use a different `SourceManager` so that we can share modulemap
parsing between `CompilerInstance`s. This will make the `SourceLocation`
meaningless.
Commit: d584d1f188553b6cb417beb903f58d763c265380
https://github.com/llvm/llvm-project/commit/d584d1f188553b6cb417beb903f58d763c265380
Author: Bruno Cardoso Lopes <bcardosolopes at users.noreply.github.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/include/mlir/Target/LLVMIR/LLVMImportInterface.h
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
M mlir/test/Target/LLVMIR/Import/import-failure.ll
A mlir/test/Target/LLVMIR/Import/intrinsic-unregistered.ll
Log Message:
-----------
[MLIR][LLVMIR] Import unregistered intrinsics via llvm.intrinsic_call (#128626)
Currently, the llvm importer can only cover intrinsics that have a first
class representation in an MLIR dialect (arm-neon, etc). This PR
introduces a fallback mechanism that allow "unregistered" intrinsics to
be imported by using the generic `llvm.intrinsic_call` operation. This
is useful in several ways:
1. Allows round-trip the LLVM dialect output lowered from other dialects
(example: ClangIR)
2. Enables MLIR-linking tools to operate on imported LLVM IR without
requiring to add new operations to dozen of different targets (cc
@xlauko @smeenai).
If multiple dialects implement this interface hook, the last one to
register is the one converting all unregistered intrinsics.
---------
Co-authored-by: Tobias Gysi <tobias.gysi at nextsilicon.com>
Commit: 1559a65efaf327f9c72e14d4bb1834f076e7fc20
https://github.com/llvm/llvm-project/commit/1559a65efaf327f9c72e14d4bb1834f076e7fc20
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
R llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
R llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-mem-transfer.ll
Log Message:
-----------
Revert "[AMDGPU] Handle memcpy()-like ops in LowerBufferFatPointers (#126621)"
This reverts commit 469757efafebdd5772d993fca4dc0dfa7cbda17c.
Multiple buildbot failures have been reported:
https://github.com/llvm/llvm-project/pull/126621
Commit: ff80bdcf734909ac837e88cafdfc1b5d66845a98
https://github.com/llvm/llvm-project/commit/ff80bdcf734909ac837e88cafdfc1b5d66845a98
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlseg-vsseg.s
Log Message:
-----------
[RISCV] Adding missing P600 sched model test for RVV segmented loads/stores
This is the P600 counterpart of
`test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s`.
Commit: effd7f04b678b4be1a77ae1f12f2b64469c8fa04
https://github.com/llvm/llvm-project/commit/effd7f04b678b4be1a77ae1f12f2b64469c8fa04
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Lex/BUILD.gn
Log Message:
-----------
[gn build] Port 8fb88f568011
Commit: f3b4d94f35eee5e1eb1ad7359a31ab0319bdf56e
https://github.com/llvm/llvm-project/commit/f3b4d94f35eee5e1eb1ad7359a31ab0319bdf56e
Author: David CARLIER <devnexen at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
Log Message:
-----------
[compiler-rt][rtsan] truncate/ftruncate interception. (#128904)
Commit: 26ac7429d1d6aed080430e8f5d890531b1054f2d
https://github.com/llvm/llvm-project/commit/26ac7429d1d6aed080430e8f5d890531b1054f2d
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
Log Message:
-----------
[memprof] std::move matchings (NFC) (#128933)
We do not use Matchings after we call try_emplace, so we can just
std::move Matchings.
Commit: 524711c344b413d5c25d4bed1175d58670ab1720
https://github.com/llvm/llvm-project/commit/524711c344b413d5c25d4bed1175d58670ab1720
Author: Michael Jones <michaelrj at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/stdlib/BUILD.bazel
Log Message:
-----------
[libc][bazel] Add targets for strfrom<float> (#128956)
Add targets and tests for strfromf, strfromd and strfroml.
No idea why the standard committee decided that the long double function
should be "strfroml" instead of "strfromld" which would match "strtold"
and leave them space to add string from integer functions in future.
Commit: 829e2a55261890e15102d978f714001a2d1acf85
https://github.com/llvm/llvm-project/commit/829e2a55261890e15102d978f714001a2d1acf85
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M libc/docs/dev/header_generation.rst
R libc/utils/hdrgen/enumeration.py
R libc/utils/hdrgen/function.py
R libc/utils/hdrgen/gpu_headers.py
A libc/utils/hdrgen/hdrgen/__init__.py
A libc/utils/hdrgen/hdrgen/enumeration.py
A libc/utils/hdrgen/hdrgen/function.py
A libc/utils/hdrgen/hdrgen/gpu_headers.py
A libc/utils/hdrgen/hdrgen/header.py
A libc/utils/hdrgen/hdrgen/macro.py
A libc/utils/hdrgen/hdrgen/main.py
A libc/utils/hdrgen/hdrgen/object.py
A libc/utils/hdrgen/hdrgen/type.py
A libc/utils/hdrgen/hdrgen/yaml_functions_sorted.py
A libc/utils/hdrgen/hdrgen/yaml_to_classes.py
R libc/utils/hdrgen/header.py
R libc/utils/hdrgen/macro.py
M libc/utils/hdrgen/main.py
R libc/utils/hdrgen/object.py
R libc/utils/hdrgen/type.py
R libc/utils/hdrgen/yaml_functions_sorted.py
M libc/utils/hdrgen/yaml_to_classes.py
Log Message:
-----------
[libc][hdrgen] Allow to treat hdrgen Python code as a Python module. (#128955)
Move the hdrgen code under a subdirectory to treat it as a Python
module.
This mimics the structure used by llvm/utils/lit and
llvm/utils/mlgo-utils and simplifies integration of hdrgen to the build
system which rely on Python modules. In addition to that, it clarifies
which imports are coming from the hdrgen-specific helpers (e.g. "from
type import ..." becomes "from hdrgen.type import ...".
Leave the entrypoints (top-level main.py and yaml_to_classes.py) as-is:
they can keep being referred by the CMake build system w/o any changes.
Commit: d708bfb3c0be7ffdba384eff15cd329863568453
https://github.com/llvm/llvm-project/commit/d708bfb3c0be7ffdba384eff15cd329863568453
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
A llvm/test/CodeGen/AMDGPU/i1-divergent-phi-fix-sgpr-copies-assert.mir
Log Message:
-----------
AMDGPU: Fix si-fix-sgpr-copies asserting on VReg_1 phi (#128903)
Commit: 2761d4ca828a557d0bdd20259d60b486d360d998
https://github.com/llvm/llvm-project/commit/2761d4ca828a557d0bdd20259d60b486d360d998
Author: Bruno Cardoso Lopes <bruno.cardoso at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/include/mlir/Target/LLVMIR/LLVMImportInterface.h
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
M mlir/test/Target/LLVMIR/Import/import-failure.ll
R mlir/test/Target/LLVMIR/Import/intrinsic-unregistered.ll
Log Message:
-----------
Revert "[MLIR][LLVMIR] Import unregistered intrinsics via llvm.intrinsic_call" (#128973)
Reverts llvm/llvm-project#128626
Looks like the static definition broke some bots!
Co-authored-by: Bruno Cardoso Lopes <bcardosolopes at users.noreply.github.com>
Commit: f409340cc217c55c3960a375054a17b2bc927e53
https://github.com/llvm/llvm-project/commit/f409340cc217c55c3960a375054a17b2bc927e53
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Return an llvm::Error instead of calling exit directly (NFC) (#128951)
Return an `llvm::Error` from `LaunchRunInTerminalTarget` instead of
calling `exit()` directly.
Commit: 4be4133a9f5a305cc9cd689f0a72b7623a31d0c5
https://github.com/llvm/llvm-project/commit/4be4133a9f5a305cc9cd689f0a72b7623a31d0c5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/test/CodeGen/AMDGPU/dag-divergence.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/si-fold-operands-commute-same-operands-assert.mir
Log Message:
-----------
AMDGPU: Do not try to commute instruction with same input register (#127562)
There's little point to trying to commute an instruction if the
two operands are already the same.
This avoids an assertion in a future patch, but this likely isn't the
correct fix. The worklist management in SIFoldOperands is dodgy, and
we should probably fix it to work like PeepholeOpt (i.e. stop looking
at use lists, and fold from users). This is an extension of the already
handled special case which it's trying to avoid folding an instruction
which is already being folded.
Commit: a3165398db0736588daedb07650195502592e567
https://github.com/llvm/llvm-project/commit/a3165398db0736588daedb07650195502592e567
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
M llvm/test/CodeGen/AMDGPU/bug-cselect-b64.ll
M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir
M llvm/test/CodeGen/AMDGPU/fold-sgpr-multi-imm.mir
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
Log Message:
-----------
AMDGPU: Fix overly conservative immediate operand check (#127563)
The real legality check is peformed later anyway, so this was
unnecessarily blocking immediate folds in handled cases.
This also stops folding s_fmac_f32 to s_fmamk_f32 in a few tests,
but that seems better. The globalisel changes look suspicious,
it may be mishandling constants for VOP3P instructions.
Commit: c8f70d7286db0eb54b001a6621a863b96c006e45
https://github.com/llvm/llvm-project/commit/c8f70d7286db0eb54b001a6621a863b96c006e45
Author: Alex Voicu <alexandru.voicu at amd.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGExprAgg.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/test/CodeGen/partial-reinitialization2.c
A clang/test/CodeGenCXX/sret_cast_with_nonzero_alloca_as.cpp
A clang/test/OpenMP/amdgcn_sret_ctor.cpp
Log Message:
-----------
[clang][CodeGen] Additional fixes for #114062 (#128166)
This addresses two issues introduced by moving indirect args into an
explicit AS (please see
<https://github.com/llvm/llvm-project/pull/114062#issuecomment-2659829790>
and
<https://github.com/llvm/llvm-project/pull/114062#issuecomment-2661158477>):
1. Unconditionally stripping casts from a pre-allocated return slot was
incorrect / insufficient (this is illustrated by the
`amdgcn_sret_ctor.cpp` test);
2. Putting compiler manufactured sret args in a non default AS can lead
to a C-cast (surprisingly) requiring an AS cast (this is illustrated by
the `sret_cast_with_nonzero_alloca_as.cpp test).
The way we handle (2), by subverting CK_BitCast emission iff a sret arg
is involved, is quite naff, but I couldn't think of any other way to use
a non default indirect AS and make this case work (hopefully this is a
failure of imagination on my part).
Commit: 2d585ccecc45d84483ce8a7e26dbf455e9ba3798
https://github.com/llvm/llvm-project/commit/2d585ccecc45d84483ce8a7e26dbf455e9ba3798
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/lib/Format/FormatToken.h
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Fix a bug that changes keyword `or` to an identifier (#128410)
Fixes #105482
Commit: d29a1be94bc391205fa361f57f7fbc83c1e6f55a
https://github.com/llvm/llvm-project/commit/d29a1be94bc391205fa361f57f7fbc83c1e6f55a
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Don't break before *const (#128817)
Fixes #28919
Commit: a2fac3f87be563cb588040c385f48b71cddf31e9
https://github.com/llvm/llvm-project/commit/a2fac3f87be563cb588040c385f48b71cddf31e9
Author: Alex Voicu <alexandru.voicu at amd.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGExprAgg.cpp
Log Message:
-----------
[NFC] Fix Sanitizer breakage introduced in #128166 (#128990)
Remove accidental leftover unused variable.
Commit: 12c7908f67924809025c6bf669881c90322dbd57
https://github.com/llvm/llvm-project/commit/12c7908f67924809025c6bf669881c90322dbd57
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/MachOBuilder.h
Log Message:
-----------
[ORC] De-duplicate some logic for handling MachO::dylib-based load commands.
All such commands share a common struct layout, and we'll be introducing
another soon (LC_LOAD_WEAK_DYLIB). To avoid redundant specializations this
commit moves the logic for these commands into a common base class.
Commit: 2e6d9af7e2f68ee72bf6de91c0ca2a9f9b1fc514
https://github.com/llvm/llvm-project/commit/2e6d9af7e2f68ee72bf6de91c0ca2a9f9b1fc514
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/MachOBuilder.h
M llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
Log Message:
-----------
[ORC] Support adding LC_LOAD_WEAK_DYLIB commands to MachO JITDylib headers.
MachOPlatform synthesizes Mach headers for JITDylibs (see ef314d39b92). This
commit adds support for adding LC_LOAD_WEAK_DYLIB commands to these synthesized
headers (LC_LOAD_DYLIB was already supported previously).
Commit: 20cea4d410df8f92a8dc639c1747c238e1e3e65b
https://github.com/llvm/llvm-project/commit/20cea4d410df8f92a8dc639c1747c238e1e3e65b
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/GetDylibInterface.h
M llvm/lib/ExecutionEngine/Orc/GetDylibInterface.cpp
Log Message:
-----------
[ORC] Sink include into implementation file.
TapiUniversal.h is only needed as an implementation detail.
Commit: 4c9f6a737ff22c8b8d0784e70677d7ec677c9b49
https://github.com/llvm/llvm-project/commit/4c9f6a737ff22c8b8d0784e70677d7ec677c9b49
Author: JaydeepChauhan14 <chauhan.jaydeep.ashwinbhai at intel.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
M llvm/test/CodeGen/X86/llvm.acos.ll
M llvm/test/CodeGen/X86/llvm.asin.ll
M llvm/test/CodeGen/X86/llvm.atan.ll
M llvm/test/CodeGen/X86/llvm.atan2.ll
M llvm/test/CodeGen/X86/llvm.cos.ll
M llvm/test/CodeGen/X86/llvm.cosh.ll
M llvm/test/CodeGen/X86/llvm.sin.ll
M llvm/test/CodeGen/X86/llvm.sinh.ll
M llvm/test/CodeGen/X86/llvm.tan.ll
M llvm/test/CodeGen/X86/llvm.tanh.ll
Log Message:
-----------
[X86][GlobalISel] Enable Trigonometric functions with libcall mapping (#126931)
Commit: 354eb88285c0d803b0674a3b2961b4109905383a
https://github.com/llvm/llvm-project/commit/354eb88285c0d803b0674a3b2961b4109905383a
Author: Dave Lee <davelee.com at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M lldb/examples/python/fzf_history.py
Log Message:
-----------
[lldb] Also show session history in fzf_history (#128986)
lldb's history log file is written to at the end of a debugging session.
As a result, the log does not contain commands run during the current
session.
This extends the `fzf_history` to include the output of `session
history`.
Commit: 363b05944f9212511ee6811d0eb1af841c177226
https://github.com/llvm/llvm-project/commit/363b05944f9212511ee6811d0eb1af841c177226
Author: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/CodeGen/ISDOpcodes.h
Log Message:
-----------
LangRef: Clarify llvm.minnum and llvm.maxnum about sNaN and signed zero (#112852)
The documents claims that it ignores sNaN, while in the current code it
may be different.
- as the finally callback, it use libc call fmin(3)/fmax(3). while C23
clarifies that fmin(3)/fmax(3) should return NaN for sNaN vs NUM.
- on some architectures, such as aarch64, it converts to `fmaxnm`, which
returns qNaN for sNaN vs NUM.
- on RISC-V (SPEC 2019+), it converts to `fmax`, which returns NUM for
sNaN vs NUM.
Since we have introduced llvm.minimumnum and llvm.maximumnum, which
follow IEEE 754-2019's minimumNumber/maximumNumber.
So, it's time for us to clarify llvm.minnum and llvm.maxnum. Since the
final fallback of llvm.minnum and llvm.maxnum is
fmin(3)/fmax(3), so that it is reasonable to follow the behaviors of
fmin(3)/fmax(3).
Although C23 clarified the behavior about sNaN and +0.0/-0.0:
(NUM or NaN) vs sNaN -> qNaN
+0.0 vs -0.0 -> either one of +0.0/-0.0
It is the same the IEEE754-2008's maxNUM and minNUM.
Not all implementation work as expected.
Since some architectures such as aarch64/MIPSr6/LoongArch, have
instructions that implements +0.0>-0.0.
So Let's define llvm.minnum and llvm.maxnum to IEEE754-2008 with
+0.0>-0.0.
The architectures without such instructions can implements `NSZ` flavor
to speed up,
and the frontend, such as clang, can call them with `nsz` attribute.
Commit: aef16edb26b2e255b6c2beda8f03a70505ffb22a
https://github.com/llvm/llvm-project/commit/aef16edb26b2e255b6c2beda8f03a70505ffb22a
Author: wheatfox <wheatfox17 at icloud.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaProfileCompliance.h
Log Message:
-----------
[mlir][Tosa] Add unreachable case for bad Extension type in TosaProfileCompliance (#128889)
add `llvm_unreachable` at the end of `getCooperativeProfiles` to
eliminate compiler warning of "control reaches end of non-void function"
Commit: eb1c3ace39644dbe24777a00ba4d879d23c7bb46
https://github.com/llvm/llvm-project/commit/eb1c3ace39644dbe24777a00ba4d879d23c7bb46
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Passes/PassBuilderPipelines.cpp
A llvm/test/Transforms/PGOProfile/ctx-instrumentation-optin.ll
Log Message:
-----------
[ctxprof] Override type of instrumentation if `-profile-context-root` is specified (#128940)
This patch makes it easy to enable ctxprof instrumentation for targets where the build has a bunch of defaults for instrumented PGO that we want to inherit for ctxprof.
This is switching experimental defaults: we'll eventually enable ctxprof instrumentation through `PGOOpt` but that type is currently quite entangled and, for the time being, no point adding to that.
Commit: 5066d7b60186fe0d557223493a17c3aa9a06f58f
https://github.com/llvm/llvm-project/commit/5066d7b60186fe0d557223493a17c3aa9a06f58f
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
A llvm/lib/Target/RISCV/RISCVInstrInfoXqccmp.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
A llvm/test/MC/RISCV/rv32xqccmp-invalid.s
A llvm/test/MC/RISCV/rv32xqccmp-valid.s
A llvm/test/MC/RISCV/rv64e-xqccmp-valid.s
A llvm/test/MC/RISCV/rv64xqccmp-invalid.s
A llvm/test/MC/RISCV/rv64xqccmp-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Xqccmp 0.1 Assembly Support (#128731)
Xqccmp is a new spec by Qualcomm that makes a vendor-specific effort to
solve the push/pop + frame pointers issue. Broadly, it takes the Zcmp
instructions and reverse the order they push/pop registers in, which
ends up matching the frame pointer convention.
This extension adds a new instruction not present in Zcmp,
`qc.cm.pushfp`, which will set `fp` to the incoming `sp` value after it
has pushed the registers.
This change duplicates the Zcmp implementation, with minor changes to
mnemonics (for the `qc.` prefix), predicates, and the addition of
`qc.cm.pushfp`. There is also new logic to prevent combining Xqccmp and
Zcmp. Xqccmp is kept separate to Xqci for decoding/encoding etc, as the
specs are separate today.
Specification:
https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.1.0
Commit: 110b77f32859f39d253623153a37671f5601de65
https://github.com/llvm/llvm-project/commit/110b77f32859f39d253623153a37671f5601de65
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/test/Lower/CUDA/cuda-device-proc.cuf
Log Message:
-----------
[flang][cuda] Handle floats in atomiccas (#128970)
Commit: 556eb8244201a81fff7b246561a677a782b69fa0
https://github.com/llvm/llvm-project/commit/556eb8244201a81fff7b246561a677a782b69fa0
Author: David Olsen <dolsen at nvidia.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/test/CIR/IR/func.cir
M clang/test/CIR/IR/global.cir
M clang/test/CIR/func-simple.cpp
M clang/test/CIR/global-var-simple.cpp
Log Message:
-----------
[CIR] Function type return type improvements (#128787)
When a C or C++ function has a return type of `void`, the function type
is now represented in MLIR as having no return type rather than having a
return type of `!cir.void`. This avoids breaking MLIR invariants that
require the number of return types and the number of return values to
match.
Change the assembly format for `cir::FuncType` from having a leading
return type to having a trailing return type. In other words, change
```
!cir.func<!returnType (!argTypes)>
```
to
```
!cir.func<(!argTypes) -> !returnType)>
```
Unless the function returns `void`, in which case change
```
!cir.func<!cir.void (!argTypes)>
```
to
```
!cir.func<(!argTypes)>
```
Commit: 5f6a3e63a31aaebc620a18c47bc5590f6f705c98
https://github.com/llvm/llvm-project/commit/5f6a3e63a31aaebc620a18c47bc5590f6f705c98
Author: David CARLIER <devnexen at gmail.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_syscalls.inc
A compiler-rt/test/sanitizer_common/TestCases/Linux/copy_file_range.c
Log Message:
-----------
[compiler-rt][sanitizer_common] copy_file_range syscall interception. (#125816)
Commit: 5d404d75cf513f9926209b8dd515083226dae88f
https://github.com/llvm/llvm-project/commit/5d404d75cf513f9926209b8dd515083226dae88f
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx2-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/mmx-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/avx-intrinsics-i386.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/avx2-intrinsics-i386.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/mmx-intrinsics.ll
Log Message:
-----------
[msan] Generalize handlePairwiseShadowOrIntrinsic, and handle x86 pairwise add/sub (#127567)
x86 pairwise add and sub are currently handled by applying the pairwise add intrinsic to the shadow (https://github.com/llvm/llvm-project/pull/124835), due to the lack of an x86 pairwise OR intrinsic. handlePairwiseShadowOrIntrinsic was added (https://github.com/llvm/llvm-project/pull/126008) to handle Arm
pairwise add, but assumes that the intrinsic operates on each pair of elements as defined by the LLVM type. In contrast, x86 pairwise add/sub may sometimes have e.g., <1 x i64> as a parameter but actually be operating on <2 x i32>.
This patch generalizes handlePairwiseShadowOrIntrinsic, to allow reinterpreting the parameters to be a vector of specified element size, and then uses this function to handle x86 pairwise add/sub.
Commit: 88ff6070a5211e0eebe9b614efbeae8082866d1a
https://github.com/llvm/llvm-project/commit/88ff6070a5211e0eebe9b614efbeae8082866d1a
Author: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/include/llvm/ADT/APFloat.h
M llvm/unittests/ADT/APFloatTest.cpp
Log Message:
-----------
APFloat: Fix maxnum and minnum with sNaN (#112854)
See: https://github.com/llvm/llvm-project/pull/112852
Fixes: https://github.com/llvm/llvm-project/issues/111991
We have reclarify llvm.maxnum and llvm.minnum to follow IEEE-754 2008's
maxNum and minNum with +0.0>-0.0.
So let's make APFloat::maxnum and APFloat::minnum to follow it, too.
Commit: 51a15d96fdb9818bf4e5439d4b551fc0950d3c69
https://github.com/llvm/llvm-project/commit/51a15d96fdb9818bf4e5439d4b551fc0950d3c69
Author: Fangrui Song <i at maskray.me>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
Log Message:
-----------
[RISCV] Simplify createRISCVELFStreamer registration
Commit: 50b508cc7b2d95f92896df73f49063b5aafec43d
https://github.com/llvm/llvm-project/commit/50b508cc7b2d95f92896df73f49063b5aafec43d
Author: Frederik Harwath <frederik.harwath at amd.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
A llvm/test/MachineVerifier/AMDGPU/verifier-sdwa-selection.mir
Log Message:
-----------
[AMDGPU] Verify SdwaSel value range (#128898)
Make the MachineVerifier check that the value provided for an SDWA selection is a
valid value for the SdwaSel enum.
Commit: 7521207e415b19b2924930ac95c2fcf07d56f2f2
https://github.com/llvm/llvm-project/commit/7521207e415b19b2924930ac95c2fcf07d56f2f2
Author: David CARLIER <devnexen at gmail.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M compiler-rt/test/sanitizer_common/TestCases/Linux/copy_file_range.c
Log Message:
-----------
[compiler-rt][sanitizer_common] fix copy_file_range test. (#129010)
Passing Large File Support.
Address #125816
Commit: dc74d2f8316eca1c2c07b36ca5998e9b15b5d03b
https://github.com/llvm/llvm-project/commit/dc74d2f8316eca1c2c07b36ca5998e9b15b5d03b
Author: lorenzo chelini <l.chelini at icloud.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/MLProgram/Transforms/Passes.h
M mlir/include/mlir/Dialect/MLProgram/Transforms/Passes.td
M mlir/include/mlir/Dialect/Shape/Transforms/Passes.h
M mlir/include/mlir/Dialect/Shape/Transforms/Passes.td
M mlir/lib/Dialect/MLProgram/Transforms/PipelineGlobalOps.cpp
M mlir/lib/Dialect/Shape/Transforms/OutlineShapeComputation.cpp
M mlir/lib/Dialect/Shape/Transforms/RemoveShapeConstraints.cpp
M mlir/lib/Dialect/Shape/Transforms/ShapeToShapeLowering.cpp
Log Message:
-----------
[MLIR][NFC] Retire `let constructor` for Shape and MLProgram (#128869)
`let constructor` is legacy (do not use in tree!) since the table gen
backend emits most of the glue logic to build a pass. This PR retires
the td method for Shape and MLProgram
Commit: b38fdfc0f9bef696420a7d02fc1441416a146527
https://github.com/llvm/llvm-project/commit/b38fdfc0f9bef696420a7d02fc1441416a146527
Author: Fangrui Song <i at maskray.me>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.h
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.h
Log Message:
-----------
[AArch64] Simplify ELFStreamer and WinCOFFStreamer
Commit: c11e3dafcf32b9b5af8ac005af6ca8bc07934a65
https://github.com/llvm/llvm-project/commit/c11e3dafcf32b9b5af8ac005af6ca8bc07934a65
Author: Gergely Futo <gergely.futo at hightec-rt.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
Log Message:
-----------
[RISCV] Correct RISCVTTIImpl::getIntImmCostInst for Zba (#128174)
zext.w is only available on RV64.
We also never hoist UINT64_C(0xffffffff) on RV32, since the AND is
deleted by SelectionDAG after type legalization splits it.
Commit: 9a4320adb13b032a035f7c2ca5516202c4036d5c
https://github.com/llvm/llvm-project/commit/9a4320adb13b032a035f7c2ca5516202c4036d5c
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] port 42526d240cc953963ea48bae0b4c2ab548e9d897
include "../" looks wrong
Commit: 78aa61d8b60fc3e9d00236332078d14808abbc57
https://github.com/llvm/llvm-project/commit/78aa61d8b60fc3e9d00236332078d14808abbc57
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Log Message:
-----------
[InstCombine] matchOrConcat - return Value* not Instruction* (#128921)
NFC to make it easier to use builders in the future that might constant fold etc.
Commit: e56a6a2683a82b21d47a5b881fb4eb104c5d8e0a
https://github.com/llvm/llvm-project/commit/e56a6a2683a82b21d47a5b881fb4eb104c5d8e0a
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M clang/test/CodeGen/allow-ubsan-check.c
M clang/test/CodeGenCXX/RelativeVTablesABI/dynamic-cast.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/type-info.cpp
M clang/test/CodeGenOpenCL/amdgcn-buffer-rsrc-type.cl
M clang/test/CodeGenOpenCL/as_type.cl
M llvm/include/llvm/Analysis/CaptureTracking.h
M llvm/include/llvm/IR/InstrTypes.h
M llvm/include/llvm/Support/ModRef.h
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/CaptureTracking.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/test/Transforms/FunctionAttrs/2009-01-02-LocalStores.ll
M llvm/test/Transforms/FunctionAttrs/arg_returned.ll
M llvm/test/Transforms/FunctionAttrs/nocapture.ll
M llvm/test/Transforms/FunctionAttrs/nonnull.ll
M llvm/test/Transforms/FunctionAttrs/noundef.ll
M llvm/test/Transforms/FunctionAttrs/readattrs.ll
M llvm/test/Transforms/FunctionAttrs/stats.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/block_scaling_decompr_8bit.ll
M llvm/test/Transforms/PhaseOrdering/bitcast-store-branch.ll
M llvm/test/Transforms/PhaseOrdering/dce-after-argument-promotion-loads.ll
M llvm/test/Transforms/PhaseOrdering/enable-loop-header-duplication-oz.ll
M llvm/unittests/Analysis/CaptureTrackingTest.cpp
Log Message:
-----------
Reapply [CaptureTracking][FunctionAttrs] Add support for CaptureInfo (#125880) (#128020)
Relative to the previous attempt this includes two fixes:
* Adjust callCapturesBefore() to not skip captures(ret: address,
provenance) arguments, as these will not count as a capture
at the call-site.
* When visiting uses during stack slot optimization, don't skip
the ModRef check for passthru captures. Calls can both modref
and be passthru for captures.
------
This extends CaptureTracking to support inferring non-trivial
CaptureInfos. The focus of this patch is to only support FunctionAttrs,
other users of CaptureTracking will be updated in followups.
The key API changes here are:
* DetermineUseCaptureKind() now returns a UseCaptureInfo where the UseCC
component specifies what is captured at that Use and the ResultCC
component specifies what may be captured via the return value of the
User. Usually only one or the other will be used (corresponding to
previous MAY_CAPTURE or PASSTHROUGH results), but both may be set for
call captures.
* The CaptureTracking::captures() extension point is passed this
UseCaptureInfo as well and then can decide what to do with it by
returning an Action, which is one of: Stop: stop traversal.
ContinueIgnoringReturn: continue traversal but don't follow the
instruction return value. Continue: continue traversal and follow the
instruction return value if it has additional CaptureComponents.
For now, this patch retains the (unsound) special logic for comparison
of null with a dereferenceable pointer. I'd like to switch key code to
take advantage of address/address_is_null before dropping it.
This PR mainly intends to introduce necessary API changes and basic
inference support, there are various possible improvements marked with
TODOs.
Commit: bae41127e2adc90d5c107501a734488134b475af
https://github.com/llvm/llvm-project/commit/bae41127e2adc90d5c107501a734488134b475af
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/PowerPC/v4i32_scalar_to_vector_shuffle.ll
Log Message:
-----------
[DAG] replaceShuffleOfInsert - add support for shuffle_vector(scalar_to_vector(x),y) -> insert_vector_elt(y,x,c) (#127210)
Begin extending replaceShuffleOfInsert to handle other forms of scalar insertion into a vector.
I've limited this to targets that have Custom/Legal ISD::INSERT_VECTOR_ELT handling for now - although we can probably always fold this before LegalOperations.
Commit: eec697baa01d7287bcd631494e79ffea219d1cbf
https://github.com/llvm/llvm-project/commit/eec697baa01d7287bcd631494e79ffea219d1cbf
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineINSERT_SUBVECTOR - use getBROADCAST_LOAD helper in insert_subvector(undef, broadcast(p), hi) -> broadcast(p) fold (#128900)
Commit: 036f5c0f58d362ad5d28400ccbbecdb3aa6d3133
https://github.com/llvm/llvm-project/commit/036f5c0f58d362ad5d28400ccbbecdb3aa6d3133
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M lldb/source/Symbol/LineTable.cpp
Log Message:
-----------
[lldb] Reimplement LineTable::FindLineEntryByAddress on top of lower_bound (#127799)
I *think* this should be equivalent to the original implementation for
all line tables occurring in practice. One difference I'm aware of is
that the original implementation tried to return the first line entry
out of multiple ones for the same address. However, this is not possible
(anymore?) because of the check in LineTable::AppendLineEntryToSequence.
Commit: b021bdbb3997ef6dd13980dc44f24754f15f3652
https://github.com/llvm/llvm-project/commit/b021bdbb3997ef6dd13980dc44f24754f15f3652
Author: David Green <david.green at arm.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/test/Analysis/CostModel/AArch64/aggregates.ll
M llvm/test/Analysis/CostModel/AArch64/arith-fp.ll
M llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
M llvm/test/Analysis/CostModel/AArch64/arith.ll
M llvm/test/Analysis/CostModel/AArch64/bitreverse.ll
M llvm/test/Analysis/CostModel/AArch64/fshl.ll
M llvm/test/Analysis/CostModel/AArch64/fshr.ll
M llvm/test/Analysis/CostModel/AArch64/gep.ll
M llvm/test/Analysis/CostModel/AArch64/min-max.ll
M llvm/test/Analysis/CostModel/AArch64/mul.ll
M llvm/test/Analysis/CostModel/AArch64/reduce-add.ll
M llvm/test/Analysis/CostModel/AArch64/reduce-and.ll
M llvm/test/Analysis/CostModel/AArch64/reduce-fadd.ll
M llvm/test/Analysis/CostModel/AArch64/reduce-minmax.ll
M llvm/test/Analysis/CostModel/AArch64/reduce-or.ll
M llvm/test/Analysis/CostModel/AArch64/reduce-xor.ll
M llvm/test/Analysis/CostModel/AArch64/select.ll
M llvm/test/Analysis/CostModel/AArch64/shuffle-broadcast.ll
M llvm/test/Analysis/CostModel/AArch64/shuffle-reverse.ll
Log Message:
-----------
[AArch64] Add codesize test coverage. NFC
This adds some basic codesize test coverage for a number of instructions. Much of
the results returned are not very accurate yet, especially around larger vector
types but also some basic operations.
Commit: c5cb3f50d2c7adedb35c4cb6d0573094db55b24d
https://github.com/llvm/llvm-project/commit/c5cb3f50d2c7adedb35c4cb6d0573094db55b24d
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
Log Message:
-----------
[mlir][OpenMP] initialize (first)private variables before task exec (#125304)
This still doesn't fix the memory safety issues because the stack
allocations created here for the private variables might go out of
scope.
I will add a more complete lit test later in this patch series.
Commit: fcc88021334d7ee904e891a9b7b29b07afd609d0
https://github.com/llvm/llvm-project/commit/fcc88021334d7ee904e891a9b7b29b07afd609d0
Author: Omar Hossam <moar.ahmed at gmail.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/docs/GetElementPtr.rst
Log Message:
-----------
[Docs] Fix typo in GetElementPtr.rst (#127393)
I couldn't find the verb "indices", and it was actually
a bit confusing for me reading this.
I think this should be "indexes" instead.
Commit: db48d49311ddacf141e78d8b6d07f56cbe29beec
https://github.com/llvm/llvm-project/commit/db48d49311ddacf141e78d8b6d07f56cbe29beec
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
A mlir/test/Target/LLVMIR/openmp-task-privatization.mlir
Log Message:
-----------
[mlir][OpenMP] Pack task private variables into a heap-allocated context struct (#125307)
See RFC:
https://discourse.llvm.org/t/rfc-openmp-supporting-delayed-task-execution-with-firstprivate-variables/83084
The aim here is to ensure that tasks which are not executed for a while
after they are created do not try to reference any data which are now
out of scope. This is done by packing the data referred to by the task
into a heap allocated structure (freed at the end of the task).
I decided to create the task context structure in
OpenMPToLLVMIRTranslation instead of adapting how it is done
CodeExtractor (via OpenMPIRBuilder] because CodeExtractor is (at least
in theory) generic code which could have other unrelated uses.
Commit: f5ee40154507637835b27092ed85184db1a39478
https://github.com/llvm/llvm-project/commit/f5ee40154507637835b27092ed85184db1a39478
Author: Pradeep Kumar <pradeepku at nvidia.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/tcgen05-ld.ll
A llvm/test/CodeGen/NVPTX/tcgen05-st.ll
Log Message:
-----------
[LLVM][NVPTX] Add codegen support for tcgen05.{ld, st} instructions (#126740)
This commit adds support for tcgen05.{ld, st} instructions with lit
tests under tcgen05-ld.ll and tcgen05-st.ll and intrinsics documentation
under NVPTXUsage.rst
Commit: 4d387c4455b78e3334f12f25adf222e67f0be050
https://github.com/llvm/llvm-project/commit/4d387c4455b78e3334f12f25adf222e67f0be050
Author: Prashanth <TheStarOne01 at proton.me>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/fp16-libcalls.ll
M llvm/test/CodeGen/X86/half.ll
Log Message:
-----------
[X86] Add custom operation actions for f16: FABS, FNEG, and FCOPYSIGN (#128877)
This pull request adds custom handling for several floating-point
operations for the `f16` type with respect to
(https://github.com/llvm/llvm-project/issues/126892)..
Fixes #126892
Commit: 3307b0374ac34188b2af189f07ba6910dcf2b6ef
https://github.com/llvm/llvm-project/commit/3307b0374ac34188b2af189f07ba6910dcf2b6ef
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
A llvm/test/Transforms/LoopVectorize/AArch64/sincos.ll
A llvm/test/Transforms/LoopVectorize/sincos.ll
A llvm/test/Transforms/Scalarizer/deinterleave2.ll
R llvm/test/Transforms/Scalarizer/sincos.ll
Log Message:
-----------
[LV] Teach the loop vectorizer llvm.sincos is trivially vectorizable (#128035)
Depends on #123210
Commit: 8b39c897bb1f0865c83961746f0d73990fc4e1c6
https://github.com/llvm/llvm-project/commit/8b39c897bb1f0865c83961746f0d73990fc4e1c6
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
Log Message:
-----------
[Bitcode] Avoid repeated hash lookups (NFC) (#128824)
Commit: f842a00b92e1b275e6482bc686099363568ced3b
https://github.com/llvm/llvm-project/commit/f842a00b92e1b275e6482bc686099363568ced3b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
Log Message:
-----------
[ARM] Avoid repeated hash lookups (NFC) (#128994)
Commit: c54e6fb5c8682266b8c8410ae3c1b82f67fbaf9f
https://github.com/llvm/llvm-project/commit/c54e6fb5c8682266b8c8410ae3c1b82f67fbaf9f
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp
Log Message:
-----------
[AsmPrinter] Avoid repeated hash lookups (NFC) (#128995)
Commit: 42e55925381ae353a4011cf32613d223eb457488
https://github.com/llvm/llvm-project/commit/42e55925381ae353a4011cf32613d223eb457488
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
Log Message:
-----------
[ExecutionEngine] Avoid repeated hash lookups (NFC) (#128997)
Commit: 25ebdfc3dd26b023b8591118492be1fea2574f03
https://github.com/llvm/llvm-project/commit/25ebdfc3dd26b023b8591118492be1fea2574f03
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/IR/DroppedVariableStats.cpp
Log Message:
-----------
[IR] Avoid repeated hash lookups (NFC) (#128998)
Commit: 4913e7bb6934c57e60db076a0331ac45ad0439f6
https://github.com/llvm/llvm-project/commit/4913e7bb6934c57e60db076a0331ac45ad0439f6
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
Log Message:
-----------
[SelectionDAG] Avoid repeated hash lookups (NFC) (#128999)
Commit: 3ce387231a3e9d9642b74152b9d42b364d565352
https://github.com/llvm/llvm-project/commit/3ce387231a3e9d9642b74152b9d42b364d565352
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/Support/DAGDeltaAlgorithm.cpp
Log Message:
-----------
[Support] Avoid repeated hash lookups (NFC) (#129000)
Commit: 0e3ba99ad65f7025d37c857f9b587b767f7709e7
https://github.com/llvm/llvm-project/commit/0e3ba99ad65f7025d37c857f9b587b767f7709e7
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
Log Message:
-----------
[X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadcast(p0) if either load is oneuse (#128857)
This fold is currently limited to cases where the load_subv(p0) has oneuse, but its beneficial if either load has oneuse and will be replaced.
Yet another yak shave for #122671
Commit: c0b5451129bba52e33cd7957d58af897a58d14c6
https://github.com/llvm/llvm-project/commit/c0b5451129bba52e33cd7957d58af897a58d14c6
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M lldb/include/lldb/Host/PipeBase.h
M lldb/include/lldb/Host/posix/PipePosix.h
M lldb/include/lldb/Host/windows/PipeWindows.h
M lldb/source/Host/common/PipeBase.cpp
M lldb/source/Host/common/Socket.cpp
M lldb/source/Host/posix/ConnectionFileDescriptorPosix.cpp
M lldb/source/Host/posix/MainLoopPosix.cpp
M lldb/source/Host/posix/PipePosix.cpp
M lldb/source/Host/windows/PipeWindows.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/source/Target/Process.cpp
M lldb/tools/lldb-server/lldb-gdbserver.cpp
M lldb/unittests/Host/PipeTest.cpp
Log Message:
-----------
[lldb] Assorted improvements to the Pipe class (#128719)
The main motivation for this was the inconsistency in handling of
partial reads/writes between the windows and posix implementations
(windows was returning partial reads, posix was trying to fill the
buffer completely). I settle on the windows implementation, as that's
the more common behavior, and the "eager" version can be implemented on
top of that (in most cases, it isn't necessary, since we're writing just
a single byte).
Since this also required auditing the callers to make sure they're
handling partial reads/writes correctly, I used the opportunity to
modernize the function signatures as a forcing function. They now use
the `Timeout` class (basically an `optional<duration>`) to support both
polls (timeout=0) and blocking (timeout=nullopt) operations in a single
function, and use an `Expected` instead of a by-ref result to return the
number of bytes read/written.
As a drive-by, I also fix a problem with the windows implementation
where we were rounding the timeout value down, which meant that calls
could time out slightly sooner than expected.
Commit: 15e295d30aa356a0ab1d83e477375cf3ef314947
https://github.com/llvm/llvm-project/commit/15e295d30aa356a0ab1d83e477375cf3ef314947
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
M llvm/test/CodeGen/ARM/misched-branch-targets.mir
M llvm/test/CodeGen/PowerPC/pr47155-47156.ll
M llvm/test/CodeGen/X86/fake-use-scheduler.mir
Log Message:
-----------
[MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (#128739)
The MI scheduler skips regions containing a single MI during scheduling.
This can prevent targets that perform multi-stage scheduling and move
MIs between regions during some stages to reason correctly about the
entire IR, since some MIs will not be assigned to a region at the
beginning.
This makes the machine scheduler no longer skip single-MI regions. Only
a few unit tests are affected (mainly those which check for the
scheduler's debug output).
Commit: 241a56dfadfdb14363cf98e8b57cfc507c7991f4
https://github.com/llvm/llvm-project/commit/241a56dfadfdb14363cf98e8b57cfc507c7991f4
Author: Abhilash Majumder <30946547+abhilash1910 at users.noreply.github.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/applypriority.ll
Log Message:
-----------
[NVPTX] Add Intrinsics for applypriority.* (#127989)
\[NVPTX\] Add ApplyPriority intrinsics
This PR adds applypriority.\* intrinsics with relevant eviction
priorities.
* The lowering is handled from nvvm to nvptx tablegen directly.
* Lit tests are added as part of applypriority.ll
* The generated PTX is verified with a 12.3 ptxas executable.
* Added docs for these intrinsics in NVPTXUsage.rst.
For more information, refer to the PTX ISA
`<https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-applypriority>`_.
---------
Co-authored-by: abmajumder <abmajumder at nvidia.com>
Commit: e3f52690c796baca241a6771d897adc6670a1ed8
https://github.com/llvm/llvm-project/commit/e3f52690c796baca241a6771d897adc6670a1ed8
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
A clang/test/Modules/no-transitive-source-location-change-2.cppm
Log Message:
-----------
[NFC] [C++20] [Modules] Add a test for no transitive changes
Commit: 63caaa24d371aae2ee5d71cdcf8eb5f342e1d28d
https://github.com/llvm/llvm-project/commit/63caaa24d371aae2ee5d71cdcf8eb5f342e1d28d
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
Log Message:
-----------
[LLVM][SVE] Add isel for bfloat based (de)interleave operations. (#128875)
Commit: 8150ab93f7411009cc919022d2937d206a2f4359
https://github.com/llvm/llvm-project/commit/8150ab93f7411009cc919022d2937d206a2f4359
Author: John Brawn <john.brawn at arm.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
A llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
A llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll
Log Message:
-----------
[LoopVectorize] Use CodeSize as the cost kind for minsize (#124119)
Functions marked with minsize should aim for minimum code size, so the
vectorizer should use CodeSize for the cost kind and also the cost we
compare should be the cost for the entire loop: it shouldn't be divided
by the number of vector elements and block costs shouldn't be divided by
the block probability.
Possibly we should also be doing this for optsize as well, but there are
a lot of tests that assume the current behaviour and the definition of
optsize is less clear than minsize (for minsize the goal is to "keep the
code size of this function as small as possible" whereas for optsize
it's "keep the code size of this function low").
Commit: f6262fa035d8b942bf76e084fa875409bc8ff83a
https://github.com/llvm/llvm-project/commit/f6262fa035d8b942bf76e084fa875409bc8ff83a
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Semantics/OpenMP/loop-bind.f90
Log Message:
-----------
[flang] Extend `omp loop` semantic checks for `reduction` (#128823)
Extend semantic checks for `omp loop` directive to report errors when a
`reduction` clause is specified on a standalone `loop` directive with
`teams` binding.
This is similar to how clang behaves.
Commit: 741d7fab4e6c00dea5a38ba202ea80e03b71c59d
https://github.com/llvm/llvm-project/commit/741d7fab4e6c00dea5a38ba202ea80e03b71c59d
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Sema/SemaInit.cpp
A clang/test/CodeGen/AArch64/fp8-init-list.c
Log Message:
-----------
[Clang][Sema] Add special handling of mfloat8 in initializer lists (#125097)
This patch fixes assertion failures in clang, caused by unique
properties of _mfp8 type, namely it not being either scalar or vector
type and it not being either integer or float type.
Commit: 556e4dbdcdfc88bc52b43324c4b3af0100c75cc4
https://github.com/llvm/llvm-project/commit/556e4dbdcdfc88bc52b43324c4b3af0100c75cc4
Author: David Rivera <110955221+RiverDave at users.noreply.github.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M clang-tools-extra/clang-tidy/performance/MoveConstArgCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/performance/move-const-arg.cpp
Log Message:
-----------
[clang-tidy] Fix performance-move-const-arg false negative in ternary… (#128402)
This PR aims to fix `performance-move-const-arg` #126515
## Changes
Enhanced the `performance-move-arg` check in Clang-Tidy to detect cases
where `std::move` is used
in **ternary operator expressions which was not being matched therefore
being tagged as a false negative**
## Testing
- A new mock class has been where the changes have been tested & all
tests pass
I'd appreciate any feedback since this is my first time contributing to
LLVM.
Commit: 7b263faf165df7dc647acae435cf9c47bdee4d1f
https://github.com/llvm/llvm-project/commit/7b263faf165df7dc647acae435cf9c47bdee4d1f
Author: Virginia Cangelosi <virginia.cangelosi at arm.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
Log Message:
-----------
[CLANG]Update svget, svset, svcreate, svundef to have FP8 variants (#126754)
This adds FP8 variants to svget, svset, svcreate and svundef under
arm_sve.td
Commit: 56762b7ace0596404e5ae271f278cf7540b374f2
https://github.com/llvm/llvm-project/commit/56762b7ace0596404e5ae271f278cf7540b374f2
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp
M clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt
A clang-tools-extra/clang-tidy/bugprone/UnintendedCharOstreamOutputCheck.cpp
A clang-tools-extra/clang-tidy/bugprone/UnintendedCharOstreamOutputCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/unintended-char-ostream-output.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/test/clang-tidy/checkers/bugprone/unintended-char-ostream-output-cast-type.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/unintended-char-ostream-output.cpp
Log Message:
-----------
[clang-tidy] Add new check bugprone-unintended-char-ostream-output (#127720)
It wants to find unintended character output from `uint8_t` and `int8_t`
to an ostream.
e.g.
```c++
uint8_t v = 9;
std::cout << v;
```
---------
Co-authored-by: whisperity <whisperity at gmail.com>
Commit: fd534e524dd3b683077cab2dae4c87b7c2f1b574
https://github.com/llvm/llvm-project/commit/fd534e524dd3b683077cab2dae4c87b7c2f1b574
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
M llvm/test/CodeGen/AArch64/argument-blocks.ll
Log Message:
-----------
[AArch64] Do not split bfloat HFA args between regs and stack (#128909)
In AAPCS64, __fp16 and __bf16 share the same machine type, so they
should be treated the same way for argument passing. In particular,
arrays of them need to be treated as homogeneous aggregates, and not
split between registers and the stack.
Commit: a826b9c6285ca111fd09e9ed48e68400948d15b6
https://github.com/llvm/llvm-project/commit/a826b9c6285ca111fd09e9ed48e68400948d15b6
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-27 (Thu, 27 Feb 2025)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp
M clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt
A clang-tools-extra/clang-tidy/bugprone/UnintendedCharOstreamOutputCheck.cpp
A clang-tools-extra/clang-tidy/bugprone/UnintendedCharOstreamOutputCheck.h
M clang-tools-extra/clang-tidy/performance/MoveConstArgCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/unintended-char-ostream-output.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/test/clang-tidy/checkers/bugprone/unintended-char-ostream-output-cast-type.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/unintended-char-ostream-output.cpp
M clang-tools-extra/test/clang-tidy/checkers/performance/move-const-arg.cpp
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Basic/Module.h
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/include/clang/Lex/ModuleMap.h
A clang/include/clang/Lex/ModuleMapFile.h
M clang/include/clang/Tooling/DependencyScanning/ModuleDepCollector.h
M clang/lib/AST/ExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGExprAgg.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Lex/CMakeLists.txt
M clang/lib/Lex/ModuleMap.cpp
A clang/lib/Lex/ModuleMapFile.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
M clang/test/CIR/IR/func.cir
M clang/test/CIR/IR/global.cir
M clang/test/CIR/func-simple.cpp
M clang/test/CIR/global-var-simple.cpp
A clang/test/ClangScanDeps/modules-debug-dir.c
A clang/test/CodeGen/AArch64/fp8-init-list.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
M clang/test/CodeGen/allow-ubsan-check.c
M clang/test/CodeGen/partial-reinitialization2.c
M clang/test/CodeGenCXX/RelativeVTablesABI/dynamic-cast.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/type-info.cpp
A clang/test/CodeGenCXX/sret_cast_with_nonzero_alloca_as.cpp
M clang/test/CodeGenOpenCL/amdgcn-buffer-rsrc-type.cl
M clang/test/CodeGenOpenCL/as_type.cl
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Modules/Inputs/export_as_test.modulemap
M clang/test/Modules/diagnostics.modulemap
M clang/test/Modules/export_as_test.c
A clang/test/Modules/no-transitive-source-location-change-2.cppm
A clang/test/OpenMP/amdgcn_sret_ctor.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_common_syscalls.inc
A compiler-rt/test/sanitizer_common/TestCases/Linux/copy_file_range.c
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/mod-file.cpp
M flang/module/cudadevice.f90
M flang/test/Lower/CUDA/cuda-device-proc.cuf
A flang/test/Semantics/Inputs/modfile72.f90
M flang/test/Semantics/OpenMP/loop-bind.f90
A flang/test/Semantics/modfile72.f90
M libc/docs/dev/header_generation.rst
R libc/utils/hdrgen/enumeration.py
R libc/utils/hdrgen/function.py
R libc/utils/hdrgen/gpu_headers.py
A libc/utils/hdrgen/hdrgen/__init__.py
A libc/utils/hdrgen/hdrgen/enumeration.py
A libc/utils/hdrgen/hdrgen/function.py
A libc/utils/hdrgen/hdrgen/gpu_headers.py
A libc/utils/hdrgen/hdrgen/header.py
A libc/utils/hdrgen/hdrgen/macro.py
A libc/utils/hdrgen/hdrgen/main.py
A libc/utils/hdrgen/hdrgen/object.py
A libc/utils/hdrgen/hdrgen/type.py
A libc/utils/hdrgen/hdrgen/yaml_functions_sorted.py
A libc/utils/hdrgen/hdrgen/yaml_to_classes.py
R libc/utils/hdrgen/header.py
R libc/utils/hdrgen/macro.py
M libc/utils/hdrgen/main.py
R libc/utils/hdrgen/object.py
R libc/utils/hdrgen/type.py
R libc/utils/hdrgen/yaml_functions_sorted.py
M libc/utils/hdrgen/yaml_to_classes.py
M libcxx/docs/ReleaseNotes/21.rst
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/include/__algorithm/equal.h
M libcxx/include/__bit_reference
M libcxx/include/__format/formatter.h
M libcxx/include/__format/formatter_string.h
M libcxx/include/__ostream/print.h
M libcxx/include/__vector/comparison.h
M libcxx/include/bitset
M libcxx/include/forward_list
M libcxx/include/list
M libcxx/test/benchmarks/algorithms/equal.bench.cpp
A libcxx/test/libcxx/containers/sequences/forwardlist/bool-conversion.pass.cpp
A libcxx/test/libcxx/containers/sequences/list/list.modifiers/bool-conversion.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.rotate/pstl.rotate_copy.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.rotate/ranges.rotate_copy.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.rotate/ranges_rotate.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.rotate/rotate.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.rotate/rotate_copy.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.equal/equal.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.equal/ranges.equal.pass.cpp
M libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/print.pass.cpp
M libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/vprint_nonunicode.pass.cpp
M libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/vprint_unicode.pass.cpp
M libcxx/test/std/utilities/format/format.formattable/concept.formattable.compile.pass.cpp
M lld/ELF/Writer.cpp
M lld/test/ELF/linkerscript/symbol-assign-many-passes2.test
M lldb/examples/python/fzf_history.py
M lldb/include/lldb/Host/PipeBase.h
M lldb/include/lldb/Host/posix/PipePosix.h
M lldb/include/lldb/Host/windows/PipeWindows.h
M lldb/source/Core/CMakeLists.txt
M lldb/source/Core/Telemetry.cpp
M lldb/source/Host/common/PipeBase.cpp
M lldb/source/Host/common/Socket.cpp
M lldb/source/Host/posix/ConnectionFileDescriptorPosix.cpp
M lldb/source/Host/posix/MainLoopPosix.cpp
M lldb/source/Host/posix/PipePosix.cpp
M lldb/source/Host/windows/PipeWindows.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/source/Symbol/LineTable.cpp
M lldb/source/Target/Process.cpp
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/IOStream.cpp
M lldb/tools/lldb-dap/IOStream.h
M lldb/tools/lldb-dap/lldb-dap.cpp
M lldb/tools/lldb-server/lldb-gdbserver.cpp
M lldb/unittests/Core/CMakeLists.txt
M lldb/unittests/Core/TelemetryTest.cpp
M lldb/unittests/Host/PipeTest.cpp
M llvm/CMakeLists.txt
M llvm/cmake/modules/LLVMConfig.cmake.in
M llvm/docs/DirectX/DXILResources.rst
M llvm/docs/GetElementPtr.rst
M llvm/docs/GettingInvolved.rst
M llvm/docs/LangRef.rst
M llvm/docs/NVPTXUsage.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/ADT/APFloat.h
M llvm/include/llvm/Analysis/CaptureTracking.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/Config/llvm-config.h.cmake
M llvm/include/llvm/ExecutionEngine/Orc/GetDylibInterface.h
M llvm/include/llvm/ExecutionEngine/Orc/MachOBuilder.h
M llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h
M llvm/include/llvm/IR/InstrTypes.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/Support/ModRef.h
M llvm/include/llvm/Telemetry/Telemetry.h
M llvm/include/llvm/Transforms/Instrumentation/PGOCtxProfLowering.h
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/CaptureTracking.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/CMakeLists.txt
M llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/GetDylibInterface.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/IR/DroppedVariableStats.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Support/DAGDeltaAlgorithm.cpp
M llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.h
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.h
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILOpBuilder.cpp
M llvm/lib/Target/DirectX/DXILOpBuilder.h
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
A llvm/lib/Target/RISCV/RISCVInstrInfoXqccmp.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/lib/Telemetry/Telemetry.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Instrumentation/PGOCtxProfLowering.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Analysis/CostModel/AArch64/aggregates.ll
M llvm/test/Analysis/CostModel/AArch64/arith-fp.ll
M llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
M llvm/test/Analysis/CostModel/AArch64/arith.ll
M llvm/test/Analysis/CostModel/AArch64/bitreverse.ll
M llvm/test/Analysis/CostModel/AArch64/fshl.ll
M llvm/test/Analysis/CostModel/AArch64/fshr.ll
M llvm/test/Analysis/CostModel/AArch64/gep.ll
M llvm/test/Analysis/CostModel/AArch64/min-max.ll
M llvm/test/Analysis/CostModel/AArch64/mul.ll
M llvm/test/Analysis/CostModel/AArch64/reduce-add.ll
M llvm/test/Analysis/CostModel/AArch64/reduce-and.ll
M llvm/test/Analysis/CostModel/AArch64/reduce-fadd.ll
M llvm/test/Analysis/CostModel/AArch64/reduce-minmax.ll
M llvm/test/Analysis/CostModel/AArch64/reduce-or.ll
M llvm/test/Analysis/CostModel/AArch64/reduce-xor.ll
M llvm/test/Analysis/CostModel/AArch64/select.ll
M llvm/test/Analysis/CostModel/AArch64/shuffle-broadcast.ll
M llvm/test/Analysis/CostModel/AArch64/shuffle-reverse.ll
M llvm/test/CodeGen/AArch64/argument-blocks.ll
M llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
M llvm/test/CodeGen/AMDGPU/bug-cselect-b64.ll
M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence.ll
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-scalar-fmac.mir
M llvm/test/CodeGen/AMDGPU/fold-sgpr-multi-imm.mir
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
A llvm/test/CodeGen/AMDGPU/i1-divergent-phi-fix-sgpr-copies-assert.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/shl64_reduce.ll
M llvm/test/CodeGen/AMDGPU/si-fold-operands-commute-same-operands-assert.mir
A llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir
A llvm/test/CodeGen/AMDGPU/spillv16.ll
A llvm/test/CodeGen/AMDGPU/spillv16.mir
M llvm/test/CodeGen/ARM/misched-branch-targets.mir
A llvm/test/CodeGen/DirectX/CBufferLoadLegacy-errors.ll
A llvm/test/CodeGen/DirectX/CBufferLoadLegacy.ll
A llvm/test/CodeGen/NVPTX/applypriority.ll
A llvm/test/CodeGen/NVPTX/tcgen05-ld.ll
A llvm/test/CodeGen/NVPTX/tcgen05-st.ll
M llvm/test/CodeGen/PowerPC/pr47155-47156.ll
M llvm/test/CodeGen/PowerPC/v4i32_scalar_to_vector_shuffle.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/WebAssembly/lower-em-ehsjlj-options.ll
M llvm/test/CodeGen/WebAssembly/lower-em-sjlj.ll
M llvm/test/CodeGen/WebAssembly/lower-wasm-ehsjlj.ll
M llvm/test/CodeGen/X86/fake-use-scheduler.mir
M llvm/test/CodeGen/X86/fp16-libcalls.ll
M llvm/test/CodeGen/X86/half.ll
M llvm/test/CodeGen/X86/llvm.acos.ll
M llvm/test/CodeGen/X86/llvm.asin.ll
M llvm/test/CodeGen/X86/llvm.atan.ll
M llvm/test/CodeGen/X86/llvm.atan2.ll
M llvm/test/CodeGen/X86/llvm.cos.ll
M llvm/test/CodeGen/X86/llvm.cosh.ll
M llvm/test/CodeGen/X86/llvm.sin.ll
M llvm/test/CodeGen/X86/llvm.sinh.ll
M llvm/test/CodeGen/X86/llvm.tan.ll
M llvm/test/CodeGen/X86/llvm.tanh.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx2-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/mmx-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/avx-intrinsics-i386.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/avx2-intrinsics-i386.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/mmx-intrinsics.ll
A llvm/test/MC/RISCV/rv32xqccmp-invalid.s
A llvm/test/MC/RISCV/rv32xqccmp-valid.s
A llvm/test/MC/RISCV/rv64e-xqccmp-valid.s
A llvm/test/MC/RISCV/rv64xqccmp-invalid.s
A llvm/test/MC/RISCV/rv64xqccmp-valid.s
A llvm/test/MC/RISCV/xrivosvisni-valid.s
A llvm/test/MachineVerifier/AMDGPU/verifier-sdwa-selection.mir
M llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
M llvm/test/Transforms/FunctionAttrs/2009-01-02-LocalStores.ll
M llvm/test/Transforms/FunctionAttrs/arg_returned.ll
M llvm/test/Transforms/FunctionAttrs/nocapture.ll
M llvm/test/Transforms/FunctionAttrs/nonnull.ll
M llvm/test/Transforms/FunctionAttrs/noundef.ll
M llvm/test/Transforms/FunctionAttrs/readattrs.ll
M llvm/test/Transforms/FunctionAttrs/stats.ll
A llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
A llvm/test/Transforms/LoopVectorize/AArch64/sincos.ll
A llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/if-conversion.ll
A llvm/test/Transforms/LoopVectorize/sincos.ll
A llvm/test/Transforms/PGOProfile/ctx-instrumentation-block-inline.ll
A llvm/test/Transforms/PGOProfile/ctx-instrumentation-optin.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/block_scaling_decompr_8bit.ll
M llvm/test/Transforms/PhaseOrdering/bitcast-store-branch.ll
M llvm/test/Transforms/PhaseOrdering/dce-after-argument-promotion-loads.ll
M llvm/test/Transforms/PhaseOrdering/enable-loop-header-duplication-oz.ll
A llvm/test/Transforms/SLPVectorizer/X86/buildvector-reused-with-bv-subvector.ll
A llvm/test/Transforms/SLPVectorizer/X86/reduction-with-removed-extracts.ll
A llvm/test/Transforms/Scalarizer/deinterleave2.ll
R llvm/test/Transforms/Scalarizer/sincos.ll
M llvm/test/tools/llvm-mca/RISCV/SiFiveP400/div.s
M llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/div.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlseg-vsseg.s
M llvm/unittests/ADT/APFloatTest.cpp
M llvm/unittests/Analysis/CaptureTrackingTest.cpp
M llvm/unittests/CMakeLists.txt
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/Telemetry/TelemetryTest.cpp
M llvm/utils/TableGen/DXILEmitter.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Lex/BUILD.gn
M llvm/utils/gn/secondary/clang/utils/TableGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn
M mlir/include/mlir/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.h
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUDialect.h
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.h
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/MLProgram/Transforms/Passes.h
M mlir/include/mlir/Dialect/MLProgram/Transforms/Passes.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/Shape/Transforms/Passes.h
M mlir/include/mlir/Dialect/Shape/Transforms/Passes.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.h
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaProfileCompliance.h
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/CMakeLists.txt
A mlir/lib/Dialect/AMDGPU/Transforms/ResolveStridedMetadata.cpp
M mlir/lib/Dialect/MLProgram/Transforms/PipelineGlobalOps.cpp
M mlir/lib/Dialect/Shape/Transforms/OutlineShapeComputation.cpp
M mlir/lib/Dialect/Shape/Transforms/RemoveShapeConstraints.cpp
M mlir/lib/Dialect/Shape/Transforms/ShapeToShapeLowering.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeDepthwise.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeTransposeConv.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaFolders.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Conversion/AMDGPUToROCDL/amdgpu-to-rocdl.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-invalid.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm-interface.mlir
A mlir/test/Dialect/AMDGPU/amdgpu-resolve-strided-metadata.mlir
M mlir/test/Dialect/AMDGPU/invalid.mlir
M mlir/test/Dialect/AMDGPU/ops.mlir
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/constant-op-fold.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/profile_all_unsupported.mlir
M mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-depthwise.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-transpose-conv.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/tosa-reduce-transposes.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-private.mlir
A mlir/test/Target/LLVMIR/openmp-task-privatization.mlir
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl
A utils/bazel/llvm-project-overlay/libc/test/src/stdbit/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/stdlib/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm_configs/llvm-config.h.cmake
Log Message:
-----------
Rebase, add option
Created using spr 1.3.5
Compare: https://github.com/llvm/llvm-project/compare/3bb5867cd34e...a826b9c6285c
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