[all-commits] [llvm/llvm-project] eec0cd: [MachineSink] Lower SplitEdgeProbabilityThreshold

[Guy David via All-commits]

  Branch: refs/heads/users/guy-david/machine-sink
  Home:   https://github.com/llvm/llvm-project
  Commit: eec0cdbe279bfb2b9af155f6ff43bf2d9fdb14ef
      https://github.com/llvm/llvm-project/commit/eec0cdbe279bfb2b9af155f6ff43bf2d9fdb14ef
  Author: Guy David <guyda96 at gmail.com>
  Date:   2025-02-26 (Wed, 26 Feb 2025)

  Changed paths:
    M llvm/lib/CodeGen/MachineSink.cpp

  Log Message:
  -----------
  [MachineSink] Lower SplitEdgeProbabilityThreshold

Lower it slightly below the likeliness of a null-check to be true which
is set to 37.5% (see PtrUntakenProb).
Otherwise, it will split the edge and create another basic-block and
with an unconditional branch which might make the CFG more complex and
with a suboptimal block placement.
Note that if multiple instructions can be sinked from the same edge then
a split will occur regardless of this change.


  Commit: 0f5d7690c8af646e8184e1132a197249a6d1ac1b
      https://github.com/llvm/llvm-project/commit/0f5d7690c8af646e8184e1132a197249a6d1ac1b
  Author: Guy David <guyda96 at gmail.com>
  Date:   2025-02-26 (Wed, 26 Feb 2025)

  Changed paths:
    M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
    M llvm/test/CodeGen/AArch64/swifterror.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
    M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
    M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
    M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
    M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
    M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
    M llvm/test/CodeGen/ARM/and-cmp0-sink.ll
    M llvm/test/CodeGen/Mips/llvm-ir/sdiv-freebsd.ll
    M llvm/test/CodeGen/PowerPC/common-chain-aix32.ll
    M llvm/test/CodeGen/PowerPC/common-chain.ll
    M llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
    M llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll
    M llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
    M llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
    M llvm/test/CodeGen/PowerPC/mma-phi-accs.ll
    M llvm/test/CodeGen/PowerPC/p10-spill-creq.ll
    M llvm/test/CodeGen/PowerPC/ppc64-rop-protection-aix.ll
    M llvm/test/CodeGen/PowerPC/ppc64-rop-protection.ll
    M llvm/test/CodeGen/PowerPC/shrink-wrap.ll
    M llvm/test/CodeGen/PowerPC/spe.ll
    M llvm/test/CodeGen/PowerPC/zext-and-cmp.ll
    M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
    M llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
    M llvm/test/CodeGen/WebAssembly/implicit-def.ll
    M llvm/test/CodeGen/X86/2007-11-06-InstrSched.ll
    M llvm/test/CodeGen/X86/2008-04-28-CoalescerBug.ll
    M llvm/test/CodeGen/X86/atomic-rm-bit-test-64.ll
    M llvm/test/CodeGen/X86/atomic-rm-bit-test.ll
    M llvm/test/CodeGen/X86/break-false-dep.ll
    M llvm/test/CodeGen/X86/coalescer-commute4.ll
    M llvm/test/CodeGen/X86/ctlo.ll
    M llvm/test/CodeGen/X86/ctlz.ll
    M llvm/test/CodeGen/X86/cttz.ll
    M llvm/test/CodeGen/X86/fold-loop-of-urem.ll
    M llvm/test/CodeGen/X86/lsr-sort.ll
    M llvm/test/CodeGen/X86/mmx-arith.ll
    M llvm/test/CodeGen/X86/pr2659.ll
    M llvm/test/CodeGen/X86/pr38795.ll
    M llvm/test/CodeGen/X86/probe-stack-eflags.ll
    M llvm/test/CodeGen/X86/testb-je-fusion.ll
    M llvm/test/CodeGen/X86/x86-shrink-wrapping.ll

  Log Message:
  -----------
  fixup! Automatically updated tests


  Commit: f2418cc0031d86d326a22b30c6dfa635ee3bbe1d
      https://github.com/llvm/llvm-project/commit/f2418cc0031d86d326a22b30c6dfa635ee3bbe1d
  Author: Guy David <guyda96 at gmail.com>
  Date:   2025-02-26 (Wed, 26 Feb 2025)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/artificial-terminators.mir
    M llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll
    M llvm/test/CodeGen/WebAssembly/implicit-def.ll
    M llvm/test/CodeGen/X86/branchfolding-debugloc.ll
    M llvm/test/CodeGen/X86/taildup-heapallocsite.ll
    M llvm/test/DebugInfo/COFF/pieces.ll

  Log Message:
  -----------
  fixup! Manually fixed tests


Compare: https://github.com/llvm/llvm-project/compare/ddb2ff2b7fd1...f2418cc0031d

To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications