[all-commits] [llvm/llvm-project] ff80bd: [RISCV] Adding missing P600 sched model test for R...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ff80bdcf734909ac837e88cafdfc1b5d66845a98
      https://github.com/llvm/llvm-project/commit/ff80bdcf734909ac837e88cafdfc1b5d66845a98
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-02-26 (Wed, 26 Feb 2025)

  Changed paths:
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlseg-vsseg.s

  Log Message:
  -----------
  [RISCV] Adding missing P600 sched model test for RVV segmented loads/stores

This is the P600 counterpart of
`test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s`.



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