[all-commits] [llvm/llvm-project] 2dfb29: [libclc] Move nan to the CLC library (#128521)
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Wed Feb 26 09:12:05 PST 2025
Branch: refs/heads/users/alexey-bataev/spr/slpreduce-number-of-alternate-instruction-where-possible-1
Home: https://github.com/llvm/llvm-project
Commit: 2dfb29a9b2f63e8dcbace2bf9b73ecc770f62b4d
https://github.com/llvm/llvm-project/commit/2dfb29a9b2f63e8dcbace2bf9b73ecc770f62b4d
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
A libclc/clc/include/clc/math/clc_nan.h
A libclc/clc/include/clc/math/clc_nan.inc
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/math/clc_nan.cl
A libclc/clc/lib/generic/math/clc_nan.inc
M libclc/generic/lib/math/nan.cl
M libclc/generic/lib/math/nan.inc
Log Message:
-----------
[libclc] Move nan to the CLC library (#128521)
Commit: 3a6108bcac26016b791cabce86424c1f1dcf3056
https://github.com/llvm/llvm-project/commit/3a6108bcac26016b791cabce86424c1f1dcf3056
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/SystemZ/revec-fix-128169.ll
Log Message:
-----------
[SLP][REVEC] Fix scalar mask is passed to getScalarizationOverhead but the type is vector. (#128476)
Fix "Vector size mismatch".
Commit: 0b52aa1bdbc7416592e9c81d9a44ce411c21e081
https://github.com/llvm/llvm-project/commit/0b52aa1bdbc7416592e9c81d9a44ce411c21e081
Author: vdonaldson <37090318+vdonaldson at users.noreply.github.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M flang/docs/Extensions.md
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/test/Lower/Intrinsics/ieee_rint_int.f90
M flang/test/Lower/Intrinsics/ieee_rounding.f90
Log Message:
-----------
[flang] Unsupported rounding modes (#128240)
Two new ieee_round_type values were added in f18 beyond the four values
defined in f03 and f08: ieee_away and ieee_other. Contemporary hardware
typically does not have support for these rounding modes, so flang does
not support them. ieee_support_rounding calls for these values return
false. Current generated code handles some attempts to set the rounding
mode to one of these unsupported values by setting the mode to
ieee_nearest. Update the code to explicitly do this in all cases.
Commit: 16f9c5da45b88ace429064b4823e94491b0ea9b1
https://github.com/llvm/llvm-project/commit/16f9c5da45b88ace429064b4823e94491b0ea9b1
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/test/CodeGen/SPIRV/read_image.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpImageReadMS.ll
Log Message:
-----------
[SPIR-V] Stop generating StorageImageReadWithoutFormat and StorageImageWriteWithoutFormat for the Unknown image format in the OpenCL environment (#128497)
This PR resolves the issue of the SPIR-V specification, requiring
Shader-coupled capabilities to read/write images in the OpenCL SPIR-V
environment, from the perspective of the LLVM SPIR-V backend. See
https://github.com/KhronosGroup/SPIRV-Headers/issues/487 for details and
discussion.
Current implementation correctly reproduces requirements of the SPIR-V
specification, however, since the requirements are problematic, out
current implementation blocks generation of valid SPIR-V code for
compute environments. This PR is to implement a solution discussed at
the SPIR-V WG to allow proceeding with generation of valid SPIR-V code
for the OpenCL environment and do not impact Vulkan environment at the
same time.
Commit: 529b3d16daf2c7970f6f0b1f97e8ed09891c726a
https://github.com/llvm/llvm-project/commit/529b3d16daf2c7970f6f0b1f97e8ed09891c726a
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Log Message:
-----------
[RISCV][TTI] Remove SK_Select from manual splitting in getShuffleCost
We have general splitting logic for this kind just below, which to my
knowledge is both correct and precise. Given no test changes, either
a) the adhoc logic works out the same, or b) we have no coverage. I
did not investigate which.
Commit: 17ccaf4fa82ed6d081144f91b5580e24e44d435c
https://github.com/llvm/llvm-project/commit/17ccaf4fa82ed6d081144f91b5580e24e44d435c
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M offload/plugins-nextgen/host/CMakeLists.txt
Log Message:
-----------
[NFC][Offload] Fix typo to output architecture (#128527)
Commit: b66ec64b5b634cbf760d69d1629e462268aa1cbd
https://github.com/llvm/llvm-project/commit/b66ec64b5b634cbf760d69d1629e462268aa1cbd
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/RegAllocGreedy.cpp
Log Message:
-----------
RegAllocGreedy: Remove unnecessary null register class check (#128487)
Commit: 538b898a836ac6efc3b0ec12cf27b511608d2e64
https://github.com/llvm/llvm-project/commit/538b898a836ac6efc3b0ec12cf27b511608d2e64
Author: quic_hchandel <quic_hchandel at quicinc.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
A llvm/test/MC/RISCV/xqcilia-invalid.s
A llvm/test/MC/RISCV/xqcilia-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (#124706)
This extension adds eight 48 bit large arithmetic instructions.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
Commit: cebb8f72b7937548bd17c7972297f2efafa1e958
https://github.com/llvm/llvm-project/commit/cebb8f72b7937548bd17c7972297f2efafa1e958
Author: Sergio Afonso <safonsof at amd.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Log Message:
-----------
[OpenMPIRBuilder] Add support for distribute constructs (#127816)
This patch adds the `OpenMPIRBuilder::createDistribute()` function and
updates `OpenMPIRBuilder::applyStaticWorkshareLoop()` in preparation for
adding `distribute` support to flang.
Co-authored-by: Dominik Adamski <dominik.adamski at amd.com>
Commit: 5bddadf783c177943fa4f86fa0d295d4e88e7dea
https://github.com/llvm/llvm-project/commit/5bddadf783c177943fa4f86fa0d295d4e88e7dea
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/docs/CodingStandards.rst
Log Message:
-----------
[CodingStandard] Rework anonymous namespace section to cover visibility more broadly (#126775)
- Rename anonymous namespace section and rework it to
cover visibility more broadly.
- Add language suggesting restricting visibility as much as
possible, using various C++ facilities.
---------
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: 4defac91dbdf4d54aa40a47851c48e9c587fb7e9
https://github.com/llvm/llvm-project/commit/4defac91dbdf4d54aa40a47851c48e9c587fb7e9
Author: Matthias Springer <me at m-sp.org>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M mlir/include/mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h
M mlir/include/mlir/Dialect/GPU/TransformOps/GPUTransformOps.td
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h
M mlir/lib/Conversion/GPUCommon/IndexIntrinsicsOpLowering.h
M mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/GPUToNVVM/WmmaOpsToNvvm.cpp
M mlir/lib/Dialect/GPU/TransformOps/GPUTransformOps.cpp
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm-32b.mlir
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
Log Message:
-----------
[mlir][GPUToNVVM] Add `benefit` to `populate` functions (#128484)
Certain GPU->NVVM patterns compete with Arith->LLVM patterns. (The ones
that lower to libdevice.) Add an optional `benefit` parameter to all
`populate` functions so that users can give preference to GPU->NVVM
patterns.
Commit: 7a4cb9bac50c8c19ec0d4ab7f186ef086064a549
https://github.com/llvm/llvm-project/commit/7a4cb9bac50c8c19ec0d4ab7f186ef086064a549
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt
M clang-tools-extra/clang-tidy/bugprone/StandaloneEmptyCheck.cpp
M clang/include/clang/Sema/HeuristicResolver.h
M clang/lib/Sema/HeuristicResolver.cpp
Log Message:
-----------
[clang-tidy][NFC] Expose HeuristicResolver::lookupDependentName() and use it in StandaloneEmptyCheck (#128391)
The use replaces CXXRecordDecl::lookupDependentName() which
HeuristicResolver aims to supersede.
Commit: ff7790e6dde7859b993b7d9abb4a2ec4fe2ae779
https://github.com/llvm/llvm-project/commit/ff7790e6dde7859b993b7d9abb4a2ec4fe2ae779
Author: Sergio Afonso <safonsof at amd.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
Log Message:
-----------
[MLIR][OpenMP] Simplify definition of the BlockArgOpenMPOpInterface, NFC (#128198)
This patch removes code duplication from the definition of methods of
the `BlockArgOpenMPOpInterface` and makes the order relationship between
entry block argument generating clauses explicit.
The goal of this change is to make the addition of clauses and methods
to the interface less error-prone.
Commit: aab07d8ca64495600ce9e7fe4825ca7ff9057c28
https://github.com/llvm/llvm-project/commit/aab07d8ca64495600ce9e7fe4825ca7ff9057c28
Author: sommersun <50041042+sommersun at users.noreply.github.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/include/llvm/TableGen/Record.h
Log Message:
-----------
fixed #95641 pointless string copy (#127325)
fixed #95641 by using std::move for T&&.
Commit: e89cd500b252c02dd18a5b7e1f5065df7a878ff4
https://github.com/llvm/llvm-project/commit/e89cd500b252c02dd18a5b7e1f5065df7a878ff4
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/clang-tools-extra/clang-tidy/BUILD.bazel
Log Message:
-----------
[bazel] Port 7a4cb9bac50c8c19ec0d4ab7f186ef086064a549
Commit: 63af27190be70c3ea94bf913b93cb82db9eca25c
https://github.com/llvm/llvm-project/commit/63af27190be70c3ea94bf913b93cb82db9eca25c
Author: Florian Mayer <fmayer at google.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M clang/test/CodeGen/memtag-globals-asm.cpp
Log Message:
-----------
[NFC] [test] assert padding in memtag-globals test (#128259)
Commit: 20fd7f0a76ae97e7cd645412ef5ca1a9e9614578
https://github.com/llvm/llvm-project/commit/20fd7f0a76ae97e7cd645412ef5ca1a9e9614578
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/docs/GettingInvolved.rst
Log Message:
-----------
Remove floating-point working group meeting (#128258)
This meeting never quite took off the way I had hoped, and I haven't had
time for it in quite a while, so I am removing it from the Getting
Involved page.
Commit: f1252f539ca203a979d61b616186e9be9d612f96
https://github.com/llvm/llvm-project/commit/f1252f539ca203a979d61b616186e9be9d612f96
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
A llvm/test/MC/PowerPC/case-insensitive-regs.s
Log Message:
-----------
[PPC][MC] Restore support for case-insensitive register names (#128525)
Lowercase the name before calling MatchRegisterName(), to restore
support for using `%R3` instead of `%r3` and similar, matching the GNU
assembler.
Fixes https://github.com/llvm/llvm-project/issues/126786.
Commit: cc7f22ee6ccb2c1ad79834e06d5b18d8f014d140
https://github.com/llvm/llvm-project/commit/cc7f22ee6ccb2c1ad79834e06d5b18d8f014d140
Author: Hood Chatham <roberthoodchatham at gmail.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/include/llvm/ObjectYAML/WasmYAML.h
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/ObjectYAML/WasmEmitter.cpp
M llvm/lib/ObjectYAML/WasmYAML.cpp
M llvm/test/ObjectYAML/wasm/dylink_section.yaml
M llvm/tools/obj2yaml/wasm2yaml.cpp
Log Message:
-----------
[object][WebAssembly] Add support for RUNTIME_PATH to yaml2obj and obj2yaml (#126080)
This is the first step of adding RPATH support for wasm.
See corresponding update to the WebAssembly/tool-conventions repo on dynamic
linking: https://github.com/WebAssembly/tool-conventions/pull/246
Commit: 36fdeb2aded08a776fcffefa73cb7667e7fc6c2d
https://github.com/llvm/llvm-project/commit/36fdeb2aded08a776fcffefa73cb7667e7fc6c2d
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/FIRBuilder.h
M flang/include/flang/Optimizer/Builder/Runtime/RTBuilder.h
M flang/include/flang/Optimizer/Dialect/FIRDialect.td
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
A flang/include/flang/Optimizer/Transforms/RuntimeFunctions.inc
M flang/lib/Lower/IO.cpp
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
A flang/lib/Optimizer/Transforms/GenRuntimeCallsForTest.cpp
A flang/lib/Optimizer/Transforms/SetRuntimeCallAttributes.cpp
M flang/test/Driver/mlir-pass-pipeline.f90
M flang/test/Fir/basic-program.fir
M flang/test/Lower/array-temp.f90
A flang/test/Transforms/set-runtime-call-attributes.fir
A flang/test/Transforms/verify-known-runtime-functions.fir
A flang/test/Utils/generate-checks-for-runtime-funcs.py
Log Message:
-----------
[flang] Set LLVM specific attributes to fir.call's of Fortran runtime. (#128093)
This change is inspired by a case in facerec benchmark, where
performance
of scalar code may improve by about 6%@aarch64 due to getting rid of
redundant
loads from Fortran descriptors. These descriptors are corresponding
to subroutine local ALLOCATABLE, SAVE variables. The scalar loop nest
in LocalMove subroutine contains call to Fortran runtime IO functions,
and LLVM globals-aa analysis cannot prove that these calls do not modify
the globalized descriptors with internal linkage.
This patch sets and propagates llvm.memory_effects attribute for
fir.call
operations calling Fortran runtime functions. In particular, it tries
to set the Other memory effect to NoModRef. The Other memory effect
includes accesses to globals and captured pointers, so we cannot set
it for functions taking Fortran descriptors with one exception
for calls where the Fortran descriptor arguments are all null.
As long as different calls to the same Fortran runtime function may have
different attributes, I decided to attach the attributes to the calls
rather than functions. Moreover, attaching the attributes to func.func
will require propagating these attributes to llvm.func, which is not
happening right now.
In addition to llvm.memory_effects, the new pass sets llvm.nosync
and llvm.nocallback attributes that may also help LLVM alias analysis
(e.g. see #127707). These attributes are ignored currently.
I will support them in LLVM IR dialect in a separate patch.
I also added another pass for developers to be able to print
declarations/calls of all Fortran runtime functions that are recognized
by the attributes setting pass. It should help with maintenance
of the LIT tests.
Commit: a6abbe03094a7afc85d4d35c24e6cedd1cfc4ef2
https://github.com/llvm/llvm-project/commit/a6abbe03094a7afc85d4d35c24e6cedd1cfc4ef2
Author: Deric Cheung <cheung.deric at gmail.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M clang/test/SemaHLSL/BuiltIns/and-errors.hlsl
Log Message:
-----------
[test] Remove `-emit-llvm` from the `and-errors.hlsl` test to avoid writing to a potentially write-protected directory (#128047)
@mikaelholmen
[mentioned](https://github.com/llvm/llvm-project/pull/127098#discussion_r1962897888)
that the `-emit-llvm` argument isn't necessary for the `and-errors.hlsl`
test and may cause issues due to writing to the current (potentially
write-protected) directory.
This PR removes the `-emit-llvm` argument from clang in the RUN lines of
the test.
Commit: 7f6f186736c81ab3ca1881ed9d5569ffc1050df8
https://github.com/llvm/llvm-project/commit/7f6f186736c81ab3ca1881ed9d5569ffc1050df8
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVBaseInfo.h
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVMCInstLower.cpp
Log Message:
-----------
[SPIRV] Stop including SPIRVInstrInfo.h in MCTargetDesc. NFC (#128443)
SPIRVInstrInfo.h is a CodeGen layer file, it should not be used in MC
layer files.
This required adding a new enum for MCInst flags and a conversion from
MachineInstr's AsmPrinter flags in SPIRVMCInstLower.
Commit: a0be17dc91d054290910b5787f41900fb6ef0d6e
https://github.com/llvm/llvm-project/commit/a0be17dc91d054290910b5787f41900fb6ef0d6e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Log Message:
-----------
[RISCV] Remove unnecessary entries from RISCVVInversePseudosTable. NFC (#128376)
The inverse pseudos table contained entries that map back to the
unmasked and masked pseudo, but the lookup only returns the first one.
Add a new FilterClassField to remove the unnecessary entries.
This reduces the size of the llvm-mca binary by ~32KB.
Commit: 664cbd1b5db190724ceea498d1f520eb66d78d69
https://github.com/llvm/llvm-project/commit/664cbd1b5db190724ceea498d1f520eb66d78d69
Author: John Harrison <harjohn at google.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M lldb/test/API/tools/lldb-dap/server/TestDAP_server.py
Log Message:
-----------
[lldb-dap] skip TestDAP_server on windows to unblock CI. (#128278)
This should fix the tests running on windows.
https://lab.llvm.org/buildbot/#/builders/141/builds/6506 is the failure,
the error message does not clearly indicate why the connection failed,
but they are passing for me locally on macOS and passed on linux in the
CI.
Commit: 571b787b83cb1bfc7d4c8214b296ec965e7bb7e2
https://github.com/llvm/llvm-project/commit/571b787b83cb1bfc7d4c8214b296ec965e7bb7e2
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
M llvm/lib/Target/AMDGPU/R600InstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/ARC/ARCInstrInfo.cpp
M llvm/lib/Target/ARC/ARCInstrInfo.h
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
M llvm/lib/Target/ARM/Thumb1InstrInfo.h
M llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
M llvm/lib/Target/ARM/Thumb2InstrInfo.h
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.h
M llvm/lib/Target/BPF/BPFInstrInfo.cpp
M llvm/lib/Target/BPF/BPFInstrInfo.h
M llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
M llvm/lib/Target/CSKY/CSKYInstrInfo.h
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
M llvm/lib/Target/Lanai/LanaiInstrInfo.h
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/lib/Target/M68k/M68kInstrInfo.h
M llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
M llvm/lib/Target/MSP430/MSP430InstrInfo.h
M llvm/lib/Target/Mips/Mips16InstrInfo.cpp
M llvm/lib/Target/Mips/Mips16InstrInfo.h
M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
M llvm/lib/Target/Mips/MipsSEInstrInfo.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
M llvm/lib/Target/Sparc/SparcInstrInfo.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.h
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
M llvm/lib/Target/VE/VEInstrInfo.cpp
M llvm/lib/Target/VE/VEInstrInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/lib/Target/XCore/XCoreInstrInfo.cpp
M llvm/lib/Target/XCore/XCoreInstrInfo.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.h
Log Message:
-----------
[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister. (#128473)
NVPTX, SPIRV, and WebAssembly pass virtual registers to this function
since they don't perform register allocation. We need to use Register to
avoid a virtual register being converted to MCRegister by the caller.
Commit: 8dbc393e447299d1a4d35b96c6e66542a5928cff
https://github.com/llvm/llvm-project/commit/8dbc393e447299d1a4d35b96c6e66542a5928cff
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
Log Message:
-----------
[flang][cuda][NFC] Remove shared alloc addr space (#128535)
Commit: e298fc2da97120a30ee2f120ac184ab209fc1eb4
https://github.com/llvm/llvm-project/commit/e298fc2da97120a30ee2f120ac184ab209fc1eb4
Author: Tom Tromey <tromey at adacore.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/include/llvm-c/DebugInfo.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/Metadata.def
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/LLVMContextImpl.h
M llvm/lib/IR/Verifier.cpp
A llvm/test/Bitcode/subrange_type.ll
M llvm/unittests/IR/MetadataTest.cpp
Log Message:
-----------
Add DISubrangeType (#126772)
An Ada program can have types that are subranges of other types. This
patch adds a new DIType node, DISubrangeType, to represent this concept.
I considered extending the existing DISubrange to do this, but as
DISubrange does not derive from DIType, that approach seemed more
disruptive.
A DISubrangeType can be used both as an ordinary type, but also as the
type of an array index. This is also important for Ada.
Ada subrange types can also be stored using a bias. Representing this in
the DWARF required the use of an extension. GCC has been emitting this
extension for years, so I've reused it here.
Commit: d9d1f241f27bab3c7b8914196316a6e6202cc61e
https://github.com/llvm/llvm-project/commit/d9d1f241f27bab3c7b8914196316a6e6202cc61e
Author: Nico Weber <thakis at chromium.org>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/tools/lldb-dap/BUILD.gn
Log Message:
-----------
[gn build] Port d0e37d972331 (llvm-dap tweaks)
Commit: 9638d08af96c4cb8cf16785eed92179b2658bdfe
https://github.com/llvm/llvm-project/commit/9638d08af96c4cb8cf16785eed92179b2658bdfe
Author: Akshay Deodhar <adeodhar at nvidia.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/atomics.ll
A llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
A llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
A llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
A llvm/test/CodeGen/NVPTX/cmpxchg.py
M llvm/test/CodeGen/NVPTX/lit.local.cfg
Log Message:
-----------
[NVPTX] Support for memory orderings for cmpxchg (#126159)
So far, all cmpxchg instructions were lowered to atom.cas. This change
adds support for memory orders in lowering. Specifically:
- For cmpxchg which are emulated, memory ordering is enforced by adding
fences around the emulation loops.
- For cmpxchg which are lowered to PTX directly, where the memory order
is supported in ptx, lower directly to the correct ptx instruction.
- For seq_cst cmpxchg which are lowered to PTX directly, use a sequence
(fence.sc; atom.cas.acquire) to provide the semantics that we want.
Also adds tests for all possible combinations of (size, memory ordering,
address space, SM/PTX versions)
This also adds `atomicOperationOrderAfterFenceSplit` in TargetLowering,
for specially handling seq_cst atomics.
Commit: 51ce6c437fec1fe0170d077424e1cbc141d05c2b
https://github.com/llvm/llvm-project/commit/51ce6c437fec1fe0170d077424e1cbc141d05c2b
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/EventHelper.cpp
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Fix error C2065: 'PATH_MAX': undeclared identifier
This should fix the Windows build.
Commit: d9b0571b5c408b3c699143a8870d04414351d28d
https://github.com/llvm/llvm-project/commit/d9b0571b5c408b3c699143a8870d04414351d28d
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 363bfd6090b0
Commit: 41cd6d2b1d6323bebfb20349d9f45b9c0ea75ada
https://github.com/llvm/llvm-project/commit/41cd6d2b1d6323bebfb20349d9f45b9c0ea75ada
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/bolt/lib/Passes/BUILD.gn
Log Message:
-----------
[gn build] Port 850b49297615
Commit: 823a597d2ad0a76e8d5278a789f37a07b393cd2a
https://github.com/llvm/llvm-project/commit/823a597d2ad0a76e8d5278a789f37a07b393cd2a
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/SetRuntimeCallAttributes.cpp
Log Message:
-----------
[flang] Workaround build failure.
https://lab.llvm.org/buildbot/#/builders/140/builds/17587
Looks like it is related to some specific version of the build compiler.
Commit: 4d536169010e4a1c70523edbdec5c6dfcbd49fda
https://github.com/llvm/llvm-project/commit/4d536169010e4a1c70523edbdec5c6dfcbd49fda
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/SetRuntimeCallAttributes.cpp
Log Message:
-----------
Revert "[flang] Workaround build failure."
This reverts commit 823a597d2ad0a76e8d5278a789f37a07b393cd2a.
Commit: 69cc16fb55089f624aba106a714aaf3f1a5504f5
https://github.com/llvm/llvm-project/commit/69cc16fb55089f624aba106a714aaf3f1a5504f5
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/FIRBuilder.h
M flang/include/flang/Optimizer/Builder/Runtime/RTBuilder.h
M flang/include/flang/Optimizer/Dialect/FIRDialect.td
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
R flang/include/flang/Optimizer/Transforms/RuntimeFunctions.inc
M flang/lib/Lower/IO.cpp
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
R flang/lib/Optimizer/Transforms/GenRuntimeCallsForTest.cpp
R flang/lib/Optimizer/Transforms/SetRuntimeCallAttributes.cpp
M flang/test/Driver/mlir-pass-pipeline.f90
M flang/test/Fir/basic-program.fir
M flang/test/Lower/array-temp.f90
R flang/test/Transforms/set-runtime-call-attributes.fir
R flang/test/Transforms/verify-known-runtime-functions.fir
R flang/test/Utils/generate-checks-for-runtime-funcs.py
Log Message:
-----------
Revert "[flang] Set LLVM specific attributes to fir.call's of Fortran runtime. (#128093)"
This reverts commit 36fdeb2aded08a776fcffefa73cb7667e7fc6c2d.
Commit: ab9cd53b86e84cc2db47d312232de4789c15adc4
https://github.com/llvm/llvm-project/commit/ab9cd53b86e84cc2db47d312232de4789c15adc4
Author: Malavika Samak <malavika.samak at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-array.cpp
Log Message:
-----------
[Wunsafe-buffer-usage] False positives for & expression indexing constant size array (arr[anything & 0]) (#112284)
Do not warn when a constant sized array is indexed with an expression
that contains bitwise and operation
involving constants and it always results in a bound safe access.
(rdar://136684050)
---------
Co-authored-by: MalavikaSamak <malavika2 at apple.com>
Commit: 4ac43b541c067e6b888948900d01521e58a00eca
https://github.com/llvm/llvm-project/commit/4ac43b541c067e6b888948900d01521e58a00eca
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Restrict widest induction type to be IntegerType (NFC) (#128173)
As the name of the function suggests, convertPointerToIntegerType should
return an IntegerType instead of a Type, and should only ever be called
with integer or ptr type. Fix the callers getWiderType, and
addInductionPhi to narrow the type of WidestIndTy to IntegerType,
stripping unclear casts. While at it, rename convertPointerToIntegerType
and getWiderType for clarity.
Commit: be5c66d97d7977bd9fa31b1a0e78196ecbb6e52b
https://github.com/llvm/llvm-project/commit/be5c66d97d7977bd9fa31b1a0e78196ecbb6e52b
Author: Michael Spencer <bigcheesegs at gmail.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M clang/lib/Serialization/ModuleManager.cpp
M clang/test/Modules/explicit-build.cpp
Log Message:
-----------
[clang] Improve module out of date error message (#128103)
When a pcm file has a different size or modification time than it had
when it was written to another module's IMPORT table Clang emits:
`<pcm> is out of date and needs to be rebuilt: module file out of date`
This is difficult to understand what's happening because there are a lot
of reasons that a module file can be out of date. This changes the
latter part of that message to:
`module file has a different size or mtime than expected`
Which makes it clearer what the issue is. For future work it would be
nice if a more detailed explanation of the issue could be emitted as a
note instead.
Commit: 607a1f2ace77fffb67a1f62df5ac6caa1c568f51
https://github.com/llvm/llvm-project/commit/607a1f2ace77fffb67a1f62df5ac6caa1c568f51
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
A clang/include/clang/CIR/Passes.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/IR/func.cir
A clang/test/CIR/IR/global.cir
M clang/test/CMakeLists.txt
M clang/test/lit.cfg.py
M clang/tools/CMakeLists.txt
A clang/tools/cir-opt/CMakeLists.txt
A clang/tools/cir-opt/cir-opt.cpp
Log Message:
-----------
[CIR] Add cir-opt tool to exercise CIR dialect parsing (#128254)
We need to be able to read in and parse files using the ClangIR dialect
in order to test this part of the functionality.
This change adds the minimum cir-opt tool needed to read and parse cir
files and write them back to text. This tool will later be extended to
add features for lowering from CIR to other MLIR dialects and to run CIR
passes as they are upstreamed.
Commit: 4c9e14b3ad64b04addc9a706663ac9ac129d7451
https://github.com/llvm/llvm-project/commit/4c9e14b3ad64b04addc9a706663ac9ac129d7451
Author: Sumanth Gundapaneni <sumanth.gundapaneni at amd.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
Log Message:
-----------
[AMDGPU] Update PromoteAlloca to handle GEPs with variable offset. (#122342)
In case of variable offset of a GEP that can be optimized out, promote
alloca is updated to use the refereshed index to avoid an assertion.
Issue found by fuzzer.
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: 82264d23a1cc2ad9334f9a277cb92043a8bac446
https://github.com/llvm/llvm-project/commit/82264d23a1cc2ad9334f9a277cb92043a8bac446
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/CMakeLists.txt
A lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
A lldb/tools/lldb-dap/Handler/StepInRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/StepInTargetsRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/StepOutRequestHandler.cpp
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Refactor stepping related request handlers (NFC) (#128453)
Continuation of the work started in #128262.
Commit: 0182b23fe144d9b8a539f2b9d8fa5741eb1223a2
https://github.com/llvm/llvm-project/commit/0182b23fe144d9b8a539f2b9d8fa5741eb1223a2
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/tools/lldb-dap/BUILD.gn
Log Message:
-----------
[gn build] Port 82264d23a1cc
Commit: 9fac59a0db7c7adaa354a47df385cd35d761ec77
https://github.com/llvm/llvm-project/commit/9fac59a0db7c7adaa354a47df385cd35d761ec77
Author: Sarah Spall <sarahspall at microsoft.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M clang/include/clang/Basic/LangOptions.h
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaType.cpp
A clang/test/CodeGenHLSL/BasicFeatures/ArrayReturn.hlsl
Log Message:
-----------
[HLSL] Allow arrays to be returned by value in HLSL (#127896)
Enable Arrays to be returned in HLSL, and a test for this.
Closes #126568
Commit: e55f1a7ef8d3e698144b013c8715a18c88912d81
https://github.com/llvm/llvm-project/commit/e55f1a7ef8d3e698144b013c8715a18c88912d81
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/RISCV/math-function.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/spillcost.ll
Log Message:
-----------
[SLP] Add test for getSpillCost fix
Commit: 8ce17c15577d223e14b62f9198d4b2ae9856b9fb
https://github.com/llvm/llvm-project/commit/8ce17c15577d223e14b62f9198d4b2ae9856b9fb
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M clang/include/clang/AST/DeclCXX.h
M clang/lib/AST/CXXInheritance.cpp
Log Message:
-----------
[clang][NFC] Remove CXXRecordDecl::lookupDependentName() and its helpers (#128392)
This function has been superseded by
HeuristicResolver::lookupDependentName(), which implements the same
heuristics and more.
Porting note for any out-of-tree callers:
```
RD->lookupDependentName(Name, Filter);
```
can be replaced with:
```
HeuristicResolver(RD->getASTContext())->lookupDependentName(Name, Filter);
```
Commit: 988480323d5ef9bb658f13ac598d4ce2aa23c782
https://github.com/llvm/llvm-project/commit/988480323d5ef9bb658f13ac598d4ce2aa23c782
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/CMakeLists.txt
A lldb/tools/lldb-dap/Handler/CompileUnitsRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/ModulesRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
A lldb/tools/lldb-dap/Handler/TestGetTargetBreakpointsRequestHandler.cpp
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Refactor custom & testing related request handlers (NFC) (#128549)
Continuation of the work started in
https://github.com/llvm/llvm-project/pull/128262. Builds on top of
#128453.
Commit: cec35077025da73bd2d8bf78d5bb62c43f3ccd0a
https://github.com/llvm/llvm-project/commit/cec35077025da73bd2d8bf78d5bb62c43f3ccd0a
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M clang/docs/analyzer/checkers.rst
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLocalVarsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
A clang/test/Analysis/Checkers/WebKit/objc-mock-types.h
A clang/test/Analysis/Checkers/WebKit/unretained-local-vars-arc.mm
A clang/test/Analysis/Checkers/WebKit/unretained-local-vars.mm
Log Message:
-----------
[alpha.webkit.UnretainedLocalVarsChecker] Add a checker for local variables to NS and CF types. (#127554)
This PR adds alpha.webkit.UnretainedLocalVarsChecker by generalizing
RawPtrRefLocalVarsChecker. It checks local variables to NS or CF types
are guarded with a RetainPtr or not. The new checker is effective for NS
and CF types in Objective-C++ code without ARC, and it's effective for
CF types in code with ARC.
Commit: 55c76ea391225bce1e0b1c1eba57bbd846c671a1
https://github.com/llvm/llvm-project/commit/55c76ea391225bce1e0b1c1eba57bbd846c671a1
Author: Kristof Beyls <kristof.beyls at arm.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M bolt/test/binary-analysis/AArch64/gs-pacret-autiasp.s
M bolt/test/binary-analysis/AArch64/gs-pacret-multi-bb.s
Log Message:
-----------
[BOLT] pacret-scanner: fix regression tests... (#128565)
by making the regex to match basic block names more general. See failing
test case that was reported on some system in comment
https://github.com/llvm/llvm-project/pull/122304#issuecomment-2679460678
These test cases were introduced in PR #122304, commit
850b49297615a613ac83adca2c9cf823a4b8ef95 .
Commit: b335d5a8303250cb49901ecae7570adf61abbd3c
https://github.com/llvm/llvm-project/commit/b335d5a8303250cb49901ecae7570adf61abbd3c
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/tools/lldb-dap/BUILD.gn
Log Message:
-----------
[gn build] Port 988480323d5e
Commit: f63c5f36c3e390fa43ba91c6d7812d0439b5203a
https://github.com/llvm/llvm-project/commit/f63c5f36c3e390fa43ba91c6d7812d0439b5203a
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M mlir/test/Integration/Dialect/MemRef/memref_abi.c
Log Message:
-----------
Revert "[mlir] Fix integration test when `%host_cc` path contains spaces" (#128573)
Reverts llvm/llvm-project#128439
Builtbot are broken, see:
https://lab.llvm.org/buildbot/#/builders/138/builds/10710
Commit: 53c08dfc18163ab50a94da344fd93fddac179495
https://github.com/llvm/llvm-project/commit/53c08dfc18163ab50a94da344fd93fddac179495
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/WindowsManifest/WindowsManifestMerger.cpp
Log Message:
-----------
[llvm-mt] Use XmlDeleter to free xmlFreeDoc (#128472)
Fixes memory leak on error in llvm-mt.
Previous https://reviews.llvm.org/D37321 missed this spot.
Commit: 23aca2f88dd5d2447e69496c89c3ed42a56f9c31
https://github.com/llvm/llvm-project/commit/23aca2f88dd5d2447e69496c89c3ed42a56f9c31
Author: Zequan Wu <zequanwu at google.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/DebugInfo/DWARF/DWARFContext.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
M llvm/test/tools/llvm-symbolizer/skip-line-zero.s
M llvm/test/tools/llvm-symbolizer/sym-verbose.test
Log Message:
-----------
Revert "Symbolize line zero as if no source info is available (#124846)"
This commit creates an inconsistency on `__sanitizer_symbolize_pc` API. Before this change, this API always uses the filename from debug info when the line number is 0. After this change, the filename becomes invalid when line number is 0. The sanitizer might fall back to use base filename from symbol table. So, this API may return either `??:0` or `{filename from symbol table}:0` depending on if the symbol table has the filename for it. Make sure this inconsistency is resolved before relanding the commit.
Commit: e063365a9732551b2d7b6c2b0d81e79d224a61e8
https://github.com/llvm/llvm-project/commit/e063365a9732551b2d7b6c2b0d81e79d224a61e8
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/WindowsManifest/WindowsManifestMerger.cpp
Log Message:
-----------
Revert "[llvm-mt] Use XmlDeleter to free xmlFreeDoc" (#128578)
Reverts llvm/llvm-project#128472
Breaks build bots.
Commit: 6c61c557569a1def56747c7b7db1926c538ec576
https://github.com/llvm/llvm-project/commit/6c61c557569a1def56747c7b7db1926c538ec576
Author: Kristof Beyls <kristof.beyls at arm.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M bolt/test/binary-analysis/AArch64/gs-pacret-autiasp.s
Log Message:
-----------
[BOLT] pacret-scanner: fix regression test failure (#128576)
... which is caused by a seemingly recent change in BOLTs basic block
calculation, where function calls seem to be ending basic blocks? I
don't have a pointer to the commit that caused this change. I'll be
looking for that later. For now, I'm trying to get the regression tests
passing again.
Commit: 1e85e5abb327317777cfe0d5d97d6dc211dbc1e3
https://github.com/llvm/llvm-project/commit/1e85e5abb327317777cfe0d5d97d6dc211dbc1e3
Author: Sam Clegg <sbc at chromium.org>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M clang/lib/Driver/ToolChains/WebAssembly.cpp
M clang/test/Driver/wasm-toolchain.c
Log Message:
-----------
[clang][WebAssembly] Always have `-pthread` imply `--shared-memory` linker flag (#127939)
Unlike `-lpthread` this flag should not be suppressed by `-nostdlib`.
Commit: 9bfe48695ed837bdc788b1ba0e877726ce83befb
https://github.com/llvm/llvm-project/commit/9bfe48695ed837bdc788b1ba0e877726ce83befb
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M libc/cmake/modules/LLVMLibCArchitectures.cmake
Log Message:
-----------
[libc] Initial support for parsing SPIR-V for GPU libc (#128570)
Summary:
Some day we'd like to support this, add some initial support for parsing
the triple so it will at least attempt to build.
Commit: bef4e5204adae9aa7d7f3268a4cf75cd0394c0d7
https://github.com/llvm/llvm-project/commit/bef4e5204adae9aa7d7f3268a4cf75cd0394c0d7
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/test/Lower/CUDA/cuda-device-proc.cuf
Log Message:
-----------
[flang][cuda] Fix type mismatch in atomiccas (#128548)
Commit: 47822c80c1b259973c29521315e3c355d1d553ad
https://github.com/llvm/llvm-project/commit/47822c80c1b259973c29521315e3c355d1d553ad
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Clarify that the pointer after an object must be valid. (#127892)
In some places, we rely on the assumption that the pointer after the
object must also be valid and not overflow, but it does not seem to be
spelled out clearly in LangRef, unless I missed a reference.
The GetElementPtr section mentions that the maximum object size is half
the pointer index type space, but then the pointer past the object may
wrap. Clarify that the pointer after the object must also be valid.
This should match Alive2's semantics:
https://alive2.llvm.org/ce/z/Dk8QFL
(https://github.com/AliveToolkit/alive2/blob/master/tools/transform.cpp#L1288)
PR: https://github.com/llvm/llvm-project/pull/127892
Commit: 1b15a89a23c631a8e2d096dad4afe456970572c0
https://github.com/llvm/llvm-project/commit/1b15a89a23c631a8e2d096dad4afe456970572c0
Author: Zequan Wu <zequanwu at google.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M offload/test/sanitizer/kernel_crash_many.c
M offload/test/sanitizer/kernel_trap.c
M offload/test/sanitizer/kernel_trap.cpp
M offload/test/sanitizer/kernel_trap_many.c
Log Message:
-----------
Revert "[Offload] Fix assumptions on symbols after #124846 (#126238)"
The dependency commit was reverted at https://github.com/llvm/llvm-project/commit/23aca2f88dd5d2447e69496c89c3ed42a56f9c31. Reverting this as well.
Commit: d3623194044452e2f1b4e81c213bc8cbbe49c2a8
https://github.com/llvm/llvm-project/commit/d3623194044452e2f1b4e81c213bc8cbbe49c2a8
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/CMakeLists.txt
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
A lldb/tools/lldb-dap/Handler/DataBreakpointInfoRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
A lldb/tools/lldb-dap/Handler/SetBreakpointsRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/SetDataBreakpointsRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/SetExceptionBreakpointsRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/SetFunctionBreakpointsRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/SetInstructionBreakpointsRequestHandler.cpp
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Refactor breakpoint related request handlers (NFC) (#128550)
Continuation of the work started in #128262. Builds on top of #128549.
Commit: a018788687c8715b0abbd24cb3258d2dd1d1740d
https://github.com/llvm/llvm-project/commit/a018788687c8715b0abbd24cb3258d2dd1d1740d
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/tools/lldb-dap/BUILD.gn
Log Message:
-----------
[gn build] Port d36231940444
Commit: df14dbd8750fba7851a3fd8878db3692c20a28d1
https://github.com/llvm/llvm-project/commit/df14dbd8750fba7851a3fd8878db3692c20a28d1
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
M llvm/lib/Target/DirectX/DirectXInstrInfo.h
M llvm/lib/Target/DirectX/DirectXRegisterInfo.cpp
M llvm/lib/Target/DirectX/DirectXRegisterInfo.h
M llvm/lib/Target/DirectX/DirectXSubtarget.h
Log Message:
-----------
[DirectX] Fix build breaks (#128556)
1. Fix build break caused by #126772 by adding `writeDISubrangeType`
stub to `DXILBitcodeWriter.cpp`
2. Fix build break caused by #128480 by adding implementation of pure
virtual method `TargetSubtargetInfo::getRegisterInfo`
Commit: baa77e30f0f2599763f3d6142cc67a96d6e6709b
https://github.com/llvm/llvm-project/commit/baa77e30f0f2599763f3d6142cc67a96d6e6709b
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[LV] Remove some redundant casts (NFC).
Commit: eabe2eb933556bf3e0db0d2d98e96f962bde14dc
https://github.com/llvm/llvm-project/commit/eabe2eb933556bf3e0db0d2d98e96f962bde14dc
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M libc/CMakeLists.txt
M llvm/runtimes/CMakeLists.txt
Log Message:
-----------
[libc] Remove special full build handling for GPU (#128572)
Summary:
Currently we default to non-fullbuild for all targets, but realistically
we should do this depending on the target OS. Some OS's like the GPU or
upcoming UEFI have no existing hosted system, so they cannot be built
with an overlay build. These are already errors so there's no reason to
complicate things and require passing it in through the runtimes build.
Commit: e5ce0304335dc1cae6856c880d1d4e14dcf8265d
https://github.com/llvm/llvm-project/commit/e5ce0304335dc1cae6856c880d1d4e14dcf8265d
Author: Charitha Saumya <136391709+charithaintc at users.noreply.github.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
R mlir/test/Dialect/XeGPU/XeGPUOps.mlir
M mlir/test/Dialect/XeGPU/invalid.mlir
A mlir/test/Dialect/XeGPU/ops.mlir
Log Message:
-----------
[mlir][xegpu] Improve XeGPU op verification logic for SIMT flavor and update tests. (#127920)
This PR adds required changes for XeGPU ops to support the SIMT
distribution.
1. Adds verification logic for SIMT flavor for load_nd, store_nd, dpas,
load_gather and store_scatter ops.
2. Adds test cases to cover the SIMT version of these ops along with
their VC counter parts.
---------
Co-authored-by: Artem Kroviakov <71938912+akroviakov at users.noreply.github.com>
Commit: 38d7cf1a81431933b732350b0141790ca94aa20a
https://github.com/llvm/llvm-project/commit/38d7cf1a81431933b732350b0141790ca94aa20a
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/CMakeLists.txt
A lldb/tools/lldb-dap/Handler/DisassembleRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/LocationsRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/PauseRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/ReadMemoryRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
A lldb/tools/lldb-dap/Handler/ScopesRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/SetVariableRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/SourceRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/StackTraceRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/ThreadsRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/VariablesRequestHandler.cpp
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Refactor remaining request handlers (NFC)Remaining request handlers (#128551)
Continuation of the work started in #128262. Builds on top of #128550.
Commit: b248817ad60953f500b070726a6c1973882bcb56
https://github.com/llvm/llvm-project/commit/b248817ad60953f500b070726a6c1973882bcb56
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/tools/lldb-dap/BUILD.gn
Log Message:
-----------
[gn build] Port 38d7cf1a8143
Commit: 31915248c06da7d132f642e4a2a3bb37df6fdab5
https://github.com/llvm/llvm-project/commit/31915248c06da7d132f642e4a2a3bb37df6fdab5
Author: Christopher Bate <cbate at nvidia.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M mlir/cmake/modules/CMakeLists.txt
Log Message:
-----------
[mlir] NFC: fix typos and improve commentary regarding generation of MLIRConfig.cmake (#127712)
Commit: d6ec32c8f25975ae31ec9ca7e67d942adadc3898
https://github.com/llvm/llvm-project/commit/d6ec32c8f25975ae31ec9ca7e67d942adadc3898
Author: Wael Yehia <wmyehia2001 at yahoo.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/fprofile-continuous.c
Log Message:
-----------
[profile] runtime counter relocation is needed on windows-msvc targets (#127858)
Continuous profile syncing is supported on windows, and it also relies on runtime counter relocation (based on this
test [1])
Thanks to @anhtuyenibm for pointing it out to me.
[1] https://github.com/llvm/llvm-project/blob/main/compiler-rt/test/profile/ContinuousSyncMode/runtime-counter-relocation.c
---------
Co-authored-by: Wael Yehia <wyehia at ca.ibm.com>
Commit: 0caa8f42be0b2d00527ad2d94144dcbb2a427605
https://github.com/llvm/llvm-project/commit/0caa8f42be0b2d00527ad2d94144dcbb2a427605
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/FIRBuilder.h
M flang/include/flang/Optimizer/Builder/Runtime/RTBuilder.h
M flang/include/flang/Optimizer/Dialect/FIRDialect.td
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
A flang/include/flang/Optimizer/Transforms/RuntimeFunctions.inc
M flang/lib/Lower/IO.cpp
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
A flang/lib/Optimizer/Transforms/GenRuntimeCallsForTest.cpp
A flang/lib/Optimizer/Transforms/SetRuntimeCallAttributes.cpp
M flang/test/Driver/mlir-pass-pipeline.f90
M flang/test/Fir/basic-program.fir
M flang/test/Lower/array-temp.f90
A flang/test/Transforms/set-runtime-call-attributes.fir
A flang/test/Transforms/verify-known-runtime-functions.fir
A flang/test/Utils/generate-checks-for-runtime-funcs.py
Log Message:
-----------
Reland "[flang] Set LLVM specific attributes to fir.call's of Fortran runtime. (#128093)"
This change is inspired by a case in facerec benchmark, where
performance
of scalar code may improve by about 6%@aarch64 due to getting rid of
redundant
loads from Fortran descriptors. These descriptors are corresponding
to subroutine local ALLOCATABLE, SAVE variables. The scalar loop nest
in LocalMove subroutine contains call to Fortran runtime IO functions,
and LLVM globals-aa analysis cannot prove that these calls do not modify
the globalized descriptors with internal linkage.
This patch sets and propagates llvm.memory_effects attribute for
fir.call
operations calling Fortran runtime functions. In particular, it tries
to set the Other memory effect to NoModRef. The Other memory effect
includes accesses to globals and captured pointers, so we cannot set
it for functions taking Fortran descriptors with one exception
for calls where the Fortran descriptor arguments are all null.
As long as different calls to the same Fortran runtime function may have
different attributes, I decided to attach the attributes to the calls
rather than functions. Moreover, attaching the attributes to func.func
will require propagating these attributes to llvm.func, which is not
happening right now.
In addition to llvm.memory_effects, the new pass sets llvm.nosync
and llvm.nocallback attributes that may also help LLVM alias analysis
(e.g. see #127707). These attributes are ignored currently.
I will support them in LLVM IR dialect in a separate patch.
I also added another pass for developers to be able to print
declarations/calls of all Fortran runtime functions that are recognized
by the attributes setting pass. It should help with maintenance
of the LIT tests.
Commit: 594919c263122e1d0468dfecee6eb5962e892b44
https://github.com/llvm/llvm-project/commit/594919c263122e1d0468dfecee6eb5962e892b44
Author: Igor Wodiany <igor.wodiany at imgtec.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.h
M mlir/test/Target/SPIRV/selection.mlir
A mlir/test/Target/SPIRV/selection.spv
M mlir/test/lit.cfg.py
Log Message:
-----------
[mlir][spirv] Split conditional basic blocks during deserialization (#127639)
With the current design some of the values are sank into a selection
region, despite them being also used outside that region. This is
because the current deserializer logic sinks the entire basic block
containing a conditional branch forming a header of a selection
construct, without accounting for some values being used outside. This
manifests as (for example):
```
<unknown>:0: error: 'spirv.Variable' op failed control flow structurization: it has uses outside of the enclosing selection/loop construct
<unknown>:0: note: see current operation: %0 = "spirv.Variable"()<{storage_class = #spirv.storage_class<Function>}> : () -> !spirv.ptr<vector<4xf32>, Function>
```
The proposed solution to this problem is to split the conditional basic
block into two, one block containing just the conditional branch, and
other the rest of instructions. By doing this, the logic that structures
selection regions, only sinks the comparison, keeping the rest of
instructions outside the selection region.
A SPIR-V test is required, as the problem can happen only during
deserialization and cannot be tested with `--test-spirv-roundtrip`. An
MLIR test exhibiting the problematic behaviour would be an incorrect
MLIR in the first place.
This solution is proposed as an alternative to an unfinished PR #123371,
that is unlikely to be merged in the foreseeable future, as the author
"stepped away from this for a time being". There is also a Discourse
thread:
https://discourse.llvm.org/t/spir-v-uses-outside-the-selection-region/84494
that tried to solicit some feedback on the topic.
Commit: 36b339b84a98afe7bdf470747a776d0d5f348b64
https://github.com/llvm/llvm-project/commit/36b339b84a98afe7bdf470747a776d0d5f348b64
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/test/Lower/CUDA/cuda-device-proc.cuf
Log Message:
-----------
[flang][cuda] Relax assertion for atomicexch (#128582)
atomicexch interfaces accepts also floating point numbers. Relax the
assertion so float are also accepted.
Commit: 6b444271a011c4e3c92a62aaed9347ad508843a2
https://github.com/llvm/llvm-project/commit/6b444271a011c4e3c92a62aaed9347ad508843a2
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/WindowsManifest/WindowsManifestMerger.cpp
Log Message:
-----------
Reland "[llvm-mt] Use XmlDeleter to free xmlFreeDoc"" (#128579)
Reverts llvm/llvm-project#128578 to reland llvm/llvm-project#128472.
Commit: 00a0b0be4b180a9458f477a8bf76d2377056d9d1
https://github.com/llvm/llvm-project/commit/00a0b0be4b180a9458f477a8bf76d2377056d9d1
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/test/Integration/Dialect/MemRef/memref_abi.c
M mlir/test/lit.cfg.py
Log Message:
-----------
Reland [mlir] Fix integration test when %host_cc path contains spaces (#128542)
Reland https://github.com/llvm/llvm-project/pull/128439
Some builders have spaces at the end of the `host_cc` path.
Commit: e8f1623a223adf5446e9999403aa6ce827a9b6dc
https://github.com/llvm/llvm-project/commit/e8f1623a223adf5446e9999403aa6ce827a9b6dc
Author: John Harrison <harjohn at google.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M lldb/test/API/tools/lldb-dap/output/TestDAP_output.py
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
Log Message:
-----------
[lldb-dap] Addressing the order of events during disconnect to flush output. (#128583)
The TestDAP_ouput test is flaky due to the order of events during
shutdown. We were stopping the output and error handle redirection after
we finished the disconnect request, which can cause us to miss output
events due to timing. Moving when we stop the redirection to ensure we
have consistent output prior to disconnect responding.
Fixes #128567
Commit: 911e94c6516926b462bc6d1d4a77dcc701b7e3db
https://github.com/llvm/llvm-project/commit/911e94c6516926b462bc6d1d4a77dcc701b7e3db
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/BreakpointLocationsHandler.cpp
M lldb/tools/lldb-dap/Handler/CompileUnitsRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/CompletionsHandler.cpp
M lldb/tools/lldb-dap/Handler/ConfigurationDoneRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/ContinueRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/DataBreakpointInfoRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/DisassembleRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/DisconnectRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/EvaluateRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/ExceptionInfoRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/InitializeRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/LaunchRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/LocationsRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/ModulesRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/PauseRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/ReadMemoryRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Handler/RestartRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/ScopesRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/SetBreakpointsRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/SetDataBreakpointsRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/SetExceptionBreakpointsRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/SetFunctionBreakpointsRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/SetInstructionBreakpointsRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/SetVariableRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/SourceRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/StackTraceRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/StepInRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/StepInTargetsRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/StepOutRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/TestGetTargetBreakpointsRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/ThreadsRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/VariablesRequestHandler.cpp
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Finish refactoring the request handlers (NFC) (#128553)
Completes the work started in #128262. This PR removes the
old way of register request handlers with callbacks and makes
the operator const.
Commit: 6d0cfbc9c0e25f9e652f5f8b3bca2d7a0768619e
https://github.com/llvm/llvm-project/commit/6d0cfbc9c0e25f9e652f5f8b3bca2d7a0768619e
Author: Henry Jiang <h243jian at uwaterloo.ca>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
A llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll
Log Message:
-----------
[PPC] Implement `areInlineCompatible` (#126562)
After the default implementation swap from
https://github.com/llvm/llvm-project/pull/117493, where
`areInlineCompatible` checks if the callee features are a subset of
caller features. This is not a safe assumption in general on PPC. We
fallback to check for strict feature set equality for now, and see what
improvements we can make.
Commit: 162eb32e747819683d747de29d7fad99f1279063
https://github.com/llvm/llvm-project/commit/162eb32e747819683d747de29d7fad99f1279063
Author: John Harrison <harjohn at google.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
A lldb/test/API/tools/lldb-dap/source/Makefile
A lldb/test/API/tools/lldb-dap/source/TestDAP_source.py
A lldb/test/API/tools/lldb-dap/source/main.c
M lldb/tools/lldb-dap/Handler/SourceRequestHandler.cpp
M lldb/tools/lldb-dap/JSONUtils.cpp
Log Message:
-----------
[lldb-dap] Add 'source' references to stack frames without source files. (#128268)
This adds 'source' references to all stack frames. When opening a stack
frame users will see the disassembly of the frame if the source is not
available.
This works around the odd behavior of navigating frames without the
VSCode disassembly view open, which causes 'step' to step in the first
frame with a source instead of the active frame.
This fixes #128260
Old behavior:
https://github.com/user-attachments/assets/3f40582d-ac96-451a-a5ae-498a323bf30e
New behavior:
https://github.com/user-attachments/assets/3a3f9ac6-3e6c-4795-9bb2-1132b3916b6f
---------
Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
Commit: f6a30021249c3b6aac20f108559915e74943540f
https://github.com/llvm/llvm-project/commit/f6a30021249c3b6aac20f108559915e74943540f
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Remove unused headers (NFC)
Commit: 1824bb47c2b5874d92cc5456c57d434ea39739e7
https://github.com/llvm/llvm-project/commit/1824bb47c2b5874d92cc5456c57d434ea39739e7
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M offload/test/sanitizer/kernel_trap.c
Log Message:
-----------
[Offload][OpenMP] Fix check-prefix (#128599)
Commit: fc09550bf4982253a93088bf1668f7a917584464
https://github.com/llvm/llvm-project/commit/fc09550bf4982253a93088bf1668f7a917584464
Author: Ali Raeisdanaei <57504158+aliraeisdanaei at users.noreply.github.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/utils/mlgo-utils/mlgo/corpus/combine_training_corpus.py
M llvm/utils/mlgo-utils/mlgo/corpus/extract_ir.py
A llvm/utils/mlgo-utils/mlgo/corpus/flags.py
Log Message:
-----------
[MLGO] Refactored verbosity flag in mlgo-utils to common location (#128541)
add common lib file to setup arguments for parser #107898
This is my first pull request to LLVM, so I would appreciate your
feedback :)
Fixes #107898.
---------
Co-authored-by: Aiden Grossman <agrossman154 at yahoo.com>
Commit: ccbb8882ac75e73e23f31ad60588a2914ebeef04
https://github.com/llvm/llvm-project/commit/ccbb8882ac75e73e23f31ad60588a2914ebeef04
Author: oltolm <oleg.tolmatcev at gmail.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M lldb/source/API/SBFrame.cpp
M lldb/test/API/python_api/run_locker/TestRunLocker.py
Log Message:
-----------
[lldb] do not show misleading error when there is no frame (#119103)
I am using VSCode with the official vscode-lldb extension. When I try to
list the breakpoints in the debug console get the message:
```
br list
can't evaluate expressions when the process is running.
```
I know that this is wrong and you need to use
```
`br list
(lldb) br list
No breakpoints currently set.
```
but the error message is misleading. I cleaned up the code and now the
error message is
```
br list
sbframe object is not valid.
```
which is still not perfect, but at least it's not misleading.
Commit: 49c31201278ae5949694ed78b69ffbbca6a1826a
https://github.com/llvm/llvm-project/commit/49c31201278ae5949694ed78b69ffbbca6a1826a
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
Log Message:
-----------
[MachineSched] Add a first valid reason [nfc]
For debugging, distinguish the first valid candidate encountered and
a preference decision driven by node number.
Commit: 305d2738944f77f8defefe79217120bb8aafab75
https://github.com/llvm/llvm-project/commit/305d2738944f77f8defefe79217120bb8aafab75
Author: Deric Cheung <cheung.deric at gmail.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsSPIRV.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Headers/hlsl/hlsl_detail.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Sema/SemaSPIRV.cpp
A clang/test/CodeGenHLSL/builtins/reflect.hlsl
A clang/test/CodeGenSPIRV/Builtins/reflect.c
A clang/test/SemaHLSL/BuiltIns/reflect-errors.hlsl
A clang/test/SemaSPIRV/BuiltIns/reflect-errors.c
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reflect.ll
A llvm/test/CodeGen/SPIRV/opencl/reflect-error.ll
Log Message:
-----------
Reland "[HLSL] Implement the reflect HLSL function" (#125599)
This PR relands #122992.
A reland was attempted before (#123853), but it [failed to pass the
`sanitizer-aarch64-linux-bootstrap-hwasan`
buildbot](https://github.com/llvm/llvm-project/pull/123853#issuecomment-2608389396)
due to the test `llvm/test/CodeGen/SPIRV/opencl/reflect-error.ll`
The issue has since been patched thanks to @vitalybuka, so the PR is
safe to reland without any changes.
See
https://github.com/llvm/llvm-project/pull/125599#discussion_r1966650839
and
https://github.com/llvm/llvm-project/pull/125599#discussion_r1966650839
Commit: 724b91b46783e68ff42fa0c9450449629cc47c65
https://github.com/llvm/llvm-project/commit/724b91b46783e68ff42fa0c9450449629cc47c65
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M flang/include/flang/Runtime/freestanding-tools.h
Log Message:
-----------
[flang-rt] Fixed freestanding memmove. (#128604)
Commit: 62ec7b8de97a197c2522177a52bdc78205579930
https://github.com/llvm/llvm-project/commit/62ec7b8de97a197c2522177a52bdc78205579930
Author: Vy Nguyen <vyng at google.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M lldb/include/lldb/Core/Telemetry.h
M lldb/source/Core/Telemetry.cpp
M lldb/unittests/Core/TelemetryTest.cpp
Log Message:
-----------
[LLDB][NFC]Renaming functions to be consistent with LLDB naming style (#128574)
Commit: a60e8a2c2579252d66a0656c387af29475e9b908
https://github.com/llvm/llvm-project/commit/a60e8a2c2579252d66a0656c387af29475e9b908
Author: Nikhil Kalra <nkalra at apple.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Bindings/Python/NanobindUtils.h
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/python/ir/operation.py
Log Message:
-----------
[mlir] Python: write bytecode to a file path (#127118)
The current `write_bytecode` implementation necessarily requires the
serialized module to be duplicated in memory when the python `bytes`
object is created and sent over the binding. For modules with large
resources, we may want to avoid this in-memory copy by serializing
directly to a file instead of sending bytes across the boundary.
Commit: 28002dd50fb7ec97da1770a11f9c6a99dd9aecb9
https://github.com/llvm/llvm-project/commit/28002dd50fb7ec97da1770a11f9c6a99dd9aecb9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
Log Message:
-----------
AMDGPU: Replace some undef pointer uses in test
Commit: 688064498a015e833bd24f5cd429462ca9126a54
https://github.com/llvm/llvm-project/commit/688064498a015e833bd24f5cd429462ca9126a54
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
R llvm/include/llvm/ExecutionEngine/Orc/JITLinkLazyCallThroughManager.h
Log Message:
-----------
[ORC] Remove unused header. NFC.
Commit: 253e11695ba8d77e4339d0c43758f192b149db1e
https://github.com/llvm/llvm-project/commit/253e11695ba8d77e4339d0c43758f192b149db1e
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.h
A llvm/include/llvm/ExecutionEngine/Orc/GetTapiInterface.h
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.cpp
A llvm/lib/ExecutionEngine/Orc/GetTapiInterface.cpp
A llvm/test/ExecutionEngine/JITLink/AArch64/Inputs/MachO_Foo.tbd
A llvm/test/ExecutionEngine/JITLink/AArch64/Inputs/MachO_main_ret_foo.s
A llvm/test/ExecutionEngine/JITLink/AArch64/MachO_weak_link.test
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
Log Message:
-----------
[ORC][llvm-jitlink] Add support for emulating ld64 -weak-lx / -weak_library.
Linking libraries in ld64 with -weak-lx / -weak_library causes all references
to symbols in those libraries to be made weak, allowing the librarie to be
missing at runtime.
This patch extends EPCDynamicLibrarySearchGenerator with support for emulating
this behavior: If an instance is constructed with an Allow predicate but no
dylib handle then all symbols matching the predicate are immediately resolved
to null.
The llvm-jitlink tool is updated with -weak-lx / -weak_library options for
testing. Unlike their ld64 counterparts these options take a TBD file as input,
and always resolve all exports in the TBD file to null.
Commit: c7101188fb3f17176e9152b1d733da6d7199d317
https://github.com/llvm/llvm-project/commit/c7101188fb3f17176e9152b1d733da6d7199d317
Author: apple-fcloutier <75502309+apple-fcloutier at users.noreply.github.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/FormatString.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/AttrImpl.cpp
M clang/lib/AST/FormatString.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaObjC.cpp
A clang/test/Sema/format-string-matches.c
M clang/test/Sema/format-strings.c
Log Message:
-----------
[clang] Implement __attribute__((format_matches)) (#116708)
This implements ``__attribute__((format_matches))``, as described in the
RFC:
https://discourse.llvm.org/t/rfc-format-attribute-attribute-format-like/83076
The ``format`` attribute only allows the compiler to check that a format
string matches its arguments. If the format string is passed
independently of its arguments, there is no way to have the compiler
check it. ``format_matches(flavor, fmtidx, example)`` allows the
compiler to check format strings against the ``example`` format string
instead of against format arguments. See the changes to AttrDocs.td in
this diff for more information.
Implementation-wise, this change subclasses CheckPrintfHandler and
CheckScanfHandler to allow them to collect specifiers into arrays, and
implements comparing that two specifiers are equivalent.
`checkFormatStringExpr` gets a new `ReferenceFormatString` argument that
is piped down when calling a function with the `format_matches`
attribute (and is `nullptr` otherwise); this is the string that the
actual format string is compared against.
Although this change does not enable -Wformat-nonliteral by default,
IMO, all the pieces are now in place such that it could be.
Commit: 8009c1fd81ad0b6ac65724d2b134a92db48f8fbf
https://github.com/llvm/llvm-project/commit/8009c1fd81ad0b6ac65724d2b134a92db48f8fbf
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
Log Message:
-----------
[LV][VPlan] Prevent calculate cost for skiped instructions in precomputeCosts(). (#127966)
Skip calculating instruction costs for exit conditions in
precomputeCosts() when it should be skipped.
Reported from:
https://github.com/llvm/llvm-project/issues/115744#issuecomment-2670479463
Godbolt for reduced test cases: https://godbolt.org/z/fr4YMeqcv
Commit: aa902a0380c167ceb68c998c25780945da99edfa
https://github.com/llvm/llvm-project/commit/aa902a0380c167ceb68c998c25780945da99edfa
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
Log Message:
-----------
[ORC] Add dependence on TextAPI to reflect changes in 253e11695ba.
Commit: 2c7780a96d24e1e23657057fb735e13e2ba5d2ce
https://github.com/llvm/llvm-project/commit/2c7780a96d24e1e23657057fb735e13e2ba5d2ce
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
Log Message:
-----------
[gn build] Port 253e11695ba8
Commit: 862595cab67b7fa71ea035e1090725bdf39d291b
https://github.com/llvm/llvm-project/commit/862595cab67b7fa71ea035e1090725bdf39d291b
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/lib/CodeGen/MachineBasicBlock.cpp
Log Message:
-----------
[MachineBasicBlock][NFC] Decouple SplitCriticalEdges from pass manager (#128151)
New clients should use this overload that accepts analyses directly.
Commit: 06f30792353a5d7bacc9110294db7cca49b4eafa
https://github.com/llvm/llvm-project/commit/06f30792353a5d7bacc9110294db7cca49b4eafa
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
A llvm/test/CodeGen/AMDGPU/si-fold-operands-commute-same-operands-assert.mir
Log Message:
-----------
AMDGPU: More consistently use the fold list instead of direct mutation (#127612)
There were 2 parallel fold check mechanisms, so consistently use the
fold list. The worklist management here is still not good. Other types
of folds are not using it, and we should probably rewrite the pass to
look more like peephole-opt.
This should be an alternative fix to skipping commute if the operands
are the same (#127562). The new test is still not broken as-is, but
demonstrates failures in a future patch.
Commit: 366daddfad9aa38ebb7d40055cf65f4ecb7dd6f9
https://github.com/llvm/llvm-project/commit/366daddfad9aa38ebb7d40055cf65f4ecb7dd6f9
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/include/clang/Serialization/ASTBitCodes.h
Log Message:
-----------
[Serialization] Update DECL_LAST
Address post commit review at
https://github.com/llvm/llvm-project/pull/119333#pullrequestreview-2637471908
Commit: b3c51db292f05cf89201911cbcca6cba83caadd6
https://github.com/llvm/llvm-project/commit/b3c51db292f05cf89201911cbcca6cba83caadd6
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
A llvm/test/CodeGen/AArch64/expand-load-got-pseudo.mir
Log Message:
-----------
[InstrRef] Preserve debug instr num in aarch64-expand-pseudo LOADgot expansion (#128081)
The aarch64-expand-pseudo pass expands the LOADgot instruction to an
ADRP instruction and a LDRXui instruction. If the LOADgot had a
debug-instr-number, the pass doesn't preserve this to the new expansion.
This patch fixes the issue by making sure the debug-instr-number is
correctly applied to the LDRXui instruction generated.
Commit: eab6f2d7a90cd9be7d622c7724d1131f9a9128b4
https://github.com/llvm/llvm-project/commit/eab6f2d7a90cd9be7d622c7724d1131f9a9128b4
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Affine/Analysis/LoopAnalysis.h
M mlir/lib/Dialect/Affine/Analysis/LoopAnalysis.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/test/Dialect/Affine/loop-fusion-4.mlir
M mlir/test/Examples/mlir-opt/loop_fusion_options.mlir
Log Message:
-----------
[MLIR][Affine] Fix fusion in the presence of cyclic deps in source nests (#128397)
Fixes: https://github.com/llvm/llvm-project/issues/61820
Fix affine fusion in the presence of cyclic deps in the source nest. In
such cases, the nest being fused can't be executed multiple times. Add a
utility to check for dependence cycles and use it in fusion. This fixes
both sibling as well as producer consumer fusion where nests with cyclic
dependences (typically reductions) were being in some cases incorrectly
fused in.
The test case also exercises/required a fix to the check for the
redundant computation being within the specified threshold.
Commit: 5deb2aa9eb454db266fb1ad38502dc6fac92ae48
https://github.com/llvm/llvm-project/commit/5deb2aa9eb454db266fb1ad38502dc6fac92ae48
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
Log Message:
-----------
AMDGPU: Make is.shared and is.private propagate poison (#128617)
Commit: d85685eb863641dce62a9f858ebcd6bab56c605b
https://github.com/llvm/llvm-project/commit/d85685eb863641dce62a9f858ebcd6bab56c605b
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.h
M llvm/test/CodeGen/AArch64/machine-latecleanup-inlineasm.mir
Log Message:
-----------
[AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (#128471)
This allows for testing AArch64 passes with the new pass manager.
Commit: b9cf684d7c39a9c36c562b67e6e53882f645fe74
https://github.com/llvm/llvm-project/commit/b9cf684d7c39a9c36c562b67e6e53882f645fe74
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/SCF/Transforms/Transforms.h
Log Message:
-----------
[mlir][scf] Fix typo of square brackets(NFC) (#128455)
Commit: 83ddb43cad3ee32b0df81aa641c4c0275334729d
https://github.com/llvm/llvm-project/commit/83ddb43cad3ee32b0df81aa641c4c0275334729d
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.h
M llvm/test/CodeGen/AArch64/machine-latecleanup-inlineasm.mir
Log Message:
-----------
Revert "[AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (#128471)"
This reverts commit d85685eb863641dce62a9f858ebcd6bab56c605b.
Multiple buildbot failures have been reported:
https://github.com/llvm/llvm-project/pull/128471
Commit: ecc7e6ce4cd57a614985e95daf7027918cb8723e
https://github.com/llvm/llvm-project/commit/ecc7e6ce4cd57a614985e95daf7027918cb8723e
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/lib/Sema/SemaConcept.cpp
M clang/test/SemaTemplate/concepts-lambda.cpp
Log Message:
-----------
[Clang] Handle instantiating captures in addInstantiatedCapturesToScope() (#128478)
addInstantiatedCapturesToScope() might be called when transforming a
lambda body. In this situation, it would look into all the lambda's
parents and figure out all the instantiated captures. However, the
instantiated captures are not visible from lambda's class decl until the
lambda is rebuilt (i.e. after the lambda body transform). So this patch
corrects that by also examining the LambdaScopeInfo, serving as a
workaround for not having deferred lambda body instantiation in Clang
20, to avoid regressing some real-world use cases.
Fixes #128175
Commit: 6e3b47597fabb8df8cf822331461cecbac907c6f
https://github.com/llvm/llvm-project/commit/6e3b47597fabb8df8cf822331461cecbac907c6f
Author: Shoaib Meenai <smeenai at fb.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M mlir/include/mlir/IR/OperationSupport.h
Log Message:
-----------
Reland "[mlir] Silence -Wdangling-assignment-gsl in OperationSupport.h"
This warning is causing lots of build spam when I use a recent Clang as
my host compiler. It's a potential false positive, so silence it until
https://github.com/llvm/llvm-project/issues/126600 is resolved.
Reland of https://github.com/llvm/llvm-project/pull/126140 with fix for
non-Clang compilers (the preprocessor doesn't short-circuit conditionals
the way I thought it did).
Commit: f58fde585775a7c25dc673076db914f8d1866081
https://github.com/llvm/llvm-project/commit/f58fde585775a7c25dc673076db914f8d1866081
Author: Hiroshi Yamauchi <56735936+hjyamauchi at users.noreply.github.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M clang/lib/Lex/HeaderSearch.cpp
Log Message:
-----------
Exclude RedirectingFileSystem with null OverlayFileDir in VFSUsage (#128267)
This is to avoid assertion failures like the following when
RedirectingFileSystem's are created and used outside
createVFSFromOverlayFiles.
```
Assertion failed: VFSUsage.size() == getHeaderSearchOpts().VFSOverlayFiles.size() && "A different number of RedirectingFileSystem's were present than " "-ivfsoverlay options passed to Clang!", file S:\SourceCache\llvm-project\clang\lib\Lex\HeaderSearch.cpp, line 162
```
Commit: e67cd152cf4d0344efba19985b005dae15e6bde0
https://github.com/llvm/llvm-project/commit/e67cd152cf4d0344efba19985b005dae15e6bde0
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/tools/llvm-size/llvm-size.cpp
Log Message:
-----------
[llvm-size] Initialize Radix to correct value (#128447)
Without the patch, invalid --radix, makes Radix to be 0, and result
in invalid format specifier ` %#7 `, instead of e.g ` %#7x `.
Commit: 9b298a1d3d2280c2b09f4a905d079bab008b5290
https://github.com/llvm/llvm-project/commit/9b298a1d3d2280c2b09f4a905d079bab008b5290
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
Log Message:
-----------
[WebAssembly] Use Register instead of unsigned. NFC
Commit: d7903c9f28bdfd17fcc2d5be1096c504b6a94ec1
https://github.com/llvm/llvm-project/commit/d7903c9f28bdfd17fcc2d5be1096c504b6a94ec1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
Log Message:
-----------
AMDGPU: Add more codegen tests for readfirstlane
Commit: f5d80c335d79d0b35741bfc762f8157a24f5491a
https://github.com/llvm/llvm-project/commit/f5d80c335d79d0b35741bfc762f8157a24f5491a
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/CTF/SymbolFileCTF.cpp
Log Message:
-----------
[lldb] Avoid Function::GetAddressRange in SymbolFileCTF (#128517)
SymbolFileCTF never creates discontinuous functions, so this is
technically NFC, but it takes us one step closer to removing the
deprecated API.
Commit: d3dae841c05c9447b665a8334aa3cfeac904d749
https://github.com/llvm/llvm-project/commit/d3dae841c05c9447b665a8334aa3cfeac904d749
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/test/CodeGen/NVPTX/ldu-ldg.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
Log Message:
-----------
[NVPTX] Switch to imm offset variants for LDG and LDU (#128270)
Commit: 3872503d6eb3eed7f2b2db13daad27307369f0be
https://github.com/llvm/llvm-project/commit/3872503d6eb3eed7f2b2db13daad27307369f0be
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M lldb/include/lldb/Symbol/UnwindPlan.h
M lldb/include/lldb/Target/RegisterContextUnwind.h
M lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
M lldb/source/Plugins/UnwindAssembly/x86/UnwindAssembly-x86.cpp
M lldb/source/Plugins/UnwindAssembly/x86/x86AssemblyInspectionEngine.cpp
M lldb/source/Symbol/FuncUnwinders.cpp
M lldb/source/Symbol/UnwindPlan.cpp
M lldb/source/Target/RegisterContextUnwind.cpp
M lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
M lldb/unittests/UnwindAssembly/PPC64/TestPPC64InstEmulation.cpp
M lldb/unittests/UnwindAssembly/x86/Testx86AssemblyInspectionEngine.cpp
Log Message:
-----------
[lldb] Don't hand out UnwindPlan::Row shared_ptrs (#128181)
The whole unwind plan is already stored in a shared pointer, and there's
no need to persist Rows individually. If there's ever a need to do that,
there are at least two options:
- copy the row (they're not that big, and they're being copied left and
right during construction already)
- use the shared_ptr subobject constructor to create a shared_ptr which
points to a Row but holds the entire unwind plan alive
This also changes all of the getter functions to return const Row
pointers, which is important for safety because all of these objects are
cached and potentially accessed from multiple threads. (Technically one
could hand out `shared_ptr<const Row>`s, but we don't have a habit of
doing that.)
As a next step, I'd like to remove the internal UnwindPlan usages of the
shared pointer, but I'm doing this separately to gauge feedback, and
also because the patch got rather big.
Commit: 6c17380ea896e9966645958ad3d76441cc25430c
https://github.com/llvm/llvm-project/commit/6c17380ea896e9966645958ad3d76441cc25430c
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M lldb/source/Target/StackFrame.cpp
M lldb/test/API/commands/frame/diagnose/dereference-function-return/TestDiagnoseDereferenceFunctionReturn.py
Log Message:
-----------
[lldb] Fix TestDiagnoseDereferenceFunctionReturn on linux (#128512)
The test was failing because it was looking up the immediate value from
the call instruction as a load address, whereas in fact it was a file
address. This worked on darwin because (with ASLR disabled) the two
addresses are generally the same. On linux, this depends on the build
mode, but with the default (PIE) build type, the two are never the same.
The test also fails on a mac with ASLR enabled.
This path fixes the code to look up the value as a file address.
Commit: 3083aea4441493b11b72218207564bf54516bf3e
https://github.com/llvm/llvm-project/commit/3083aea4441493b11b72218207564bf54516bf3e
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegacyLegalizerInfo.cpp
Log Message:
-----------
[GlobalISel] Avoid repeated hash lookups (NFC) (#128633)
Commit: 5088e1b435fd06de2bfccd3894dcc2f2c326630f
https://github.com/llvm/llvm-project/commit/5088e1b435fd06de2bfccd3894dcc2f2c326630f
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M lldb/source/Target/ThreadPlanStepRange.cpp
Log Message:
-----------
[lldb] Avoid Function::GetAddressRange in ThreadPlanStepRange::InSymbol (#128515)
The existing implementation would probably produce false positives for
discontinuous functions. I haven't tried reproducing it because setting
up discontinuous functions (and executing them, in particular) is pretty
complex and there's nothing particularly interesting happening here.
Commit: d254fa877f419e61e54709f0a6f2e891da893a60
https://github.com/llvm/llvm-project/commit/d254fa877f419e61e54709f0a6f2e891da893a60
Author: Michał Górny <mgorny at gentoo.org>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M flang-rt/CMakeLists.txt
Log Message:
-----------
[flang-rt] Make `FLANG_RT_INSTALL_RESOURCE_PATH` configurable (#128561)
Make it possible to change the path used to install flang-rt library.
This is particularly necessary for standalone builds, where the CMake
script currently hardwires the default clang install path, and therefore
is incorrect for distributions that override it. However, for
consistency I have made it configurable unconditionally, preserving the
current defaults.
Commit: 5114b9b386ca69058d19d9c3dac53b4b429c71a6
https://github.com/llvm/llvm-project/commit/5114b9b386ca69058d19d9c3dac53b4b429c71a6
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
A llvm/include/llvm/ExecutionEngine/Orc/GetDylibInterface.h
R llvm/include/llvm/ExecutionEngine/Orc/GetTapiInterface.h
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
A llvm/lib/ExecutionEngine/Orc/GetDylibInterface.cpp
R llvm/lib/ExecutionEngine/Orc/GetTapiInterface.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
Log Message:
-----------
[ORC][llvm-jitlink] Extend weak-linking emulation to real dylibs.
Commit 253e11695ba added support for emulating weak-linking against dylibs
that are (under the emulation) absent at runtime. This commit extends emulated
weak linking support to allow a real dylib to supply the interface (i.e.
-weak-lx / -weak_library can be pointed at a dylib, in which case they should
be read as "weak-link against this dylib, behavining as if it weren't actually
present at runtime").
Commit: ea4e19df53abb21a1f1df725e3728fabec902978
https://github.com/llvm/llvm-project/commit/ea4e19df53abb21a1f1df725e3728fabec902978
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
A llvm/test/CodeGen/PowerPC/llvm.sincos.ll
Log Message:
-----------
[SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (#128514)
Commit: 0087523e1a273b738b94a15547dbf308d0470283
https://github.com/llvm/llvm-project/commit/0087523e1a273b738b94a15547dbf308d0470283
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/test/Dialect/Affine/loop-fusion-4.mlir
Log Message:
-----------
[MLIR][Affine] Add missing check on fusion compute tolerance on a path (#128454)
When profitability analysis can't be performed, we should still be
respecting the compute tolerance specified. Refactor to pull the
additional computation factor computation and check.
Fixes: https://github.com/llvm/llvm-project/issues/54541
Commit: 49f60b4e098493f5128ba4276b3fbb985b0c61c8
https://github.com/llvm/llvm-project/commit/49f60b4e098493f5128ba4276b3fbb985b0c61c8
Author: Vikash Gupta <Vikash.Gupta at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
Log Message:
-----------
[AMDGPU][NFC] Added test for live-in CSR SGPR used partially giving MachineVerifier error (#126696)
Commit: 674dbcfe8f400db65f0d066ea638e977e8b82781
https://github.com/llvm/llvm-project/commit/674dbcfe8f400db65f0d066ea638e977e8b82781
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M libcxx/test/std/re/re.iter/re.tokiter/re.tokiter.comp/equal.pass.cpp
Log Message:
-----------
[libc++][NFC] Use TEST_STD_VER instead of _LIBCPP_STD_VER in re.tokiter.comp/equal.pass.cpp
Commit: d7211693af27760c939b6610f0c79a3ecd2790d2
https://github.com/llvm/llvm-project/commit/d7211693af27760c939b6610f0c79a3ecd2790d2
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] port e5ce0304335dc1cae6856c880d1d4e14dcf8265d
Commit: 60cc3af0d93ecb8bfc9d6bebc6cbc395df3bb4b6
https://github.com/llvm/llvm-project/commit/60cc3af0d93ecb8bfc9d6bebc6cbc395df3bb4b6
Author: Charitha Saumya <136391709+charithaintc at users.noreply.github.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
Log Message:
-----------
[mlir][xegpu] Fix bazel build failure (#128595)
Removes unnecessary headers creating wrong dependencies.
Commit: 275eeb56ddc4c236219f7df9618e7b03ff12e9fb
https://github.com/llvm/llvm-project/commit/275eeb56ddc4c236219f7df9618e7b03ff12e9fb
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
Log Message:
-----------
[gn build] Port 5114b9b386ca
Commit: 87dc245f3e65ee926081e575ffb2e57a32a91ba3
https://github.com/llvm/llvm-project/commit/87dc245f3e65ee926081e575ffb2e57a32a91ba3
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/MacOSKeychainAPIChecker.cpp
Log Message:
-----------
[analyzer] Partial revert of #127017 (#128642)
This assertion was hit, as reported by a user.
https://github.com/llvm/llvm-project/issues/128427#issuecomment-2677724438
Ideally, we would reduce and add a regression test for this, but I don't
have the bandwidth for it.
See the summary of the issue #128427 for the reproducer.
Commit: a4656bbc595839b57e6f021aa2a728b4cf321d54
https://github.com/llvm/llvm-project/commit/a4656bbc595839b57e6f021aa2a728b4cf321d54
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/ops.mlir
Log Message:
-----------
[mlir][tosa] Allow conv ops zero point to be variable (#128533)
The TOSA specification allows the zero point of conv ops to be variable
when the dynamic extension is being used, but information about which
extensions are in use is only known when the validation pass is run. A
variable zero point should be allowed in the conv ops verifiers.
In terms of testing, there didn't seem to be an existing set of tests
for the verifiers to add this check to, so the opportunity has been
taken to run the verifiers on the tests in `ops.mlir`. Since the conv2d
test there had variable zero points, this change in functionality is
being tested.
Signed-off-by: Luke Hutton <luke.hutton at arm.com>
Co-authored-by: Georgios Pinitas <georgios.pinitas at arm.com>
Commit: b36a18df96f9b8f206ec4b7f1036bdd4701c117e
https://github.com/llvm/llvm-project/commit/b36a18df96f9b8f206ec4b7f1036bdd4701c117e
Author: SivanShani-Arm <sivan.shani at arm.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
R llvm/test/CodeGen/AArch64/aarch64-build-attributes-all.ll
R llvm/test/CodeGen/AArch64/aarch64-build-attributes-bti.ll
R llvm/test/CodeGen/AArch64/aarch64-build-attributes-gcs.ll
R llvm/test/CodeGen/AArch64/aarch64-build-attributes-pac.ll
R llvm/test/CodeGen/AArch64/aarch64-build-attributes-pauthabi.ll
A llvm/test/CodeGen/AArch64/build-attributes-all.ll
A llvm/test/CodeGen/AArch64/build-attributes-bti.ll
A llvm/test/CodeGen/AArch64/build-attributes-gcs.ll
A llvm/test/CodeGen/AArch64/build-attributes-pac.ll
A llvm/test/CodeGen/AArch64/build-attributes-pauthabi.ll
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-all.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-bti.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-err-attrs.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-err-headers.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-gcs.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-none.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-numerical-tags.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-out-of-order.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-pac.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-private-subsections-err.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-private-subsections.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-aeabi-known.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-bti.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-err-attrs.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-err-headers.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-gcs.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-mixed.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-none.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-numerical-tags.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-out-of-order.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-pac.s
A llvm/test/MC/AArch64/build-attributes-asm-non_aeabi-err.s
A llvm/test/MC/AArch64/build-attributes-asm-non_aeabi.s
Log Message:
-----------
[AArch64][Build Attributes] Improve Parsing and Formatting (#126530)
- Removed assertion for duplicate values as adding them is valid.
- Fix parsing: reject strings for unknown tags, allow any value for
Tag_PAuth_Platform and Tag_PAuth_Schema.
- Print tags by using numbers with comments to reduce compiler-assembler
dependencies.
- Parsing error messages now only point to the symbol (^) instead of
printing it.
Commit: 547a8bc2365d9f1dc7bce52580a3ab64d69c80ed
https://github.com/llvm/llvm-project/commit/547a8bc2365d9f1dc7bce52580a3ab64d69c80ed
Author: Alcaro <floating at muncher.se>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/lib/Headers/cpuid.h
M clang/test/Headers/cpuid.c
Log Message:
-----------
[clang][x86] Support -masm=intel in cpuid.h (#127331)
Fixes #127271
Testing mostly done in Compiler Explorer https://godbolt.org/z/q1h3ohxr7
Commit: 85cf95876c4b21ee6ecd0253a2c9de0e90c4a521
https://github.com/llvm/llvm-project/commit/85cf95876c4b21ee6ecd0253a2c9de0e90c4a521
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
Log Message:
-----------
[AArch64] Improve codegen for some fixed-width partial reductions (#126529)
This patch teaches optimizeExtendOrTruncateConversion to bail out
if the user of a zero-extend is a partial reduction intrinsic
that we know will get lowered efficiently to a udot instruction.
Commit: 2a0946bc0dffca89d16cd9d5208ec9416ed8100e
https://github.com/llvm/llvm-project/commit/2a0946bc0dffca89d16cd9d5208ec9416ed8100e
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/GVN.cpp
Log Message:
-----------
[GVN][NFC] Match coding standards (#128683)
As per LLVM coding standards
"Variable names should be nouns (as they represent state).
The name should be camel case, and start with an upper
case letter (e.g. Leader or Boats)."
Commit: 7ff87af533a7acf47134eabe656702180d8ad171
https://github.com/llvm/llvm-project/commit/7ff87af533a7acf47134eabe656702180d8ad171
Author: Sergio Afonso <safonsof at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[MLIR][OpenMP] Host lowering of standalone distribute (#127817)
This patch adds MLIR to LLVM IR translation support for standalone
`omp.distribute` operations, as well as `distribute simd` through
ignoring SIMD information (similarly to `do/for simd`).
Co-authored-by: Dominik Adamski <dominik.adamski at amd.com>
Commit: 88163ca79cab1a9a2be1cfa71000f43fd642d91e
https://github.com/llvm/llvm-project/commit/88163ca79cab1a9a2be1cfa71000f43fd642d91e
Author: Sergio Afonso <safonsof at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Log Message:
-----------
[OpenMPIRBuilder] Add support for distribute-parallel-for/do constructs (#127818)
This patch adds codegen for `kmpc_dist_for_static_init` runtime calls,
used to support worksharing a single loop across teams and threads. This
can be used to implement `distribute parallel for/do` support.
Commit: 9fc2f786934599c51427cf6f581450ee951ece4a
https://github.com/llvm/llvm-project/commit/9fc2f786934599c51427cf6f581450ee951ece4a
Author: JaydeepChauhan14 <chauhan.jaydeep.ashwinbhai at intel.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/fp128-libcalls.ll
M llvm/test/CodeGen/X86/fp16-libcalls.ll
M llvm/test/CodeGen/X86/llvm.acos.ll
M llvm/test/CodeGen/X86/llvm.asin.ll
M llvm/test/CodeGen/X86/llvm.atan.ll
M llvm/test/CodeGen/X86/llvm.atan2.ll
A llvm/test/CodeGen/X86/llvm.cos.ll
M llvm/test/CodeGen/X86/llvm.cosh.ll
A llvm/test/CodeGen/X86/llvm.sin.ll
M llvm/test/CodeGen/X86/llvm.sinh.ll
M llvm/test/CodeGen/X86/llvm.tan.ll
M llvm/test/CodeGen/X86/llvm.tanh.ll
Log Message:
-----------
[X86][NFC] Added/Updated Trigonometric functions testcases (#127094)
- Added sin/cos testcases.
- Added i686 checks for all testcases.
- Moved fp16 and fp128 cases into separate files.
- Dropped tests for ppc_fp128 type.
- Added global-isel runs as precommit testing for #126931
Commit: 446899e7bed5555c2bacfe0d09c4f4f00c41bc0f
https://github.com/llvm/llvm-project/commit/446899e7bed5555c2bacfe0d09c4f4f00c41bc0f
Author: Sergio Afonso <safonsof at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[MLIR][OpenMP] Host lowering of distribute-parallel-do/for (#127819)
This patch adds support for translating composite `omp.parallel` +
`omp.distribute` + `omp.wsloop` loops to LLVM IR on the host. This is
done by passing an updated `WorksharingLoopType` to the call to
`applyWorkshareLoop` associated to the lowering of the `omp.wsloop`
operation, so that `__kmpc_dist_for_static_init` is called at runtime in
place of `__kmpc_for_static_init`.
Existing translation rules take care of creating a parallel region to
hold the workshared and workdistributed loop.
Commit: 48397fe41ee67557e00f13f35d60c3c9b8485e89
https://github.com/llvm/llvm-project/commit/48397fe41ee67557e00f13f35d60c3c9b8485e89
Author: David Green <david.green at arm.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/shuffle-reverse.ll
Log Message:
-----------
[AArch64] Add cost model for REV shuffles. (#128498)
These patterns represent rev instructions, which reverse inside a
portion of the full vector. See llvm/test/CodeGen/AArch64/arm64-rev.ll
for codegen tests.
Commit: 56975b4ecd188a77b4f9420ff8aa5d5a72e4e076
https://github.com/llvm/llvm-project/commit/56975b4ecd188a77b4f9420ff8aa5d5a72e4e076
Author: Sergio Afonso <safonsof at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
Log Message:
-----------
[OpenMPIRBuilder] Split calculation of canonical loop trip count, NFC (#127820)
This patch splits off the calculation of canonical loop trip counts from
the creation of canonical loops. This makes it possible to reuse this
logic to, for instance, populate the `__tgt_target_kernel` runtime call
for SPMD kernels.
This feature is used to simplify one of the existing OpenMPIRBuilder
tests.
Commit: 29e14958090cb01150bda068f721a09d4bb1c36b
https://github.com/llvm/llvm-project/commit/29e14958090cb01150bda068f721a09d4bb1c36b
Author: Sergio Afonso <safonsof at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/openmp-target-spmd.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[MLIR][OpenMP] Support target SPMD (#127821)
This patch implements MLIR to LLVM IR translation of host-evaluated loop
bounds, completing initial support for `target teams distribute parallel
do [simd]` and `target teams distribute [simd]`.
Commit: 25c19eb1178a26b09e8ee58c825d4ed0260b70da
https://github.com/llvm/llvm-project/commit/25c19eb1178a26b09e8ee58c825d4ed0260b70da
Author: Sergio Afonso <safonsof at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Lower/OpenMP/host-eval.f90
Log Message:
-----------
[Flang][OpenMP] Allow host evaluation of loop bounds for distribute (#127822)
This patch adds `target teams distribute [simd]` and equivalent
construct nests to the list of cases where loop bounds can be evaluated
in the host, as they represent kernels for which the trip count must
also be evaluated in advance to the kernel call.
Commit: dfa3af9255fd542fed5149021289404e92a8a6f3
https://github.com/llvm/llvm-project/commit/dfa3af9255fd542fed5149021289404e92a8a6f3
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/arrays.cpp
A clang/test/AST/ByteCode/libcxx/pointer-subscript.cpp
Log Message:
-----------
[clang][bytecode] Expand subscript base if of pointer type (#128511)
This is similar to what we do in the AddOffset instruction when adding
an offset to a pointer.
Commit: 820aa438a6ec5e028d96bf6b345f41c585f91572
https://github.com/llvm/llvm-project/commit/820aa438a6ec5e028d96bf6b345f41c585f91572
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/test/Dialect/Vector/vector-transfer-permutation-lowering.mlir
Log Message:
-----------
[mlir][vector] Update tests for xfer permutation lowering (4/N) (#127624)
* Document the remaining test cases, add a note that these are
exercising `TransferOpReduceRank` (addresses an existing TODO).
* Add missing cases (for fixed-width and scalable vectors).
* Remove scalable vectors from the negative test (the masked case) - this test
will also fail with fixed-width vectors. For consistency, lets make all
negative test use fixed-width vectors.
Commit: f95ad44068e48c4d8c66f7d65147349b7dd16efa
https://github.com/llvm/llvm-project/commit/f95ad44068e48c4d8c66f7d65147349b7dd16efa
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/remat-sop.mir
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
Log Message:
-----------
AMDGPU: Mark v_mov_b64_pseudo as a VOP1 instruction (#128677)
This is mostly true, and it tricks the rematerialization
code into handling this without special casing it.
Commit: b57e63b07a7b70ebfb5f794648e2102b7c1bd3a3
https://github.com/llvm/llvm-project/commit/b57e63b07a7b70ebfb5f794648e2102b7c1bd3a3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M libclc/amdgcn/lib/workitem/get_global_size.cl
Log Message:
-----------
libclc: Stop using asm declarations for r600 on amdgcn for get_global_size (#128692)
Comparing the case where each dimension is used alone, the only codegen
difference is a missed addressing mode fold for the constant offset in the old
version due to an ancient bug.
Commit: 6aeec5eabfe11f017dd4e427ff5e9a4695f2a24a
https://github.com/llvm/llvm-project/commit/6aeec5eabfe11f017dd4e427ff5e9a4695f2a24a
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/test/Transforms/ConstraintElimination/analysis-invalidation.ll
Log Message:
-----------
[ConstraintElim] Test for #128588
Commit: f8948d3c4754e06cdd3e2903bfbfe74438f6b463
https://github.com/llvm/llvm-project/commit/f8948d3c4754e06cdd3e2903bfbfe74438f6b463
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M libclc/clc/include/clc/float/definitions.h
A libclc/clc/include/clc/math/clc_log.h
A libclc/clc/include/clc/math/clc_log10.h
A libclc/clc/include/clc/math/clc_log2.h
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/math/clc_log.cl
A libclc/clc/lib/generic/math/clc_log10.cl
A libclc/clc/lib/generic/math/clc_log2.cl
A libclc/clc/lib/generic/math/clc_log_base.h
M libclc/generic/include/clc/math/log10.h
M libclc/generic/lib/math/log.cl
M libclc/generic/lib/math/log10.cl
M libclc/generic/lib/math/log2.cl
R libclc/generic/lib/math/log_base.h
Log Message:
-----------
[libclc] Move log/log2/log10 to CLC library (#128540)
This commit also enables fp16 log, which was previously missing.
Other than that, no changes to codegen for AMDGPU/Nvidia targets.
Note that for simplicity this commit doesn't try to refactor or optimize
the implementations. Notably, each log is only implementated for scalar
types; vector types are scalarized. It doesn't look too difficult to
make the implementations suitable for vector codegen, so I'll try that
in a future commit.
There's also an unused implementation of log in clc_log_base.h, whereas
the implementation currently used by libclc targets re-uses log2 with an
additional multiplication. That should also be cleaned up as on first
inspection it looks a more optimal implementation, though it would have
to be checked against the OpenCL CTS for good measure.
Commit: dff2ca424c20c672b418ec86ac3a120fad4fb364
https://github.com/llvm/llvm-project/commit/dff2ca424c20c672b418ec86ac3a120fad4fb364
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/unions.cpp
Log Message:
-----------
[clang][bytecode] Add special case for anonymous unions (#128681)
This fixes the expected output to match the one of the current
interpreter.
Commit: 70de57edcad0055d962e9fe899b347b16a6efaa3
https://github.com/llvm/llvm-project/commit/70de57edcad0055d962e9fe899b347b16a6efaa3
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/Maintainers.rst
Log Message:
-----------
[clang] Add alternative email for steakhal (#128558)
Both steakhal and balazs-benics-sonarsource accounts are mine. See
#125859
Commit: 0f9720a61b1deea225f172851210550f8a60d49f
https://github.com/llvm/llvm-project/commit/0f9720a61b1deea225f172851210550f8a60d49f
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/test/Target/BUILD.bazel
Log Message:
-----------
[bazel] port 29e14958090cb01150bda068f721a09d4bb1c36b
Commit: 11766a40972f5cc853e296231e5d90ca3c886cc1
https://github.com/llvm/llvm-project/commit/11766a40972f5cc853e296231e5d90ca3c886cc1
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M libcxx/include/future
A libcxx/test/std/thread/futures/futures.async/thread_create_failure.pass.cpp
Log Message:
-----------
[libc++] Don't try to wait on a thread that hasn't started in std::async (#125433)
If the creation of a thread fails, this causes an idle loop that will
never end because the thread wasn't started in the first place.
Fixes #125428
Commit: a93cda47ad97af7c69563b3b02dfd9c9a63faefa
https://github.com/llvm/llvm-project/commit/a93cda47ad97af7c69563b3b02dfd9c9a63faefa
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineX86ShuffleChain - pull out repeated getOpcode() calls. NFC.
Commit: e47cd4694851dd71c877b72fa59ec169260cbd32
https://github.com/llvm/llvm-project/commit/e47cd4694851dd71c877b72fa59ec169260cbd32
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineX86ShuffleChain - pass IsMaskedShuffle flag as argument from combineX86ShufflesRecursively instead of computing it internally. NFC.
Prep work toward better handling of shuffle combining across different vector widths.
Commit: 4b29c285645eb0ab8c795044c64072eabd3c041e
https://github.com/llvm/llvm-project/commit/4b29c285645eb0ab8c795044c64072eabd3c041e
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/analysis-invalidation.ll
Log Message:
-----------
[ConstraintElim] Preserve analyses when IR is unchanged. (#128588)
Commit: 089f988f46d7350827c38c1718d47caa56c5a206
https://github.com/llvm/llvm-project/commit/089f988f46d7350827c38c1718d47caa56c5a206
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M libc/CMakeLists.txt
Log Message:
-----------
[libc] Fix defaulting the full build
Summary:
This was missing the architecture macros as they were defined just
below.
Commit: d21b2e619a5e23fd2f4cb05f5929990ee517d164
https://github.com/llvm/llvm-project/commit/d21b2e619a5e23fd2f4cb05f5929990ee517d164
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
Log Message:
-----------
[SPIR-V] Fix generation of gMIR vs. SPIR-V code from utility methods (#128159)
The SPIR-V Backend uses the same set of utility functions, mostly though
not entirely from SPIRVGlobalRegistry, to generate gMIR and SPIR-V
opcodes, depending on the current stage of translation. This is
controlled by an explicit EmitIR flag rather than the current
translation pass, and there are legacy pieces of code where the EmitIR
flag is declared so that it has a default true value, allowing using
utility functions without explicitly declaring their intent to work
either in gMIR or in SPIR-V part of the lowering process.
While it may be ok to leave this default EmitIR flag as is in generation
of scalar integer/float types, as we don't expect to see any dependent
opcodes derived from such OpTypeXXX instructions, using of EmitIR by
default in aggregation types is a source of hidden logical flaws and
actual issues.
This PR provides a partial fix to the problem by removing default status
of EmitIR, requiring a user call site to explicitly announce its intent
to generate gMIR or SPIR-V code, fixes several cases of misuse of
EmitIR, and, the most important, fixes a nasty logical error that breaks
passing of actually asked EmitIR value by the default value in the
middle of the chain of calls, in the `findSPIRVType` call. The latter
error was a source of issues in the post-instruction selection pass that
has been getting gMIR code where SPIR-V was explicitly requested due to
overloaded with default parameters internal API in SPIRVGlobalRegistry
(most notably, `findSPIRVType`).
Commit: 44d1dbd24c20a0ee93063dcf44d68e2b8f0bf77c
https://github.com/llvm/llvm-project/commit/44d1dbd24c20a0ee93063dcf44d68e2b8f0bf77c
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/include/llvm/ADT/APFloat.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
Log Message:
-----------
[X86][DAGCombiner] Skip x87 fp80 values in `combineFMulOrFDivWithIntPow2` (#128618)
f80 is not a valid IEEE floating-point type.
Closes https://github.com/llvm/llvm-project/issues/128528.
Commit: d23da7d6300ec6732b462d475c331f289170cb83
https://github.com/llvm/llvm-project/commit/d23da7d6300ec6732b462d475c331f289170cb83
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
M llvm/test/Transforms/InstCombine/load.ll
Log Message:
-----------
[InstCombine] Increase recursion limit to 3 in `simplifyNonNullOperand` (#128695)
Address review comment
https://github.com/llvm/llvm-project/pull/128466#discussion_r1967228790
Compile-time impact:
https://llvm-compile-time-tracker.com/compare.php?from=72781f58efddecee19feb07fec4e6104ef4c4812&to=3853aee61626b0eda06671b4cbbc4cdd1344440c&stat=instructions:u
Commit: 522b05afb636229acd1f2a50eff14a29c79b4a1a
https://github.com/llvm/llvm-project/commit/522b05afb636229acd1f2a50eff14a29c79b4a1a
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanCFG.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Construct immutable VPIRBBs for exit blocks at construction(NFC) (#128374)
Constract immutable VPIRBasicBlocks for all exit blocks up front and
keep a list of them. Same as the scalar header, they are leaf nodes of
the VPlan and won't change. Some exit blocks may be unreachable, e.g. if
the scalar epilogue always executes or depending on optimizations.
This simplifies both the way we retrieve the exit blocks as well as
hooking up the exit blocks.
PR: https://github.com/llvm/llvm-project/pull/128374
Commit: 1e0e4169dd00bf8a37cef8d74d0add7861982c4e
https://github.com/llvm/llvm-project/commit/1e0e4169dd00bf8a37cef8d74d0add7861982c4e
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
R libclc/generic/include/math/binary_intrin.inc
R libclc/generic/include/math/ternary_intrin.inc
Log Message:
-----------
[libclc][NFC] Remove unused intrinsics helpers (#128708)
We want to move away from using asm declarations to define builtins.
Commit: af68927a831c45b92248b1f6fc24d445be42dd91
https://github.com/llvm/llvm-project/commit/af68927a831c45b92248b1f6fc24d445be42dd91
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/IR/Instruction.cpp
A llvm/test/Transforms/SimplifyCFG/X86/fake-use-considered-when-sinking.ll
Log Message:
-----------
Do not treat llvm.fake.use as a debug instruction (#128684)
The llvm.fake.use intrinsic is used to prevent certain values from being
optimized out for the benefit of debug info; it is not, however, a debug
or pseudo instruction itself and necessarily must not be treated as one,
since its purpose is to act like a normal instruction. In the original
commit that added them, the IR intrinsic however was treated as one in
`getPrevNonDebugInstruction` (but _not_ in `getNextNonDebugInstruction`,
or in the MIR equivalents). This patch correctly treats it as a
non-debug instruction.
Commit: 352c48f278c89ac4c65642d3fadf52032e7fe734
https://github.com/llvm/llvm-project/commit/352c48f278c89ac4c65642d3fadf52032e7fe734
Author: Vikash Gupta <Vikash.Gupta at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/bfis-in-loop.ll
M llvm/test/CodeGen/AArch64/select_cc.ll
M llvm/test/CodeGen/AArch64/selectopt-const.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/copysign-simplify-demanded-bits.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
M llvm/test/CodeGen/ARM/select-imm.ll
M llvm/test/CodeGen/MSP430/shift-amount-threshold.ll
M llvm/test/CodeGen/Thumb/branchless-cmp.ll
Log Message:
-----------
[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)
The Target hook convertSelectOfConstantsToMath() needs to be used within
SimplifySelectCC helper combine function in SelectionDAG Isel, where
generic select folding with constants is happening into simple maths op
using the condition as it is.
It necessarily fixes #121145.
Commit: 4f7d8948d9d9a0d366ac737247abab2246834e05
https://github.com/llvm/llvm-project/commit/4f7d8948d9d9a0d366ac737247abab2246834e05
Author: Ikhlas Ajbar <iajbar at quicinc.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
A llvm/test/CodeGen/Hexagon/bittracker-regclass.ll
Log Message:
-----------
[Hexagon] Add a case to BitTracker for new register class (#128580)
Code in the HexagonBitTracker checks for a specific register class when
processing sub-registers. A crash occurred due to a register class that
was not handled. The register class is
DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID, which is a class
formed by creating a register pair when one of the sub registers is a
Low8 integer register.
Fixes #128078
Patch by: Brendon Cahoon
Commit: a12ca57c1cb070be8e0048004c6b4e820029b6ee
https://github.com/llvm/llvm-project/commit/a12ca57c1cb070be8e0048004c6b4e820029b6ee
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][REVEC] Add getScalarizationOverhead helper function to reduce error when REVEC is enabled. (#128530)
Commit: 1affadb7c662a2eb1cfd01fdfa014ffe473c0dc2
https://github.com/llvm/llvm-project/commit/1affadb7c662a2eb1cfd01fdfa014ffe473c0dc2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
Log Message:
-----------
AMDGPU: Drop legacy r600.read.global.size intrinsics from amdgcn (#128700)
These ancient intrinsics were still consumed by the backend for libclc,
which no longer uses them.
Commit: 148111fdcf0e807fe74274b18fcf65c4cff45d63
https://github.com/llvm/llvm-project/commit/148111fdcf0e807fe74274b18fcf65c4cff45d63
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M .github/workflows/release-binaries.yml
M clang/cmake/caches/Release.cmake
Log Message:
-----------
[CMake][Release] Enable bolt optimization for clang on Linux (#128090)
Also stop buiding the bolt project on other platforms since bolt only
supports ELF.
Commit: 85eb7259d9e1ab57e9fac248096d73505a60c072
https://github.com/llvm/llvm-project/commit/85eb7259d9e1ab57e9fac248096d73505a60c072
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/lib/Sema/SemaChecking.cpp
Log Message:
-----------
[clang] Fix use-after-scope when diagnosting __attribute__((format_matches))
I don't think this will ever crash, but asan complains about it.
SUMMARY: AddressSanitizer: stack-use-after-scope clang/lib/Sema/SemaChecking.cpp:6925:43 in void (anonymous namespace)::CheckFormatHandler::EmitFormatDiagnostic<clang::CharSourceRange>(clang::PartialDiagnostic, clang::SourceLocation, bool, clang::CharSourceRange, llvm::ArrayRef<clang::FixItHint>)
While there switch to stable_sort to not give a flipped error message
half of the time.
Commit: 5fd188833c4cc2f18aa53908fd6237f6a432d629
https://github.com/llvm/llvm-project/commit/5fd188833c4cc2f18aa53908fd6237f6a432d629
Author: Igor Wodiany <igor.wodiany at imgtec.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVImageOps.td
M mlir/lib/Dialect/SPIRV/IR/CMakeLists.txt
A mlir/lib/Dialect/SPIRV/IR/ImageOps.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
M mlir/test/Dialect/SPIRV/IR/image-ops.mlir
M mlir/test/Target/SPIRV/image-ops.mlir
Log Message:
-----------
[mlir][spirv] Refactor image operations (#128552)
This patch makes multiple changes to images ops:
1) The assembly format is unified with the rest of the dialect to use
`%0 = spirv.op %1, %2, %3 : f32, f32, f32` rather than having each type
directly attached to each argument.
2) The verification is moved from `SPIRVOps.cpp` to a new file so the
ops can be easier maintained.
3) Majority of C++ verification is removed and moved into ODS.
Verification of `ImageQuerySizeOp` is left in C++ due to the complexity
of rules.
4) `spirv::bitEnumContainsAll` is replaced by
`spirv::bitEnumContainsAny` in `verifyImageOperands`. In this context
`...Any` seems to be the correct function, as we want to check whether
unsupported operand is being used - in opposite to checking if all
unsupported operands are being used.
5) Simplify target tests by removing entry points and adding `Linkage`
capability to the modules.
This change is made in preparation for adding more Image ops. Change to
the assembly format was previously mentioned in #124124.
Commit: f10e0f7321b34693697a0bf895d440f82b32ba54
https://github.com/llvm/llvm-project/commit/f10e0f7321b34693697a0bf895d440f82b32ba54
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/test/CodeGenCXX/merge-functions.cpp
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
M llvm/test/Transforms/MergeFunc/comdat.ll
M llvm/test/Transforms/MergeFunc/linkonce_odr.ll
M llvm/test/Transforms/MergeFunc/merge-linkonce-odr-used.ll
M llvm/test/Transforms/MergeFunc/merge-linkonce-odr-weak-odr-mixed-used.ll
M llvm/test/Transforms/MergeFunc/merge-linkonce-odr.ll
M llvm/test/Transforms/MergeFunc/merge-weak-odr-used.ll
M llvm/test/Transforms/MergeFunc/merge-weak-odr.ll
Log Message:
-----------
[MergeFuncs] Don't introduce calls to (linkonce,weak)_odr functions. (#125050)
Avoid creating new calls to linkonce_odr/weak_odr functions when
merging 2 functions, as this may introduce an infinite call
cycle.
Consider 2 functions below, both present in 2 modules.
Module X
--
define linkonce_odr void @"A"() {
call void @"foo"()
}
define linkonce_odr void @"B"() {
call void @"foo"()
}
---
Module Y
---
global @"g" = @"B"
define linkonce_odr void @"A"() {
%l = load @"g"
call void %l()
}
define linkonce_odr void @"B"() {
call void @"foo"()
}
---
@"A" and @"B" in both modules are semantically equivalent
Module X after function merging:
---
define linkonce_odr void @"A"() {
call void @"foo"()
}
define linkonce_odr void @"B"() {
call void @"A"()
}
---
Module Y is unchanged.
Then the linker picks @"A" from module Y and @"B" from module X. Now there's an infinite call cycle
PR: https://github.com/llvm/llvm-project/pull/125050
Commit: 83c6b1a88852ac6462e2ae58cb4e5ebdeb0eadd3
https://github.com/llvm/llvm-project/commit/83c6b1a88852ac6462e2ae58cb4e5ebdeb0eadd3
Author: Dave Lee <davelee.com at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
A lldb/examples/python/fzf_history.py
Log Message:
-----------
[lldb] Add fzf_history command to examples (#128571)
Adds a `fzf_history` to the examples directory.
This python command invokes [fzf](https://github.com/junegunn/fzf) to
select from lldb's command history.
Tighter integration is available on macOS, via commands for copy and
paste. The user's chosen history entry back is pasted into the lldb
console (via AppleScript). By pasting it, users have the opportunity to
edit it before running it. This matches how fzf's history search works.
Without copy and paste, the user's chosen history entry is printed to
screen and then run automatically.
Commit: cf3b0368a55c1c285dd80f12b044b58e87a425ac
https://github.com/llvm/llvm-project/commit/cf3b0368a55c1c285dd80f12b044b58e87a425ac
Author: Jack Frankland <jack.frankland at arm.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
Log Message:
-----------
[mlir][tosa][tosa-to-linalg] Add NaN Mode Lowering (#125668)
Add support for NaN propagation lowering in the `tosa-to-linalg` and
`tosa-to-linalg-named` conversions by conditionally checking for NaN in
the case of ignore semantics and materializing the appropriate select
operations. Note that the default behviour of "propagate" matches that
of the arith dialect and so in that case we can avoid creating the
checks altogether.
Add appropriate lit tests including negative tests which check the
various comparisons and selects are materialized as appropriate.
This affects the following TOSA operators:
* arg_max
* max_pool_2d
* clamp
* reduce_max
* reduce_min
* maximum
* minimum
Signed-off-by: Jack Frankland <jack.frankland at arm.com>
Commit: a821ae284724f1522297c0b455b1ca5c05fbc270
https://github.com/llvm/llvm-project/commit/a821ae284724f1522297c0b455b1ca5c05fbc270
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
A libclc/clc/include/clc/math/clc_round.h
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/math/clc_round.cl
M libclc/generic/lib/math/round.cl
Log Message:
-----------
[libclc] Move round to CLC library (#128721)
Commit: 37559c8401cf9236d561eebd75bd3d70be6ab723
https://github.com/llvm/llvm-project/commit/37559c8401cf9236d561eebd75bd3d70be6ab723
Author: pkarveti <quic_pkarveti at quicinc.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonCallingConv.td
A llvm/test/CodeGen/Hexagon/calloperand-v128i1.ll
A llvm/test/CodeGen/Hexagon/calloperand-v16i1.ll
A llvm/test/CodeGen/Hexagon/calloperand-v32i1.ll
A llvm/test/CodeGen/Hexagon/calloperand-v4i1.ll
A llvm/test/CodeGen/Hexagon/calloperand-v64i1.ll
A llvm/test/CodeGen/Hexagon/calloperand-v8i1.ll
Log Message:
-----------
[Hexagon] Handle Call Operand vxi1 in Hexagon Backend (#128027)
This commit updates the Hexagon backend to handle
vxi1 call operands. It ensures compatibility for
vector types of sizes 4, 8, 16, 32, 64, and 128 x i1 when HVX is
enabled.
~Fixes #59009 and #118879~
Commit: 99207ae835efea859f2d9ed4cce781363c0e1562
https://github.com/llvm/llvm-project/commit/99207ae835efea859f2d9ed4cce781363c0e1562
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/lib/Dialect/SPIRV/IR/ImageOps.cpp
Log Message:
-----------
[mlir] Fix a warning
This patch fixes:
mlir/lib/Dialect/SPIRV/IR/ImageOps.cpp:33:24: error: unused variable
'noSupportOperands' [-Werror,-Wunused-variable]
Commit: 568106c2150f4442ad39d9c58493b962c87763bd
https://github.com/llvm/llvm-project/commit/568106c2150f4442ad39d9c58493b962c87763bd
Author: Julian Lettner <yln at users.noreply.github.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M lldb/include/lldb/Core/ModuleList.h
Log Message:
-----------
[lldb][NFC] Fix comment in lldb/Core/ModuleList.h (#128602)
Commit: 7501c9c0e124139198cf84148a49fe80b9f64cea
https://github.com/llvm/llvm-project/commit/7501c9c0e124139198cf84148a49fe80b9f64cea
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/AsmParser/LLParser.cpp
Log Message:
-----------
[AsmParser] Avoid repeated map lookups (NFC) (#128629)
Commit: 791da3c5c2efc13e952ec4fe041e88428e4a331a
https://github.com/llvm/llvm-project/commit/791da3c5c2efc13e952ec4fe041e88428e4a331a
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
Log Message:
-----------
[AsmPrinter] Avoid repeated hash lookups (NFC) (#128630)
Commit: 9388e42a3c67a4399bbc3a427077ea95bac31323
https://github.com/llvm/llvm-project/commit/9388e42a3c67a4399bbc3a427077ea95bac31323
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/SelectOptimize.cpp
Log Message:
-----------
[CodeGen] Avoid repeated hash lookups (NFC) (#128631)
Commit: 43401dd0b5c659047e546efbc55f9f88261142d6
https://github.com/llvm/llvm-project/commit/43401dd0b5c659047e546efbc55f9f88261142d6
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M libcxx/test/libcxx/atomics/atomics.syn/compatible_with_stdatomic.compile.pass.cpp
M libcxx/test/libcxx/input.output/file.streams/fstreams/filebuf/traits_mismatch.verify.cpp
M libcxx/test/libcxx/input.output/file.streams/fstreams/traits_mismatch.verify.cpp
M libcxx/test/libcxx/input.output/iostream.format/input.streams/traits_mismatch.verify.cpp
M libcxx/test/libcxx/input.output/iostream.format/output.streams/traits_mismatch.verify.cpp
M libcxx/test/libcxx/input.output/string.streams/traits_mismatch.verify.cpp
M libcxx/test/std/containers/sequences/array/array.fill/fill.verify.cpp
M libcxx/test/std/containers/sequences/array/array.swap/swap.verify.cpp
M libcxx/test/std/containers/sequences/array/array.tuple/get.verify.cpp
M libcxx/test/std/containers/sequences/array/array.tuple/tuple_element.verify.cpp
M libcxx/test/std/strings/basic.string/char.bad.verify.cpp
Log Message:
-----------
[libc++] Make .verify.cpp tests more robust against changing headers (#128703)
This is fixes the tests for the frozen headers, but is an improvement
either way.
Commit: 38f8ca1d1817969d712a7e70e070228eee8a0f3f
https://github.com/llvm/llvm-project/commit/38f8ca1d1817969d712a7e70e070228eee8a0f3f
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/DebugInfo/LogicalView/Readers/LVCodeViewReader.cpp
Log Message:
-----------
[DebugInfo] Avoid repeated hash lookups (NFC) (#128632)
Commit: 9889de834b0a9fa4a5a222a81a524c75977e41d4
https://github.com/llvm/llvm-project/commit/9889de834b0a9fa4a5a222a81a524c75977e41d4
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h
Log Message:
-----------
[Utils] Avoid repeated hash lookups (NFC) (#128634)
Commit: 8bea51103000e4ac752ecd8ed1550c1c9d105a6b
https://github.com/llvm/llvm-project/commit/8bea51103000e4ac752ecd8ed1550c1c9d105a6b
Author: Marius Kamp <msk at posteo.org>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/andnot-blsmsk.ll
Log Message:
-----------
[X86] Fold AND(Y, XOR(X, SUB(0, X))) to ANDN(Y, BLSMSK(X)) (#128348)
XOR(X, SUB(0, X)) corresponds to a bitwise-negated BLSMSK instruction
(i.e., x ^ (x - 1)). On its own, this transformation is probably not
really profitable but when the XOR operation is an operand of an AND
operation, we can use an ANDN instruction to reduce the number of
emitted instructions by one.
Fixes #103501.
Commit: e58f475e84545d12c52e177fdea69c0f2bec81df
https://github.com/llvm/llvm-project/commit/e58f475e84545d12c52e177fdea69c0f2bec81df
Author: Tai Ly <tai.ly at arm.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaProfileCompliance.h
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/profile_all_unsupported.mlir
M mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
M mlir/test/Dialect/Tosa/profile_pro_int_unsupported.mlir
Log Message:
-----------
[mlir][tosa] Move cond_if and while_loop operations to controlflow extension (#128216)
This commit adds the concept of a controlflow extension to the dialect
and updates the validation pass to check conf_if and while_loop are
supported only in the presence of the controlflow extension.
Signed-off-by: Luke Hutton <luke.hutton at arm.com>
Co-authored-by: Luke Hutton <luke.hutton at arm.com>
Commit: 53b46bb09474bd22fd097411f9eb4596424116ee
https://github.com/llvm/llvm-project/commit/53b46bb09474bd22fd097411f9eb4596424116ee
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/test/Dialect/Tosa/canonicalize.mlir
Log Message:
-----------
[mlir][tosa] Fix crash on attempt to fold int_div by zero (#128682)
Fixes #118268.
Signed-off-by: Luke Hutton <luke.hutton at arm.com>
Commit: f08824b935434b91f7352904a25f6309f2b3e6bd
https://github.com/llvm/llvm-project/commit/f08824b935434b91f7352904a25f6309f2b3e6bd
Author: David Green <david.green at arm.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/test/Analysis/CostModel/AArch64/div.ll
M llvm/test/Analysis/CostModel/AArch64/rem.ll
Log Message:
-----------
[AArch64] Add udiv and urem uniform tests. NFC
These should cost the same as non-uniform version.
Commit: 24b7759a9dfe5714236957e7d829e2412100a4b7
https://github.com/llvm/llvm-project/commit/24b7759a9dfe5714236957e7d829e2412100a4b7
Author: Mats Petersson <mats.petersson at arm.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M flang/examples/FlangOmpReport/FlangOmpReportVisitor.cpp
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
A flang/test/Lower/OpenMP/Todo/assume.f90
A flang/test/Lower/OpenMP/Todo/assumes.f90
A flang/test/Parser/OpenMP/assumption.f90
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[FLANG][OpenMP]Add frontend support for ASSUME and ASSUMES (#120770)
Enough suport to parse correctly formed directives of !$OMP ASSUME and
!$OMP ASSUMES with teh related clauses that go with them: ABSENT,
CONTAINS, NO_OPENPP, NO_OPENMP_ROUTINES, NO_PARALLELISM and HOLDS.
Tests added for unparsing and dump parse-tree.
Semantics support is very minimal and no specific tests added.
The lowering will hit a TODO, and there are tests in Lower/OpenMP/Todo
to make it clear that this is currently expected behaviour.
---------
Co-authored-by: Kiran Chandramohan <kiran.chandramohan at arm.com>
Co-authored-by: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Commit: 041b7f508533417bcda4feaa03d6c16ff85275f5
https://github.com/llvm/llvm-project/commit/041b7f508533417bcda4feaa03d6c16ff85275f5
Author: Malavika Samak <malavika.samak at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-function-attr.cpp
Log Message:
-----------
[Wunsafe-buffer-usage] Turn off unsafe-buffer warning for methods annotated with clang::unsafe_buffer_usage attribute (#125671)
Unsafe operation in methods that are already annotated with
clang::unsafe_buffer_usage attribute, should not trigger a warning. This
is because, the developer has already identified the method as unsafe
and warning at every unsafe operation is redundant.
rdar://138644831
---------
Co-authored-by: MalavikaSamak <malavika2 at apple.com>
Commit: d2d469eb7981885eac188bf7988c72d7e85b2d4e
https://github.com/llvm/llvm-project/commit/d2d469eb7981885eac188bf7988c72d7e85b2d4e
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/WasmEHPrepare.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/test/CodeGen/WebAssembly/exception.ll
M llvm/test/Verifier/invoke.ll
Log Message:
-----------
[WebAssembly] Make llvm.wasm.throw invokable (#128104)
`llvm.wasm.throw` intrinsic can throw but it was not invokable. Not sure
what the rationale was when it was first written that way, but I think
at least in Emscripten's C++ exception support with the Wasm port of
libunwind, `__builtin_wasm_throw`, which is lowered down to
`llvm.wasm.rethrow`, is used only within `_Unwind_RaiseException`, which
is an one-liner and thus does not need an `invoke`:
https://github.com/emscripten-core/emscripten/blob/720e97f76d6f19e0c6a2d6988988cfe23f0517fb/system/lib/libunwind/src/Unwind-wasm.c#L69
(`_Unwind_RaiseException` is called by `__cxa_throw`, which is generated
by the `throw` C++ keyword)
But this does not address other direct uses of the builtin in C++, whose
use I'm not sure about but is not prohibited. Also other language
frontends may need to use the builtin in different functions, which has
`try`-`catch`es or destructors.
This makes `llvm.wasm.throw` invokable in the backend. To do that, this
adds a custom lowering routine to `SelectionDAGBuilder::visitInvoke`,
like we did for `llvm.wasm.rethrow`.
This does not generate `invoke`s for `__builtin_wasm_throw` yet, which
will be done by a follow-up PR.
Addresses #124710.
Commit: 48db4e8377f8504cf151cf4d2b4ecf33461eedc8
https://github.com/llvm/llvm-project/commit/48db4e8377f8504cf151cf4d2b4ecf33461eedc8
Author: Tai Ly <tai.ly at arm.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeTransposeConv.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaFolders.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaReduceTransposes.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Dialect/MemRef/resolve-dim-ops.mlir
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/constant-op-fold.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-transpose-conv.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/tosa-reduce-transposes.mlir
M mlir/test/Dialect/Tosa/transpose-fold.mlir
Log Message:
-----------
[mlir][tosa] Change Transpose perms operand to attribute (#128115)
This patch changes the perms operand for Tosa Transpose operator to an
i32 array attribute
Signed-off-by: Tai Ly <tai.ly at arm.com>
Commit: 4f18f3f09a744ddd05de2188592fa11533ff3054
https://github.com/llvm/llvm-project/commit/4f18f3f09a744ddd05de2188592fa11533ff3054
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/test/CodeGen/RISCV/or-is-add.ll
M llvm/test/CodeGen/RISCV/select-const.ll
M llvm/test/CodeGen/RISCV/select.ll
Log Message:
-----------
[RISCV] Use addiw for or_is_add when or input is sign extended. (#128635)
We prefer to emit addi instead of ori because its more compressible, but
this can pessimize the sext.w removal pass.
If the input to the OR is known to be a sign extended 32 bit value, we
can use addiw instead of addi which will give more power to the sext.w
removal pass. As it is known to produce sign a sign extended value and
only consume the lower 32 bits.
Fixes #128468.
Commit: 0a7809c644485d6650ea01bfe616623f580b24d1
https://github.com/llvm/llvm-project/commit/0a7809c644485d6650ea01bfe616623f580b24d1
Author: Jerry-Ge <jerry.ge at arm.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/Utils/ConversionUtils.cpp
Log Message:
-----------
[mlir][tosa] Fix ability to expand ranks with dynamic shape support (#128037)
- Fix ability to expand ranks with dynamic shape support
- Simplify the code
Signed-off-by: Suraj Sudhir <suraj.sudhir at arm.com>
Co-authored-by: Suraj Sudhir <suraj.sudhir at arm.com>
Commit: 43999deb370113945ef86680014f838f55315ee7
https://github.com/llvm/llvm-project/commit/43999deb370113945ef86680014f838f55315ee7
Author: Jon Chesterfield <jonathanchesterfield at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/lib/Basic/Targets/SPIR.h
Log Message:
-----------
[spirv][amdgpu] Set atomic size in the clang target info (#128569)
Problem identified by Joseph. The openmp device runtime uses
__scoped_atomic_load_n and similar which presently hit
```
error: large atomic operation may incur significant performance
penalty; the access size (4 bytes) exceeds the max lock-free size (0 bytes) [-Werror,-Watomic-alignment]
```
This is because the spirv class doesn't set the corresponding field. The
base does, but only if there's a host toolchain, which there isn't.
Commit: 67056c280a7171a3546442013593687d5ad5440b
https://github.com/llvm/llvm-project/commit/67056c280a7171a3546442013593687d5ad5440b
Author: Brendan Dahl <brendan.dahl at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/test/CodeGen/WebAssembly/half-precision.ll
Log Message:
-----------
[WebAssembly] Support shuffle for F16x8 vectors. (#127857)
Commit: a778930f85b6d17cf31ff0e15964a7c7116e2a9d
https://github.com/llvm/llvm-project/commit/a778930f85b6d17cf31ff0e15964a7c7116e2a9d
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.h
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgRelayoutOps.td
A mlir/include/mlir/Dialect/Linalg/IR/RelayoutOpInterface.h
A mlir/include/mlir/Dialect/Linalg/IR/RelayoutOpInterface.td
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
Log Message:
-----------
[mlir][linalg] Create a dedicated target for `LinalgRelayoutInterface` (#128485)
Creates an interface target for `LinalgRelayoutInterface`. This is
primarily to reduce the dependency of `Tensor` on `Linalg` to the
required minimum. For context and rationale, see:
* https://github.com/llvm/llvm-project/issues/127668
Note, I also took the liberty of renaming `LinalgRelayoutInterface` as
`RelayoutOpInterface` (removed `Linalg`, added `Op`).
Commit: 3968ebd00da80a08de84f83a101ebb23710f6631
https://github.com/llvm/llvm-project/commit/3968ebd00da80a08de84f83a101ebb23710f6631
Author: Amir Ayupov <aaupov at fb.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M bolt/lib/Core/BinaryFunction.cpp
A bolt/test/X86/entry-point-fallthru.s
Log Message:
-----------
[BOLT] Keep multi-entry functions simple in aggregation mode (#128253)
BOLT used to mark multi-entry functions non-simple in non-relocation
mode with the reasoning that we can't move them due to potentially
undetected references. However, in aggregation mode it doesn't apply as
BOLT doesn't perform optimizations.
Relax this constraint in case of an aggregation job.
Test Plan: added entry-point-fallthru.s
Commit: f5675243995dbca22319ed4c0665b3e46138285b
https://github.com/llvm/llvm-project/commit/f5675243995dbca22319ed4c0665b3e46138285b
Author: Amir Ayupov <aaupov at fb.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M bolt/lib/Profile/DataAggregator.cpp
M bolt/test/X86/bolt-address-translation-yaml.test
Log Message:
-----------
[BOLT] Fix doTrace in BAT mode (#128546)
When processing BOLTed binaries with BAT section, we used to
indiscriminately use `BAT->getFallthroughsInTrace` to record
fall-throughs, even if the function is not covered by BAT.
Fix that by using non-BAT CFG-based `getFallthroughsInTrace` if the
function is not in BAT.
Test Plan: updated bolt-address-translation-yaml.test
Commit: ab0e6fcaadf158427dfe480e1ae2c0a5ddea98ec
https://github.com/llvm/llvm-project/commit/ab0e6fcaadf158427dfe480e1ae2c0a5ddea98ec
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M libc/cmake/modules/LLVMLibCHeaderRules.cmake
Log Message:
-----------
[libc][cmake] Clean up dead code in add_gen_header (#128753)
DATA_FILES CMake argument never existed in the new YAML-based hdrgen
version of add_gen_header function, and thus its uses added in
b1fd6f0996a9d6e6ebfa0cc3df0fe499c5ccdf65 were always dead code.
Remove them to clean up the function implementation.
Co-authored-by: Alexey Samsonov <samsonov at google.com>
Commit: 66af4923ce245a0fd9427db8e4861354576d0866
https://github.com/llvm/llvm-project/commit/66af4923ce245a0fd9427db8e4861354576d0866
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/CMakeLists.txt
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/Handler/RequestHandler.cpp
A lldb/tools/lldb-dap/Handler/ResponseHandler.cpp
A lldb/tools/lldb-dap/Handler/ResponseHandler.h
Log Message:
-----------
[lldb-dap] Refactor reverse request response handlers (NFC) (#128594)
This refactors the response handlers for reverse request to follow the
same architecture as the request handlers. With only two implementation
that might be overkill, but it reduces code duplication and improves
error reporting by storing the sequence ID. This PR also fixes an
unchecked Expected in the old callback for unknown sequence IDs.
Commit: 7c266756ad2eeeb2a9018eb97dc45809922bd49e
https://github.com/llvm/llvm-project/commit/7c266756ad2eeeb2a9018eb97dc45809922bd49e
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/tools/lldb-dap/BUILD.gn
Log Message:
-----------
[gn build] Port 66af4923ce24
Commit: 9102afcd0146e4e0be7e10ecd6a2537a6960cfcd
https://github.com/llvm/llvm-project/commit/9102afcd0146e4e0be7e10ecd6a2537a6960cfcd
Author: Brendan Dahl <brendan.dahl at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/test/CodeGen/WebAssembly/half-precision.ll
Log Message:
-----------
[WebAssembly] Use the same lowerings for f16x8 as other float vectors. (#127897)
This fixes failures to select the various compare operations that
weren't being expanded for f16x8.
Commit: c8136da26c56f44ab6a217853c58f79b88ceeb97
https://github.com/llvm/llvm-project/commit/c8136da26c56f44ab6a217853c58f79b88ceeb97
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
A llvm/test/MC/Disassembler/RISCV/xqci-invalid.txt
Log Message:
-----------
[RISCV] Correctly Decode Unsigned Immediates with Ranges (#128584)
We currently have two operands upstream that are an unsigned immediate
with a range constraint - `uimm8ge32` (for `cm.jalt`) and `uimm5gt3`
(for `qc.shladd`).
Both of these were using `decodeUImmOperand<N>` for decoding. For `Zcmt`
this worked, because the generated decoder automatically checked for
`cm.jt` first because the 8 undefined bits in `cm.jalt` are `000?????`
in `cm.jt` (this is to do with the range lower-bound being a
power-of-two). For Zcmt, this patch is NFC.
We have less luck with `Xqciac` - `qc.shladd` is being decoded where the
`uimm5` field is 3 or lower. This patch fixes this by introducing a
`decodeUImmOperandGE<Width, LowerBound>` helper, which will corretly
return `MCDisassembler::Fail` when the immediate is below the lower
bound.
I have added a test to show the encoding where `uimm5` is equal to 3 is
no longer disassembled as `qc.shladd`.
Commit: f22291c791c8063ef5125392ada3556dd3e62df5
https://github.com/llvm/llvm-project/commit/f22291c791c8063ef5125392ada3556dd3e62df5
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
Log Message:
-----------
[RISCV][NFC] Merge Xqci Decoder Tables (#128140)
RISC-V has multiple decoder tables because there is no guarantee that
non-standard extensions do not overlap with each other.
Qualcomm's Xqci family of extensions are intended to be implemented
together, and therefore we want a single decode table for this group of
extensions. This should be more efficient overall, and allows us to use
tablegen's existing mechanism that finds overlapping encodings within
the group.
To implement this, the key addition is `TRY_TO_DECODE_FEATURE_ANY`,
which will use the provided decoder table if any of the features from
the FeatureBitset (first argument) are enabled, rather than if all are
enabled.
Commit: 00f02fed882822008f8e4733bcdfb84799d9fb39
https://github.com/llvm/llvm-project/commit/00f02fed882822008f8e4733bcdfb84799d9fb39
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/docs/RISCVUsage.rst
M llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
M llvm/test/MC/RISCV/xrivosvizip-invalid.s
M llvm/test/MC/RISCV/xrivosvizip-valid.s
Log Message:
-----------
[RISCV] Change the vendor prefix for Rivos from "rv." to "ri." (#128761)
There had been concern raised about possible confusion with "rvv". After
internal discussion, we decided to go with an alternate prefix to reduce
possible confusion going forward. The specification document
(https://github.com/rivosinc/rivos-custom-extensions) has been updated.
And also add the XRivosVizip extension to the documentation. I'd missed
that in the initial commit.
Commit: 4357a6603f2c21f343d500778f71494e865262ac
https://github.com/llvm/llvm-project/commit/4357a6603f2c21f343d500778f71494e865262ac
Author: Jeff Niu <jeffniu22 at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrDialect.td
M mlir/include/mlir/Interfaces/DataLayoutInterfaces.td
M mlir/test/lib/Dialect/Test/TestTypeDefs.td
Log Message:
-----------
[mlir][DLTI] Make `getPreferredAlignment` default to `getABIAlignment` (#128754)
Many types don't have a preferred alignment, but often specifying an ABI
alignment is required to implement APIs on top of data layouts. Default
the preferred alignment to `getABIAlignment` to simplify things.
Commit: eacbcbe47744a496ad1651ebd65914f9e6a66f85
https://github.com/llvm/llvm-project/commit/eacbcbe47744a496ad1651ebd65914f9e6a66f85
Author: David Olsen <dolsen at nvidia.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/test/CIR/func-simple.cpp
M clang/test/CIR/global-var-simple.cpp
Log Message:
-----------
[CIR] Upstream type `bool` (#128601)
Support the type `bool` and the literals `true` and `false`. Add the
type `cir::BoolType` and the attribute `cir::BoolAttr` to ClangIR. Add
code in all the necessary places in ClangIR CodeGen to handle and to
recognize the type and the attribute.
Add test cases to existing tests func-simple.cpp and
global-var-simple.cpp.
Commit: f1025e671ef1c1d6a65944cdb3989608cfbc7f0c
https://github.com/llvm/llvm-project/commit/f1025e671ef1c1d6a65944cdb3989608cfbc7f0c
Author: Jonas Hahnfeld <hahnjo at hahnjo.de>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/include/llvm/Support/AlignOf.h
Log Message:
-----------
[Support] Replace deprecated std::aligned_union, NFCI. (#127417)
All std::aligned_* are deprecated in C++23. Implement the replacement
suggested in P1413R3 using alignas and std::max.
Commit: 5e4938a9918ac0e9c2ed3a9171767e6beafcea47
https://github.com/llvm/llvm-project/commit/5e4938a9918ac0e9c2ed3a9171767e6beafcea47
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M libcxx/test/std/thread/futures/futures.async/thread_create_failure.pass.cpp
Log Message:
-----------
Exclude hwasan from thread_create_failure.pass.cpp (#128768)
Fixes hwasan buildbot failure
(https://lab.llvm.org/buildbot/#/builders/55/builds/7536/steps/10/logs/stdio)
introduced in https://github.com/llvm/llvm-project/pull/125433 by
excluding this test for hwasan, similar to the existing exclusion of
asan.
Commit: 6a5dd04013a1442ed4c5861216c8c67a81f37ed0
https://github.com/llvm/llvm-project/commit/6a5dd04013a1442ed4c5861216c8c67a81f37ed0
Author: Jonas Hahnfeld <hahnjo at hahnjo.de>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/include/llvm/Support/AlignOf.h
Log Message:
-----------
[Support] Try to fix AlignedCharArrayUnion with GCC 7.5
Work around "internal compiler error: Segmentation fault", apparently
caused by alignas(Ts...).
Commit: c79e867cd2bbf414f53de169cd4480666303f0dc
https://github.com/llvm/llvm-project/commit/c79e867cd2bbf414f53de169cd4480666303f0dc
Author: Justin Bogner <mail at justinbogner.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/include/llvm/Analysis/DXILResource.h
M llvm/lib/Analysis/DXILResource.cpp
M llvm/test/Analysis/DXILResource/buffer-frombinding.ll
Log Message:
-----------
[DirectX] Update CBuffer to refer to a `dx.Layout` type (#128697)
This adds support cbuffers based on llvm/wg-hlsl#171 - the type argument
of the CBuffer TargetExtType is either a `dx.Layout` type which reports
its own size, or it's a normal type and we can simply refer to
DataLayout.
Commit: 303d7fa867407e9763f329e94a271e652ccb9ed0
https://github.com/llvm/llvm-project/commit/303d7fa867407e9763f329e94a271e652ccb9ed0
Author: Johannes de Fine Licht <johannes.definelicht at nextsilicon.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/include/mlir/Interfaces/LoopLikeInterface.td
Log Message:
-----------
[MLIR][Interfaces] Make LoopLikeOpInterface inheritable outside of MLIR (#128743)
Many interface methods did not prefix the `mlir` namespace, which
prevented inheriting from this interface from an interface defined
outside the `mlir` namespace. Prefix namespaces everywhere to enable
this.
Commit: 0be3f134c3b0bea0a3f32db55258c776caf616fb
https://github.com/llvm/llvm-project/commit/0be3f134c3b0bea0a3f32db55258c776caf616fb
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/test/CodeGen/DirectX/clamp.ll
M llvm/test/CodeGen/DirectX/discard.ll
A llvm/test/CodeGen/DirectX/unsupported_intrinsic.ll
Log Message:
-----------
[DirectX] only allow intrinsics defined in DXIL.td (#128613)
Fixes #128071
The current behavior lets intrinsics that don't map to a DXILOP slip
through. Nothing catches this until we hit the DXIL validator. This
change fails earlier so we don't encode invalid llvm intrinsics that can
slip through because of clang builtins like `__builtin_reduce_and`
example:
https://hlsl.godbolt.org/z/13rPj18vn
Commit: 2646c36a864aa6a62bc1280e9a8cd2bcd2695349
https://github.com/llvm/llvm-project/commit/2646c36a864aa6a62bc1280e9a8cd2bcd2695349
Author: Christopher Bate <cbate at nvidia.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Bufferization/Transforms/OneShotModuleBufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/TensorCopyInsertion.cpp
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir
M mlir/test/Dialect/Bufferization/Transforms/transform-ops.mlir
Log Message:
-----------
[mlir][bufferization] Change OneShotModuleBufferize to not analyze or bufferize nested symbol tables (#127726)
The existing OneShotModuleBufferize will analyze and bufferize
operations which are in nested symbol tables (e.g. nested
`builtin.module`, `gpu.module`, or similar operations). This
behavior is untested and likely unintentional given other
limitations of OneShotModuleBufferize (`func.call` can't call
into nested symbol tables). This change reverses the existing
behavior so that the operations considered by the analysis and
bufferization exclude any operations in nested symbol table
scopes. Users who desire to bufferize nested modules can still do
so by applying the transformation in a pass pipeline or in a
custom pass. This further enables controlling the order in which
modules are bufferized as well as allowing use of different
options for different kinds of modules.
Commit: ad94af973a76ecaa3e6a85304a4abe8130e88bdb
https://github.com/llvm/llvm-project/commit/ad94af973a76ecaa3e6a85304a4abe8130e88bdb
Author: David Olsen <dolsen at nvidia.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
Log Message:
-----------
[CIR] React to breaking change to DataLayoutTypeInterface (#128772)
In #128754, `DataLayoutTypeInterface` was changed to give
`getPreferredAlignment` a default implemention. As a result, table-gen
no longer declared `getPreferredAlignment` when defining a class that
contained `[DeclareTypeInterfaceMethods<DataLayoutTypeInterface>]` in
the table-gen definition. That means all of the definitions in
`CIRTypes.cpp`, such as `PointerType::getPreferredAligment`, were
compilation errors.
Delete all the definitions of `getPreferredAlignment`. I verified that
the default implementation does the exact same thing as the explicit
overrides that are being deleted.
Commit: 44ffeecde2658249d57a54f52c11a339f2e6d14e
https://github.com/llvm/llvm-project/commit/44ffeecde2658249d57a54f52c11a339f2e6d14e
Author: Justin Bogner <mail at justinbogner.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Analysis/DXILResource.cpp
A llvm/test/CodeGen/DirectX/Metadata/cbuffer-only.ll
Log Message:
-----------
[DXIL][Analysis] Make sure resource accessors are contiguous (#128696)
When some resource types were present, but not all of them, we were
ending up in a situation where we would fail to initialize the `FirstX`
variables and get incorrect iterators.
Fixes #128560.
Commit: f4a80180f141bbe0e00477db59f6fc6ed4f50a2f
https://github.com/llvm/llvm-project/commit/f4a80180f141bbe0e00477db59f6fc6ed4f50a2f
Author: Michael Jones <michaelrj at google.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/src/stdio/generic/fileno.cpp
Log Message:
-----------
[libc] Move fileno and fdopen to fullbuild only (#128762)
Both fileno and fdopen require interfacing with the opaque FILE struct,
so they shouldn't be enabled in overlay mode. This patch moves both into
fullbuild only on all platforms.
Fixes #128643
Commit: 8beec9fc48194224779e5428b625fe341e617129
https://github.com/llvm/llvm-project/commit/8beec9fc48194224779e5428b625fe341e617129
Author: Michael Jones <michaelrj at google.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/stdlib.yaml
M libc/src/stdlib/CMakeLists.txt
A libc/src/stdlib/a64l.cpp
A libc/src/stdlib/a64l.h
M libc/test/src/stdlib/CMakeLists.txt
A libc/test/src/stdlib/a64l_test.cpp
Log Message:
-----------
[libc] implement a64l (#128758)
Implement the posix function a64l.
Standard:
https://pubs.opengroup.org/onlinepubs/9799919799/functions/a64l.html
Commit: 59cee030fb9b8be7ee0a89964ead5120d029deb4
https://github.com/llvm/llvm-project/commit/59cee030fb9b8be7ee0a89964ead5120d029deb4
Author: Reid Kleckner <rnk at google.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
R clang/utils/creduce-clang-crash.py
A clang/utils/reduce-clang-crash.py
Log Message:
-----------
Generalize creduce-clang-crash.py script to look for cvise (#128592)
cvise reimplements creduce in Python and bundles clang-delta and other
tools. In my experience, it is generally a more robust reduction tool
that is better maintained. I renamed the script to make it tool-neutral,
which also opens up the possibility that we teach it how to
automatically transition over to llvm-reduce and opt/llc to handle LLVM
backend crashes, but that is potential future work.
Internally, the variable names still say "creduce". I kept using the
verb "reduce" because "vise" is not a verb, but the external facing text
has been updated.
Commit: e6f6a1e863895a3378e703525a6d0d293413be33
https://github.com/llvm/llvm-project/commit/e6f6a1e863895a3378e703525a6d0d293413be33
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
Log Message:
-----------
[AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (#128233)
Enable gisel selection for uaddsat and usubsat in true16 flow
This patch includes:
1. Added VGPR_16_Lo128/VGPR_16 to register bank and update register info
for recognizing 16bit regclass id and bit width
2. uaddsat/usubsat test update
Commit: 40566fd674d110185e2d5e72e320369bfab63ede
https://github.com/llvm/llvm-project/commit/40566fd674d110185e2d5e72e320369bfab63ede
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGenCXX/builtins-eh-wasm.cpp
Log Message:
-----------
[WebAssembly] Generate invokes with llvm.wasm.(re)throw (#128105)
Even though `__builtin_wasm_throw`, which is lowered down to
`llvm.wasm.throw`, throws,
```cpp
try {
__builtin_wasm_throw(0, obj);
} catch (...) {
}
```
does not generate `invoke`. This is because we have assumed the
intrinsic cannot be invoked, which doesn't make much sense. (See #128104
for the historical context)
#128104 made `llvm.wasm.throw` intrinsic invokable in the backend. This
actually generates `invoke`s in Clang for `__builtin_wasm_throw`.
While we're at it, this also generates `invoke`s for
`__builtin_wasm_rethrow`, which is actually not used anywhere in C++
support. I haven't deleted it just in case in may have uses later. (For
example, to support rethrow functionality that carries stack trace with
exnref)
Depends on #128104 for the CI to pass.
Fixes #124710.
Commit: 65cf534139ab884d6886810b647dc50e3affaa19
https://github.com/llvm/llvm-project/commit/65cf534139ab884d6886810b647dc50e3affaa19
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M flang/module/cudadevice.f90
Log Message:
-----------
[flang][cuda] Add interfaces for __ldcg, __ldca, __ldcs, __ldlu, __ldcv, __stwb, __stcg, __stcs, __stwt (#128766)
Commit: 789bfdc3e60cad3b8aa6798ed06d24ad62a4bc1d
https://github.com/llvm/llvm-project/commit/789bfdc3e60cad3b8aa6798ed06d24ad62a4bc1d
Author: Paul Floyd <pjfloyd at wanadoo.fr>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M openmp/tools/archer/ompt-tsan.cpp
Log Message:
-----------
[OMPT] Use __tsan_init to detect TSan binaries rather than RunningOnValgrind (#128357)
Switch to using __tsan_init rather than RunningOnValgrind as the means
for detecting TSan instumented binaries. RunningOnValgrind is present in
other libraries (such as Google perftools tcmalloc). An exe that links
with a tcmalloc static library and exports symbols with -rdynamic will
appear to be TSan instrumented even when it is not resulting in "Unable
to fint TSan function ..." messages.
Fixes issue #122319.
Commit: 864071dd7e191ba895abf69dfa6937a2cadaffbe
https://github.com/llvm/llvm-project/commit/864071dd7e191ba895abf69dfa6937a2cadaffbe
Author: Sterling-Augustine <56981066+Sterling-Augustine at users.noreply.github.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Bazel fixes for a778930f85b6d17cf31ff0e15964a7c7116e2a9d (#128783)
Commit: 30a7c816ee5ca998da960c6ab98e72903de40592
https://github.com/llvm/llvm-project/commit/30a7c816ee5ca998da960c6ab98e72903de40592
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Passes/PassBuilderPipelines.cpp
Log Message:
-----------
[LTO][Pipelines][NFC] Exctract isLTOPostLink (#128653)
Commit: fc655b1ae78305ad0839c0311f72607775af0c73
https://github.com/llvm/llvm-project/commit/fc655b1ae78305ad0839c0311f72607775af0c73
Author: Justin Bogner <mail at justinbogner.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
Log Message:
-----------
[DirectX] Fix printing of DXIL cbuffer info (#128698)
Make sure we're able to print cbuffer comments in a way that's
compatible with DXC.
Fixes #128562
Commit: 1b39328d7440aa7a94af4083257ef1c2f9394887
https://github.com/llvm/llvm-project/commit/1b39328d7440aa7a94af4083257ef1c2f9394887
Author: Eli Friedman <efriedma at quicinc.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/MachineInstr.cpp
A llvm/test/CodeGen/AArch64/inline-asm-speculation.ll
M llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll
M llvm/test/CodeGen/AMDGPU/early-if-convert.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
M llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
M llvm/test/CodeGen/X86/x86-win64-shrink-wrapping.ll
Log Message:
-----------
[CodeGen] Fix MachineInstr::isSafeToMove handling of inline asm. (#126807)
Even if an inline asm doesn't have memory effects, we can't assume it's
safe to speculate: it could trap, or cause undefined behavior. At the
LLVM IR level, this is handled correctly: we don't speculate inline asm
(unless it's marked "speculatable", but I don't think anyone does that).
Codegen also needs to respect this restriction.
This change stops Early If Conversion and similar passes from
speculating an INLINEASM MachineInstr.
Some uses of isSafeToMove probably could be switched to a different API:
isSafeToMove assumes you're hoisting, but we could handle some forms of
sinking more aggressively. But I'll leave that for a followup, if it
turns out to be relevant.
See also discussion on gcc bugtracker
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102150 .
Commit: b7060d0183f8f23e4e1a8ce6222fa8fa51b26fbd
https://github.com/llvm/llvm-project/commit/b7060d0183f8f23e4e1a8ce6222fa8fa51b26fbd
Author: Justin Bogner <mail at justinbogner.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILPrettyPrinter.cpp
M llvm/test/CodeGen/DirectX/CreateHandleFromBinding.ll
Log Message:
-----------
[DirectX] Fix printing of DXIL cbuffer info (#128698)
Make sure we're able to print cbuffer comments in a way that's
compatible with DXC.
Fixes #128562
Note: This is a re-commit because I somehow managed to get a completely
empty commit the first time.
Commit: 09832777d830e0fddff84bf36793ec4e453656b0
https://github.com/llvm/llvm-project/commit/09832777d830e0fddff84bf36793ec4e453656b0
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/cmake/caches/Release.cmake
Log Message:
-----------
[CMake][Release] Statically link ZSTD on all OSes (#128554)
This will make the binaries more portable.
Commit: cd4c30bb224e432d8cd37f375c138cbaada14f6c
https://github.com/llvm/llvm-project/commit/cd4c30bb224e432d8cd37f375c138cbaada14f6c
Author: Ashley Coleman <ascoleman at microsoft.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/CodeGenHLSL/cbuffer_align.hlsl
Log Message:
-----------
[HLSL][Sema] Fix Struct Size Calculation containing 16/32 bit scalars (#128086)
Fixes #119641
Update SemaHLSL to correctly calculate the alignment barrier for scalars
that are not 4 bytes wide
Commit: 2db8386867c5083980ff00bf2eae8937457ab9da
https://github.com/llvm/llvm-project/commit/2db8386867c5083980ff00bf2eae8937457ab9da
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/include/clang/AST/Decl.h
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/AST/Decl.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/AST/HLSL/default_cbuffer.hlsl
M clang/test/CodeGenHLSL/basic_types.hlsl
A clang/test/CodeGenHLSL/default_cbuffer.hlsl
Log Message:
-----------
[HLSL] Implement default constant buffer $Globals (2nd attempt) (#128589)
All variable declarations in the global scope that are not resources,
static or empty are implicitly added to implicit constant buffer
`$Globals`. They are created in `hlsl_constant` address space and
collected in an implicit `HLSLBufferDecl` node that is added to the AST
at the end of the translation unit. Codegen is the same as for explicit
constant buffers.
Fixes #123801
This is a second attempt to implement this feature. The first attempt
had to be reverted because of memory leaks. The problem was adding a
`SmallVector` member on `HLSLBufferDecl` node to represent a list of
default buffer declarations. When this vector needed to grow, it
allocated memory that was never released, because all memory used by AST
nodes must be allocated by `ASTContext` allocator and is released all at
once. Destructors on AST nodes are never called.
It this change the list of default buffer declarations is collected in a
`SmallVector` instance on `SemaHLSL`. The `HLSLBufDecl` representing
`$Globals` is created at the end of the translation unit when the number
of declarations is known, and the list is copied into an array allocated
by the `ASTContext` allocator.
Commit: c8b40867d144395ad3c306a3cf87f970e0f97f07
https://github.com/llvm/llvm-project/commit/c8b40867d144395ad3c306a3cf87f970e0f97f07
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
Log Message:
-----------
[AMDGPU][True16][CodeGen] test fix for uaddsat/usubsat true16 selection (#128784)
This is a NFC change. Update the test file and fix the build
https://github.com/llvm/llvm-project/pull/128233 is causing a build
issue. This is caused by PR
https://github.com/llvm/llvm-project/pull/127945 being merged while the
128233 is pending for review.
Commit: f3000d7d27fab1d1bbf1d848c6f84d3f91931326
https://github.com/llvm/llvm-project/commit/f3000d7d27fab1d1bbf1d848c6f84d3f91931326
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M flang/lib/Lower/ConvertVariable.cpp
M flang/test/Lower/CUDA/cuda-return01.cuf
M flang/test/Lower/CUDA/cuda-return02.cuf
Log Message:
-----------
[flang][cuda] Do not trigger automatic deallocation in main (#128789)
Similar to host flow, do not trigger automatic deallocation at then end
of the main program since anything could happen like a
cudaDevcieReset().
Commit: e350485595d0694dbf5847d8d0eff1fb3df56e3b
https://github.com/llvm/llvm-project/commit/e350485595d0694dbf5847d8d0eff1fb3df56e3b
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
A flang/test/Lower/CUDA/cuda-kernel-alloca-block.cuf
Log Message:
-----------
[flang][cuda] Set alloca block in cuf kernel (#128776)
Temporary created during lowering in a cuf kernel must be set in the cuf
kernel itself otherwise they will be allocated on the host.
Commit: b1a735b45dcc194ad9be08d057bc853ad1c1467b
https://github.com/llvm/llvm-project/commit/b1a735b45dcc194ad9be08d057bc853ad1c1467b
Author: Kai Sasaki <lewuathe at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Math/Transforms/ExpandPatterns.cpp
M mlir/test/Dialect/Math/expand-math.mlir
Log Message:
-----------
[mlir][math] expand-math pass assumes the static shaped type (#128299)
In the process of `expand-math` pass, the conversion of ceil op assumes
the static shaped type as input as it needs create 0 and 1 constant
values whose type is aligned with the op type.
Fixes https://github.com/llvm/llvm-project/issues/128275
Commit: da37c76ac621c64216e56ead3efe1bd569250ee2
https://github.com/llvm/llvm-project/commit/da37c76ac621c64216e56ead3efe1bd569250ee2
Author: Prakhar Dixit <75660779+Prakhar-Dixit at users.noreply.github.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/test/Dialect/Vector/vector-unroll-options.mlir
Log Message:
-----------
[mlir][vector] Add a check to ensure input vector rank equals target shape rank (#127706)
Fixes issue #126197
The crash is caused because, during IR transformation, the
vector-unrolling pass (using ExtractStridedSliceOp) attempts to slice an
input vector of higher rank using a target vector of lower rank, which
is not supported.
Specific example :
```
module {
func.func @func1() {
%cst_25 = arith.constant dense<3.718400e+04> : vector<4x2x2xf16>
%cst_26 = arith.constant dense<1.000000e+00> : vector<24x2x2xf32>
%47 = vector.fma %cst_26, %cst_26, %cst_26 : vector<24x2x2xf32>
%818 = scf.execute_region -> vector<24x2x2xf32> {
scf.yield %47 : vector<24x2x2xf32>
}
%823 = vector.extract_strided_slice %cst_25 {offsets = [2], sizes = [1], strides = [1]} : vector<4x2x2xf16> to vector<1x2x2xf16>
return
}
}
```
---------
Co-authored-by: Kai Sasaki <lewuathe at gmail.com>
Commit: 439de05848b22e76d4fb377ef28587b3eba2a4c5
https://github.com/llvm/llvm-project/commit/439de05848b22e76d4fb377ef28587b3eba2a4c5
Author: Jim Lin <jim at andestech.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
Log Message:
-----------
[RISCV] Rename function name to start with prefix vpreduce for consistency. (NFC)
Commit: a565f9eb2997ab1614cad326b93ab21810e39f32
https://github.com/llvm/llvm-project/commit/a565f9eb2997ab1614cad326b93ab21810e39f32
Author: Jim Lin <jim at andestech.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
Log Message:
-----------
[RISCV] The test for vp.reduce.fminimum/fmaximum with fixed-length should stay in fixed-vectors-reduction-fp-vp.ll. (NFC)
Commit: 01cc1d13cd0c54bd4c29185b052fa5c16285dca7
https://github.com/llvm/llvm-project/commit/01cc1d13cd0c54bd4c29185b052fa5c16285dca7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
Log Message:
-----------
[RISCV] Use Priv tablegen class for sf.cease instruction.
The encoding for sf.cease is only one bit different than wfi which
I believe was an intentional choice. wfi uses the Priv class so
this makes them consistent.
Commit: c53eb93dd7e93988b8456d317e3ebffa0c809fb9
https://github.com/llvm/llvm-project/commit/c53eb93dd7e93988b8456d317e3ebffa0c809fb9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
A llvm/test/CodeGen/Thumb2/peephole-opt-check-reg-sequence-compose-supports-subreg-index.ll
Log Message:
-----------
PeepholeOpt: Immediately check if a reg_sequence compose supports a subregister (#128279)
This is a quick fix for EXPENSIVE_CHECKS bot failures. I still think we
could
defer looking for a compatible subregister further up the use-def chain,
and
should be able to check compatibilty with the ultimate found source.
Commit: 8fc8a84e23471fe56214e68706addc712b5a2949
https://github.com/llvm/llvm-project/commit/8fc8a84e23471fe56214e68706addc712b5a2949
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Allow breaking before kw___attribute (#128623)
Fixes #74784
Commit: 31897e651a1aa69207806d497a7080e252c53ebe
https://github.com/llvm/llvm-project/commit/31897e651a1aa69207806d497a7080e252c53ebe
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/test/LTO/X86/coro.ll
M llvm/test/Other/new-pm-defaults.ll
M llvm/test/Other/new-pm-lto-defaults.ll
Log Message:
-----------
[LTO][Pipelines][Coro] De-duplicate Coro passes (#128654)
```
if (!isLTOPostLink(Phase))
CoroPM.addPass(CoroEarlyPass());
if (!isLTOPreLink(Phase))
// Other Coro passes
```
Followup to #126168.
Commit: 852923822fd085d304988c24f9b02edebe5e7903
https://github.com/llvm/llvm-project/commit/852923822fd085d304988c24f9b02edebe5e7903
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-literal.mir
Log Message:
-----------
[AMDGPU][NewPM] Port AMDGPUInsertDelayAlu to NPM (#128003)
Commit: 472ea0b7821fa8054906c7477e6089f2aa8e3a67
https://github.com/llvm/llvm-project/commit/472ea0b7821fa8054906c7477e6089f2aa8e3a67
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
Log Message:
-----------
[RISCV] Merge some of the Sifive decoder tables. (#128794)
This makes a single table for vector and another table for system. I
left sf.cease out of system because its not in custom encoding space.
The other system instructions are in the custom part of OPC_SYSTEM.
Commit: e927cf6653a9df804ca0556d8a5985f86ed9147c
https://github.com/llvm/llvm-project/commit/e927cf6653a9df804ca0556d8a5985f86ed9147c
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.h
M llvm/lib/Target/AArch64/CMakeLists.txt
M llvm/test/CodeGen/AArch64/machine-latecleanup-inlineasm.mir
Log Message:
-----------
Reland "[AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (#128… (#128662)
…471)"
Reland https://github.com/llvm/llvm-project/pull/128471
The Passes library was not linked in earlier.
Commit: e3ece07593b387dcb4a95deef6ce8a20b1bf1da3
https://github.com/llvm/llvm-project/commit/e3ece07593b387dcb4a95deef6ce8a20b1bf1da3
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.h
M llvm/lib/Target/AArch64/CMakeLists.txt
M llvm/test/CodeGen/AArch64/machine-latecleanup-inlineasm.mir
Log Message:
-----------
Revert "Reland "[AArch64][NPM] Chalk out the CodeGenPassBuilder for NPM (#128…" (#128819)
Reverts llvm/llvm-project#128662
Still a link error.
Commit: 98542a3d6d087e1baf6c90d134140e2ed858f823
https://github.com/llvm/llvm-project/commit/98542a3d6d087e1baf6c90d134140e2ed858f823
Author: Kunwar Grover <groverkss at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
M mlir/test/Dialect/Vector/linearize.mlir
M mlir/test/Dialect/Vector/scalar-vector-transfer-to-memref.mlir
M mlir/test/Dialect/Vector/vector-gather-lowering.mlir
Log Message:
-----------
[mlir][Vector] Move vector.extract canonicalizers for DenseElementsAttr to folders (#127995)
This PR moves vector.extract canonicalizers for DenseElementsAttr (splat
and non splat case) to folders. Folders are local, and it's always
better to implement a folder than a canonicalization pattern.
This PR is mostly NFC-ish, because the functionality mostly remains
same, but is now run as part of a folder, which is why some tests are
changed, because GreedyPatternRewriter tries to fold by default.
There is also a test change which makes the indices of a vector.extract
test dynamic. This is so that it doesn't fold away after this pr.
Commit: b5dd1fedc5dc3c2e76069ac7536b889915acc2ae
https://github.com/llvm/llvm-project/commit/b5dd1fedc5dc3c2e76069ac7536b889915acc2ae
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/VirtRegMap.cpp
M llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
M llvm/test/CodeGen/AMDGPU/issue48473.mir
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
M llvm/test/CodeGen/X86/inline-asm-assertion.ll
Log Message:
-----------
VirtRegRewriter: Fix verifier errors after regalloc failures (#128280)
Commit: 75aff78f64d2f915b38be1c3635eb6f0f9911514
https://github.com/llvm/llvm-project/commit/75aff78f64d2f915b38be1c3635eb6f0f9911514
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
Log Message:
-----------
RegAllocFast: Fix verifier errors after assigning to reserved registers (#128281)
Commit: fe13cb985c77902c0bc8f6f999d9b18d6b39ed01
https://github.com/llvm/llvm-project/commit/fe13cb985c77902c0bc8f6f999d9b18d6b39ed01
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/Passes.h
A llvm/include/llvm/CodeGen/RegAllocGreedyPass.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegAllocGreedy.h
M llvm/lib/Passes/PassBuilder.cpp
Log Message:
-----------
[CodeGen][NewPM] Port RegAllocGreedy to NPM (#119540)
Leaving out NPM command line support for the next patch.
Commit: 8dd609598e498faa34c7bdb777718d6c6622fa27
https://github.com/llvm/llvm-project/commit/8dd609598e498faa34c7bdb777718d6c6622fa27
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Support/Unix/Program.inc
M llvm/test/tools/llvm-rc/windres-preproc.test
Log Message:
-----------
Support: Do not check if a file exists before executing (#128821)
Let the actual syscall error if the file doesn't exist. This produces
a more standard "no such file or directory" phrasing of the error
message,
and avoids an extra step.
The same antipattern appears in the windows code, we should probably
fix that one too.
Commit: 3f648992bf317a3496c4d137374d2c1532423d1c
https://github.com/llvm/llvm-project/commit/3f648992bf317a3496c4d137374d2c1532423d1c
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
A clang/test/AST/ByteCode/libcxx/make_unique.cpp
Log Message:
-----------
[clang][bytecode] Fix initing incomplete arrays from ImplicitValueIni… (#128729)
…tExpr
If the ImplicitValueInitExpr is of incomplete array type, we ignore it
in its Visit function. This is a special case here, so pull out the
element type and zero the elements.
Commit: 29c5e4289f53a8abf0ffffb7074d2af2d4d0a26b
https://github.com/llvm/llvm-project/commit/29c5e4289f53a8abf0ffffb7074d2af2d4d0a26b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
A llvm/test/Transforms/InstCombine/AMDGPU/bitcast-fold-lane-ops.ll
M llvm/test/Transforms/InstCombine/AMDGPU/permlane64.ll
Log Message:
-----------
AMDGPU: Add baseline tests for bitcast + readlane intrinsics (#128493)
Commit: 2015626783aa7510ccdf6098f2112417cf56a8d0
https://github.com/llvm/llvm-project/commit/2015626783aa7510ccdf6098f2112417cf56a8d0
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/test/CXX/drs/cwg29xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[Clang] Implement CWG2918 'Consideration of constraints for address of overloaded function' (#127773)
Closes https://github.com/llvm/llvm-project/issues/122523
Commit: cdfcce48d5c290a77ab868fb62c18f6ba16e58df
https://github.com/llvm/llvm-project/commit/cdfcce48d5c290a77ab868fb62c18f6ba16e58df
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/include/llvm/Passes/MachinePassRegistry.def
Log Message:
-----------
[Passes] Fix a warning
This patch fixes:
llvm/include/llvm/Passes/MachinePassRegistry.def:202:6: error:
lambda capture 'PB' is not used [-Werror,-Wunused-lambda-capture]
Commit: a522c227a1d7d5dd4cd855a5fe4460193faf0856
https://github.com/llvm/llvm-project/commit/a522c227a1d7d5dd4cd855a5fe4460193faf0856
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/test/Dialect/Vector/vector-rewrite-narrow-types.mlir
A mlir/test/Dialect/Vector/vector-rewrite-subbyte-ext-and-trunci.mlir
Log Message:
-----------
[mlir][vector] Move tests for `rewriteAlignedSubByteInt{Ext|Trunc}` (nfc) (#126416)
Moves tests for `rewriteAlignedSubByteIntExt` and
`rewriteAlignedSubByteIntTrunc` into a dedicated files. Also adds +
fixes some comments.
This is merely for better organisation and so that it's easier to
identify the patterns and edge cases being tested.
Commit: ae839b02504a68a0dfe63ac8ec314d9d7a6ce8df
https://github.com/llvm/llvm-project/commit/ae839b02504a68a0dfe63ac8ec314d9d7a6ce8df
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang-tools-extra/clangd/ModulesBuilder.cpp
M clang-tools-extra/clangd/ProjectModules.h
M clang-tools-extra/clangd/ScanningProjectModules.cpp
M clang-tools-extra/clangd/unittests/PrerequisiteModulesTest.cpp
Log Message:
-----------
[clangd] [C++20] [Modules] Add scanning cache (#125988)
Previously, everytime we want to get a source file declaring a specific
module, we need to scan the whole projects again and again. The
performance is super bad. This patch tries to improve this by
introducing a simple cache.
Commit: 92d822245b0f034133fb958c1a067330236f9dea
https://github.com/llvm/llvm-project/commit/92d822245b0f034133fb958c1a067330236f9dea
Author: tangaac <tangyan01 at loongson.cn>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
A llvm/test/CodeGen/LoongArch/lsx/vec-sext.ll
A llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll
Log Message:
-----------
[LoongArch] Pre-commit tests for vector sext & zext (#128835)
Commit: e160c35c9ec69c099daeffdbca3cf4c94d3e05b9
https://github.com/llvm/llvm-project/commit/e160c35c9ec69c099daeffdbca3cf4c94d3e05b9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/RegAllocBase.cpp
M llvm/lib/CodeGen/RegAllocBase.h
M llvm/lib/CodeGen/RegAllocBasic.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
M llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
M llvm/test/CodeGen/AMDGPU/issue48473.mir
A llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
A llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
Log Message:
-----------
Reapply "RegAlloc: Fix verifier error after failed allocation (#119690)" (#128400)
Reapply "RegAlloc: Fix verifier error after failed allocation (#119690)"
This reverts commit 0c50054820799578be8f62b6fd2cc3fbc751c01e.
Reapply with more fixes to avoid expensive_checks failures. Make sure to
call splitSeparateComponents after shrinkToUses, and update the VirtRegMap
with the split registers. Also set undef on all physical register aliases to
the assigned register.
Move physreg handling. Not sure if necessary
Remove intervals from regunits. Not sure if necessary
Commit: 1a114fa302b48fc761a58a8d3be5962d92fa581b
https://github.com/llvm/llvm-project/commit/1a114fa302b48fc761a58a8d3be5962d92fa581b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/RegAllocBase.cpp
M llvm/lib/CodeGen/RegAllocBase.h
M llvm/lib/CodeGen/RegAllocBasic.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/VirtRegMap.cpp
A llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers-assertion-after-ra-failure.ll
R llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers-assertion-after-ra-failure.xfail.ll
M llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
M llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
M llvm/test/CodeGen/AMDGPU/issue48473.mir
M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
Log Message:
-----------
RegAlloc: Use new approach to handling failed allocations (#128469)
This fixes an assert after allocation failure.
Rather than collecting failed virtual registers and hacking
on the uses after the fact, directly hack on the uses and rewrite
the registers to the dummy assignment immediately.
Previously we were bypassing LiveRegMatrix and directly assigning
in the VirtRegMap. This resulted in inconsistencies where illegal
overlapping assignments were missing. Rather than try to hack in
some system to manage these in LiveRegMatrix (i.e. hacking around
cases with invalid iterators), avoid this by directly using the
physreg. This should also allow removal of special casing in
virtregrewriter for failed allocations.
Commit: d8bcb53780bf8e2f622380d5f4ccde96fa1d81a9
https://github.com/llvm/llvm-project/commit/d8bcb53780bf8e2f622380d5f4ccde96fa1d81a9
Author: LU-JOHN <John.Lu at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AMDGPU/shl64_reduce.ll
Log Message:
-----------
DAG: Preserve range metadata when load is narrowed (#128144)
In DAGCombiner.cpp preserve range metadata when load is narrowed to load
LSBs if original range metadata bounds can fit in the narrower type.
Utilize preserved range metadata to reduce 64-bit shl to 32-bit shl.
---------
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: b8d1f3d62746110ff0c969a136fc15f1d52f811d
https://github.com/llvm/llvm-project/commit/b8d1f3d62746110ff0c969a136fc15f1d52f811d
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/test/SemaTemplate/deduction-guide.cpp
Log Message:
-----------
[Clang] Fix an integer overflow issue in computing CTAD's parameter depth (#128704)
There were some cases where we computed incorrect template parameter
depths for synthesized CTAD, invalid as they might be, we still
shouldn't crash anyway.
Technically the only scenario in which the inner function template's
depth is 0 is when it lives within an explicit template specialization,
where the template parameter list is empty.
Fixes https://github.com/llvm/llvm-project/issues/128691
Commit: bd9e31ef1ea3b53122ca84d0e9e6dcd5901a2012
https://github.com/llvm/llvm-project/commit/bd9e31ef1ea3b53122ca84d0e9e6dcd5901a2012
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.cpp
Log Message:
-----------
[DWARFLinker] Avoid repeated hash lookups (NFC) (#128825)
Commit: e49c8d5d3d40d184665eae2c5c49df4fa4b7c6cc
https://github.com/llvm/llvm-project/commit/e49c8d5d3d40d184665eae2c5c49df4fa4b7c6cc
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/DebugInfo/LogicalView/Readers/LVCodeViewVisitor.cpp
Log Message:
-----------
[DebugInfo] Avoid repeated map lookups (NFC) (#128826)
Commit: 67d92cf3841660e9ba58a02223b7801e74db1051
https://github.com/llvm/llvm-project/commit/67d92cf3841660e9ba58a02223b7801e74db1051
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
Log Message:
-----------
[ExecutionEngine] Avoid repeated hash lookups (NFC) (#128827)
Commit: b2c8f66eea8119efd9ec2b3b0794946a7806c3c6
https://github.com/llvm/llvm-project/commit/b2c8f66eea8119efd9ec2b3b0794946a7806c3c6
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Passes/StandardInstrumentations.cpp
Log Message:
-----------
[Passes] Avoid repeated hash lookups (NFC) (#128828)
Commit: e264b0e85627d52e2c696c99f8937f7612f00228
https://github.com/llvm/llvm-project/commit/e264b0e85627d52e2c696c99f8937f7612f00228
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/ProfileData/InstrProf.cpp
Log Message:
-----------
[ProfileData] Avoid repeated hash lookups (NFC) (#128829)
Commit: ec9c2935e19171ce8004e1d970f9b7bf068d92a7
https://github.com/llvm/llvm-project/commit/ec9c2935e19171ce8004e1d970f9b7bf068d92a7
Author: lorenzo chelini <l.chelini at icloud.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
Log Message:
-----------
[MLIR][Bufferization] Remove `GEN_PASS_DEF_BUFFERIZATIONBUFFERIZE` (#128842)
It was related to the old bufferization mechanism, which has since been
retired.
Commit: 2d12c9e83f5ade9a2518ddfbed7ec438b2a5cb45
https://github.com/llvm/llvm-project/commit/2d12c9e83f5ade9a2518ddfbed7ec438b2a5cb45
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/RelayoutOpInterface.h
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] add missing header for RelayoutOptInterface
for a778930f85b6d17cf31ff0e15964a7c7116e2a9d
Commit: 13245cea11050f875891389ce36115c78aaedd4a
https://github.com/llvm/llvm-project/commit/13245cea11050f875891389ce36115c78aaedd4a
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M lldb/include/lldb/Symbol/UnwindPlan.h
M lldb/include/lldb/Target/ABI.h
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Plugins/ABI/AArch64/ABIMacOSX_arm64.cpp
M lldb/source/Plugins/ABI/AArch64/ABIMacOSX_arm64.h
M lldb/source/Plugins/ABI/AArch64/ABISysV_arm64.cpp
M lldb/source/Plugins/ABI/AArch64/ABISysV_arm64.h
M lldb/source/Plugins/ABI/ARC/ABISysV_arc.cpp
M lldb/source/Plugins/ABI/ARC/ABISysV_arc.h
M lldb/source/Plugins/ABI/ARM/ABIMacOSX_arm.cpp
M lldb/source/Plugins/ABI/ARM/ABIMacOSX_arm.h
M lldb/source/Plugins/ABI/ARM/ABISysV_arm.cpp
M lldb/source/Plugins/ABI/ARM/ABISysV_arm.h
M lldb/source/Plugins/ABI/Hexagon/ABISysV_hexagon.cpp
M lldb/source/Plugins/ABI/Hexagon/ABISysV_hexagon.h
M lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
M lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.h
M lldb/source/Plugins/ABI/MSP430/ABISysV_msp430.cpp
M lldb/source/Plugins/ABI/MSP430/ABISysV_msp430.h
M lldb/source/Plugins/ABI/Mips/ABISysV_mips.cpp
M lldb/source/Plugins/ABI/Mips/ABISysV_mips.h
M lldb/source/Plugins/ABI/Mips/ABISysV_mips64.cpp
M lldb/source/Plugins/ABI/Mips/ABISysV_mips64.h
M lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc.cpp
M lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc.h
M lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc64.cpp
M lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc64.h
M lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
M lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
M lldb/source/Plugins/ABI/SystemZ/ABISysV_s390x.cpp
M lldb/source/Plugins/ABI/SystemZ/ABISysV_s390x.h
M lldb/source/Plugins/ABI/X86/ABIMacOSX_i386.cpp
M lldb/source/Plugins/ABI/X86/ABIMacOSX_i386.h
M lldb/source/Plugins/ABI/X86/ABISysV_i386.cpp
M lldb/source/Plugins/ABI/X86/ABISysV_i386.h
M lldb/source/Plugins/ABI/X86/ABISysV_x86_64.cpp
M lldb/source/Plugins/ABI/X86/ABISysV_x86_64.h
M lldb/source/Plugins/ABI/X86/ABIWindows_x86_64.cpp
M lldb/source/Plugins/ABI/X86/ABIWindows_x86_64.h
M lldb/source/Plugins/UnwindAssembly/x86/UnwindAssembly-x86.cpp
M lldb/source/Symbol/FuncUnwinders.cpp
M lldb/source/Target/RegisterContextUnwind.cpp
Log Message:
-----------
[lldb] Modernize ABI-based unwind plan creation (#128505)
Replace the by-ref return value with an actual result.
Commit: 5cbff437fadd4c2983fb73e727c82044ae269a6f
https://github.com/llvm/llvm-project/commit/5cbff437fadd4c2983fb73e727c82044ae269a6f
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/test/Transforms/InstCombine/onehot_merge.ll
Log Message:
-----------
[InstCombine] Test for trunc to i1 in foldLogOpOfMaskedICmps.
Commit: a98c2940dbc04bf84de95cb1893694cdcbc4f5fe
https://github.com/llvm/llvm-project/commit/a98c2940dbc04bf84de95cb1893694cdcbc4f5fe
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avx2-arith.ll
Log Message:
-----------
[X86] Handle multiple use freeze(undef) in LowerAVXCONCAT_VECTORS as zero vectors (#128830)
Follow up of
https://github.com/llvm/llvm-project/commit/ee52af74d8e5e3083cf5195d11c92f8df95b8072
Handles the multiple use come from different vectors:
https://godbolt.org/z/GMb3Endhr
Commit: 0ba2000b3cece317fd0ec6c433e49185885c4ef7
https://github.com/llvm/llvm-project/commit/0ba2000b3cece317fd0ec6c433e49185885c4ef7
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/quant-test.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
Log Message:
-----------
[mlir][tosa] Enhance the conv2d verifier (#128693)
This commit adds additional checks to the conv2d verifier that check
error_if conditions from the tosa specification. Notably, it adds
padding, stride and dilation invalid value checking, output height and
width checking and bias size checking.
Signed-off-by: Luke Hutton <luke.hutton at arm.com>
Commit: 28cf323e8717cd57984b5d5b0d7c90cbce0fc54f
https://github.com/llvm/llvm-project/commit/28cf323e8717cd57984b5d5b0d7c90cbce0fc54f
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/test/Transforms/InstCombine/scalable-const-fp-splat.ll
M llvm/test/Transforms/InstCombine/scalable-select.ll
M llvm/test/Transforms/InstCombine/select-masked_gather.ll
M llvm/test/Transforms/InstCombine/udiv-pow2-vscale.ll
M llvm/test/Transforms/InstCombine/vector_gep1.ll
M llvm/test/Transforms/InstSimplify/ConstProp/extractelement-vscale.ll
Log Message:
-----------
[LLVM] Port a few InstCombine tests to use splat instead of shufflevector.
Commit: 575656877f1f42a4996a551caa7a2c9145810813
https://github.com/llvm/llvm-project/commit/575656877f1f42a4996a551caa7a2c9145810813
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
R llvm/test/Transforms/InstCombine/AArch64/sve-inst-combine-cmpne.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-abs-srshl.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-all-active-lanes-cvt.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-fmul-idempotency.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-fmul_u-idempotency.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul-idempotency.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul_u-idempotency.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-cmpne.ll
Log Message:
-----------
[LLVM][AArch64] Reduce uses of "undef" in SVE InstCombine tests.
Also removes a largely duplicate test file and changes the other
one to use autogenerated CHECK lines.
Commit: 6f2345a20e361c7748578b0c3bae37589989e3b8
https://github.com/llvm/llvm-project/commit/6f2345a20e361c7748578b0c3bae37589989e3b8
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/test/CodeGen/AArch64/pr49781.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
M llvm/test/CodeGen/AArch64/sve-gep.ll
M llvm/test/CodeGen/AArch64/sve-int-log.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
M llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
M llvm/test/CodeGen/AArch64/sve-vselect-imm.ll
Log Message:
-----------
[LLVM][AArch64] Change SVE CodeGen tests to use splat().
The affected tests were using the longwinded syntax for constant
splats. By using the splat() syntax the tests get simplified whilst
also removing the need for "undef".
Commit: 01371d64a91ed65d18670a1ee570058a0678ce0b
https://github.com/llvm/llvm-project/commit/01371d64a91ed65d18670a1ee570058a0678ce0b
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll
M llvm/test/CodeGen/AArch64/aarch64-sve-and-combine-crash.ll
M llvm/test/CodeGen/AArch64/dag-combine-insert-subvector.ll
M llvm/test/CodeGen/AArch64/sub-splat-sub.ll
M llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
M llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
M llvm/test/CodeGen/AArch64/sve-extract-element.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-addressing-modes.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-mask-opt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
M llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
M llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll
M llvm/test/CodeGen/AArch64/sve-insert-element.ll
M llvm/test/CodeGen/AArch64/sve-insert-vector-to-predicate-load.ll
M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-scaled-offset.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-unscaled-offset.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-mask-ldst-ext.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-scalar-to-vec.ll
M llvm/test/CodeGen/AArch64/sve-ld1r.ll
M llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-32b-signed-scaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-32b-signed-unscaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-32b-unsigned-scaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-32b-unsigned-unscaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-64b-scaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-64b-unscaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-vec-plus-imm.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-vec-plus-reg.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-nonext.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter.ll
M llvm/test/CodeGen/AArch64/sve-nontemporal-masked-ldst.ll
M llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
M llvm/test/CodeGen/AArch64/sve-split-load.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reshuffle.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
M llvm/test/CodeGen/AArch64/sve-unary-movprfx.ll
M llvm/test/CodeGen/AArch64/sve-uunpklo-load-uzp1-store-combine.ll
M llvm/test/CodeGen/AArch64/sve-vector-compress.ll
M llvm/test/CodeGen/AArch64/sve-vector-splat.ll
M llvm/test/CodeGen/AArch64/sve-vl-arith.ll
M llvm/test/CodeGen/AArch64/sve2-unary-movprfx.ll
M llvm/test/CodeGen/AArch64/vector-insert-dag-combines.ll
Log Message:
-----------
[LLVM][AArch64] Reduce uses of "undef" in SVE CodeGen tests.
Using "poison" better reflects realworld generated IR. The main idioms
ported are:
* Inserting into an undefined vector.
* Vector splats.
* Masked load/gather operations with an undefined passthrough.
Commit: d5038b3774485d617e1300cf2f7b98c2460b9042
https://github.com/llvm/llvm-project/commit/d5038b3774485d617e1300cf2f7b98c2460b9042
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M libclc/CMakeLists.txt
M libclc/amdgcn/lib/SOURCES
R libclc/amdgcn/lib/math/ldexp.cl
A libclc/clc/include/clc/math/clc_ldexp.h
A libclc/clc/include/clc/math/clc_ldexp.inc
A libclc/clc/lib/amdgcn/SOURCES
A libclc/clc/lib/amdgcn/math/clc_ldexp_override.cl
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/math/clc_ldexp.cl
M libclc/clspv/lib/SOURCES
R libclc/generic/include/math/clc_ldexp.h
M libclc/generic/lib/SOURCES
R libclc/generic/lib/math/clc_ldexp.cl
M libclc/generic/lib/math/ldexp.cl
M libclc/generic/lib/math/ldexp.inc
M libclc/spirv/lib/SOURCES
Log Message:
-----------
[libclc] Move __clc_ldexp to CLC library (#126078)
This function was already conceptually in the CLC namespace - this just
formally moves it over.
Note however that this commit marks a change in how libclc functions may
be overridden by targets.
Until now we have been using a purely build-system-based approach where
targets could register identically-named files which took responsibility
for the implementation of the builtin in its entirety.
This system wasn't well equipped to deal with AMD's overriding of
__clc_ldexp for only a subset of types, and furthermore conditionally on
a pre-defined macro.
One option for handling this would be to require AMD to duplicate code
for the versions of __clc_ldexp it's *not* interested in overriding. We
could also make it easier for targets to re-define CLC functions through
macros or .inc files. Both of these have obvious downsides. We could
also keep AMD's overriding in the OpenCL layer and bypass CLC
altogether, but this has limited use.
We could use weak linkage on the "base" implementations of CLC
functions, and allow targets to opt-in to providing their own
implementations on a much finer granularity. This commit supports this
as a proof of concept; we could expand it to all CLC builtins if
accepted.
Note that the existing filename-based "claiming" approach is still in
effect, so targets have to name their overrides differently to have both
files compiled. This could also be refined.
Commit: 178b9e5375dd42a4b590803a81b3831923288c91
https://github.com/llvm/llvm-project/commit/178b9e5375dd42a4b590803a81b3831923288c91
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
A llvm/test/Transforms/MergeFunc/linkonce.ll
Log Message:
-----------
[MergeFunc] Add linkonce test with discardable functions.
Commit: 900220d444257633cc7d1be1475d4da1be58e0ed
https://github.com/llvm/llvm-project/commit/900220d444257633cc7d1be1475d4da1be58e0ed
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Analysis/CostModel.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
A llvm/test/Analysis/CostModel/AArch64/sincos.ll
M llvm/test/Analysis/CostModel/AMDGPU/frexp.ll
Log Message:
-----------
[CostModel] Handle vector struct results and cost `llvm.sincos` (#123210)
This patch updates the cost model to cost intrinsics that return
multiple values (in structs) correctly. Previously, the cost model only
thought intrinsics that return `VectorType` need scalarizing, which
meant it cost intrinsics that return multiple vectors (that need
scalarizing) way too cheap (giving it the cost of a single function
call).
This patch also adds a custom cost for llvm.sincos when a vector
function library is available, as certain VFs can be expanded (later in
code gen) to a vector function, reducing the cost to a single call (+
the possible loads from the vector function returns values via output
pointers).
Commit: 5f4d1f74004d3e4699b5c8b05edd2050f8456ee8
https://github.com/llvm/llvm-project/commit/5f4d1f74004d3e4699b5c8b05edd2050f8456ee8
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M libclc/CMakeLists.txt
M libclc/clc/lib/generic/math/clc_ldexp.cl
Log Message:
-----------
[libclc] Make CLC library warning-free (#128864)
There is a long-standing workaround in the libclc build system that
silences a warning about the use of parentheses in bitwise conditional
operations.
In an effort to remove this workaround, this commit re-enables the
warning on the internal CLC library, where most of the bodies of the
builtins will eventually be defined. Thus as we move builtin
implementations into this library, the warnings will trigger and we can
clean up the codebase as we go.
As it happens the only instance in the CLC library which triggered the
warning was in __clc_ldexp.
Commit: 5231736329224fa3f812c22e1e5250e776956550
https://github.com/llvm/llvm-project/commit/5231736329224fa3f812c22e1e5250e776956550
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-s-add-copy-to-vgpr.mir
M llvm/test/CodeGen/AMDGPU/fold-readlane.mir
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll
M llvm/test/CodeGen/AMDGPU/licm-valu.mir
M llvm/test/CodeGen/AMDGPU/licm-wwm.mir
M llvm/test/CodeGen/AMDGPU/live-interval-bug-in-rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.append.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.consume.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.m0.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.ttracedata.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ptr.ll
M llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
M llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir
M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies-copy-to-sgpr.mir
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
Log Message:
-----------
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
M0 can only be written to by the SALU, so `v_readfirstlane_b32 m0` is
effectively useless. Represent this by restricting the dest RC of that
instruction to `SReg_32_XM0` which excludes M0.
There is a lot of test changes due to the register class changing, but
most changes are trivial. In some cases, an extra register and
`s_mov_b32` is needed.
Fixes SWDEV-513269
Commit: a00586171cdf835148c66704a877740a9f742a3a
https://github.com/llvm/llvm-project/commit/a00586171cdf835148c66704a877740a9f742a3a
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang-tools-extra/clang-tidy/performance/UnnecessaryValueParamCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/performance/unnecessary-value-param.rst
M clang-tools-extra/test/clang-tidy/checkers/performance/unnecessary-value-param.cpp
Log Message:
-----------
[clang-tidy]improve performance-unnecessary-value-param performance (#128383)
Tolerate fix-it breaking compilation when functions is used as pointers.
`isReferencedOutsideOfCallExpr` will visit the whole translate unit for
each matched function decls. It will waste lots of cpu time in some big
cpp files.
But the benefits of this validation are limited. Lots of function usage
are out of current translation unit.
After removing this validation step, the check profiling changes from
5.7 to 1.1 in SemaExprCXX.cpp, which is similar to version 18.
Commit: 8138d85f630726d2ddbf4a7950683c7db3853eb8
https://github.com/llvm/llvm-project/commit/8138d85f630726d2ddbf4a7950683c7db3853eb8
Author: David Tarditi <d_tarditi at apple.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/UndefinedAssignmentChecker.cpp
M clang/test/Analysis/Inputs/expected-plists/edges-new.mm.plist
M clang/test/Analysis/Inputs/expected-plists/plist-output.m.plist
M clang/test/Analysis/a_flaky_crash.cpp
M clang/test/Analysis/analysis-after-multiple-dtors.cpp
M clang/test/Analysis/array-init-loop.cpp
M clang/test/Analysis/array-punned-region.c
M clang/test/Analysis/builtin_overflow_notes.c
M clang/test/Analysis/call-invalidation.cpp
M clang/test/Analysis/ctor-array.cpp
M clang/test/Analysis/ctor.mm
M clang/test/Analysis/diagnostics/no-store-func-path-notes.m
M clang/test/Analysis/fread.c
M clang/test/Analysis/implicit-ctor-undef-value.cpp
M clang/test/Analysis/initialization.c
M clang/test/Analysis/initialization.cpp
M clang/test/Analysis/kmalloc-linux.c
M clang/test/Analysis/malloc-annotations.c
M clang/test/Analysis/malloc.c
M clang/test/Analysis/misc-ps.c
M clang/test/Analysis/operator-calls.cpp
M clang/test/Analysis/stack-addr-ps.cpp
M clang/test/Analysis/undef-buffers.c
M clang/test/Analysis/uninit-const.c
M clang/test/Analysis/uninit-const.cpp
M clang/test/Analysis/uninit-structured-binding-array.cpp
M clang/test/Analysis/uninit-structured-binding-struct.cpp
M clang/test/Analysis/uninit-structured-binding-tuple.cpp
M clang/test/Analysis/uninit-vals.m
M clang/test/Analysis/zero-size-non-pod-array.cpp
Log Message:
-----------
[analyzer] Update the undefined assignment checker diagnostics to not use the term 'garbage' (#126596)
A clang user pointed out that messages for the static analyzer undefined
assignment checker use the term ‘garbage’, which might have a negative
connotation to some users. This change updates the messages to use the
term ‘uninitialized’. This is the usual reason why a value is undefined
in the static analyzer and describes the logical error that a programmer
should take action to fix.
Out-of-bounds reads can also produce undefined values in the static
analyzer. The right long-term design is to have to the array bounds
checker cover out-of-bounds reads, so we do not cover that case in the
updated messages. The recent improvements to the array bounds checker
make it a candidate to add to the core set of checkers.
rdar://133418644
Commit: aace6a2f9d8bffd84a225ef76633421ff541a5d0
https://github.com/llvm/llvm-project/commit/aace6a2f9d8bffd84a225ef76633421ff541a5d0
Author: Luke Quinn <quic_lquinn at quicinc.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/xqcia-invalid.s
M llvm/test/MC/RISCV/xqcia-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Xqcia 0.4 The spec was recently updated, this changes the name in the TD files associated and increments the Extension number in the clang driver. This is mostly a MC change as there is no other generated code for these instructions yet.
Signed-off-by: Luke Quinn <quic_lquinn at quicinc.com>
Commit: 0f0d3fb6b59b27628a05f2da536b0294c99d61bc
https://github.com/llvm/llvm-project/commit/0f0d3fb6b59b27628a05f2da536b0294c99d61bc
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umax.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umin.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
M llvm/test/CodeGen/AMDGPU/wqm.mir
Log Message:
-----------
[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)
See #128851 - this is the same patch, but for v_readlane_b32.
This instruction is used much less often so there were less changes
required.
Commit: 83ccab35d4ae2164fd3a8c039bcfcc0c8a5780bd
https://github.com/llvm/llvm-project/commit/83ccab35d4ae2164fd3a8c039bcfcc0c8a5780bd
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
Log Message:
-----------
PeepholeOpt: Remove pointless check for subregister def (#128850)
Subregister defs are illegal in SSA
Commit: 3c4fa5a20aff390959385bf959a8c0b87e81d36c
https://github.com/llvm/llvm-project/commit/3c4fa5a20aff390959385bf959a8c0b87e81d36c
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
A llvm/test/Transforms/MergeFunc/metadata-call-arguments.ll
Log Message:
-----------
[MergeFunc] Add tests showing incorrect handling of metadata call args.
Commit: a5d8b7aeb6b360f20eec88715081ecfdb286b83d
https://github.com/llvm/llvm-project/commit/a5d8b7aeb6b360f20eec88715081ecfdb286b83d
Author: David Green <david.green at arm.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/div.ll
M llvm/test/Analysis/CostModel/AArch64/div_cte.ll
M llvm/test/Analysis/CostModel/AArch64/fshl.ll
M llvm/test/Analysis/CostModel/AArch64/fshr.ll
M llvm/test/Analysis/CostModel/AArch64/rem.ll
M llvm/test/Analysis/CostModel/AArch64/sve-div.ll
M llvm/test/Analysis/CostModel/AArch64/sve-rem.ll
Log Message:
-----------
[AArch64] Improve urem by constant costs (#122236)
A urem by a constant, much like a udiv by a constant, can be expanded
into a series of mul/add/shift instructions. The exact sequence of
instructions depends on the constants and the types.
If the constant is a power-2 then a shift / and will be used, so the
cost will be 1. This canonicalization happens relatively early so this
likely has very little effect in practice (it does help the cost of
funnel shifts).
For a non-power 2 the code for div will expand to a series of UMULH +
Add + Shift + Add, depending on the constant. urem is generally udiv +
mul + sub, so involves a few extra instructions. The UMULH is not always
available, i32 will use umull+shift, and vector types will use
umull+shift or umull+umull2+uzp depending on the vector size. v2i64 will
be scalarized because there is no mul available. SVE does have a UMULH
instruction.
The end result is that the costs should be closer to reality, with
scalable types a little lower cost than the fixed-width versions. (In
the future we might be able to use umulh for fixed-width when the SVE
instruction is available, but for the moment this should favour scalable
vectorization a little).
I've tried to make this patch only apply to constant UREM/UDIV
instructions. SDIV and SREM are left until a later patch to prevent this
becoming too complex. The funnel shift costs are changing as it believes
it will need a urem to clamp the shift amount, which should be a power-2
value for most common types.
Commit: 15fbdc2b9635b75f431a26b89b48fe03e7ed9d5c
https://github.com/llvm/llvm-project/commit/15fbdc2b9635b75f431a26b89b48fe03e7ed9d5c
Author: Ricardo Jesus <rjj at nvidia.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/test/CodeGen/AArch64/sve-vector-bits-codegen.c
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/alloca-load-store-scalable-array.ll
M llvm/test/CodeGen/AArch64/alloca-load-store-scalable-struct.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
M llvm/test/CodeGen/AArch64/nontemporal-load.ll
M llvm/test/CodeGen/AArch64/sinksplat.ll
M llvm/test/CodeGen/AArch64/sme-framelower-use-bp.ll
M llvm/test/CodeGen/AArch64/sme-peephole-opts.ll
M llvm/test/CodeGen/AArch64/sme-pstate-sm-changing-call-disable-coalescing.ll
M llvm/test/CodeGen/AArch64/sme-streaming-interface.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-faminmax.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlall.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-rshl.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-sqdmulh.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-vdot.ll
M llvm/test/CodeGen/AArch64/spillfill-sve.ll
M llvm/test/CodeGen/AArch64/split-vector-insert.ll
M llvm/test/CodeGen/AArch64/stack-guard-sve.ll
M llvm/test/CodeGen/AArch64/stack-hazard.ll
M llvm/test/CodeGen/AArch64/sve-aliasing.ll
M llvm/test/CodeGen/AArch64/sve-alloca.ll
M llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
M llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
M llvm/test/CodeGen/AArch64/sve-dead-masked-store.ll
M llvm/test/CodeGen/AArch64/sve-extload-icmp.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll
M llvm/test/CodeGen/AArch64/sve-fp-reduce-fadda.ll
M llvm/test/CodeGen/AArch64/sve-fp.ll
M llvm/test/CodeGen/AArch64/sve-fpext-load.ll
M llvm/test/CodeGen/AArch64/sve-fptrunc-store.ll
M llvm/test/CodeGen/AArch64/sve-insert-element.ll
M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
M llvm/test/CodeGen/AArch64/sve-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-ld1r.ll
M llvm/test/CodeGen/AArch64/sve-llrint.ll
M llvm/test/CodeGen/AArch64/sve-load-store-strict-align.ll
M llvm/test/CodeGen/AArch64/sve-lrint.ll
M llvm/test/CodeGen/AArch64/sve-lsrchain.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter-legalize.ll
M llvm/test/CodeGen/AArch64/sve-min-max-pred.ll
M llvm/test/CodeGen/AArch64/sve-pr92779.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
M llvm/test/CodeGen/AArch64/sve-reassocadd.ll
M llvm/test/CodeGen/AArch64/sve-redundant-store.ll
M llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
M llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll
M llvm/test/CodeGen/AArch64/sve-split-load.ll
M llvm/test/CodeGen/AArch64/sve-split-store.ll
M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-stack-frame-layout.ll
M llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll
M llvm/test/CodeGen/AArch64/sve-vector-compress.ll
M llvm/test/CodeGen/AArch64/sve2-intrinsics-combine-rshrnb.ll
M llvm/test/CodeGen/AArch64/sve2-rsh.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx4.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
M llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll
Log Message:
-----------
[AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (#127837)
Currently, given:
```cpp
svuint8_t foo(uint8_t *x) {
return svld1(svptrue_b8(), x);
}
```
We generate:
```gas
foo:
ptrue p0.b
ld1b { z0.b }, p0/z, [x0]
ret
```
However, on little-endian and with unaligned memory accesses allowed, we
could instead be using LDR as follows:
```gas
foo:
ldr z0, [x0]
ret
```
The second form avoids the predicate dependency.
Likewise for other types and stores.
Commit: 4277c21059a80fdd915aef9abd7be3d2b161f1b0
https://github.com/llvm/llvm-project/commit/4277c21059a80fdd915aef9abd7be3d2b161f1b0
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/divs-with-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-step.ll
M llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/pr54634.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-predication.ll
M llvm/test/Transforms/LoopVectorize/create-induction-resume.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/LoopVectorize/induction-step.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization-2.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/no_outside_user.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_hcfg_construction.ll
M llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/scalable-iv-outside-user.ll
M llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
Log Message:
-----------
[VPlan] Introduce explicit broadcasts for live-ins. (#124644)
Add a new VPInstruction::Broadcast opcode and use it to materialize
explicit broadcasts of live-ins. The initial patch only materlizes the
broadcasts if the vector preheader dominates all uses that need it.
Later patches will pick the best valid insert point, thus retiring
implicit hoisting of broadcasts from VPTransformsState::get().
PR: https://github.com/llvm/llvm-project/pull/124644
Commit: 8634635d689c5a7adfb19cde4a313d7c02e95194
https://github.com/llvm/llvm-project/commit/8634635d689c5a7adfb19cde4a313d7c02e95194
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/RegAllocFast.cpp
Log Message:
-----------
RegAllocFast: Stop reading uninitalized memory
Found by msan.
==8138==WARNING: MemorySanitizer: use-of-uninitialized-value
#0 0x559016395beb in allocVirtRegUndef llvm/lib/CodeGen/RegAllocFast.cpp:1010:6
Commit: 0f6240c4ddc815283f7bd42fe80847295de4a92c
https://github.com/llvm/llvm-project/commit/0f6240c4ddc815283f7bd42fe80847295de4a92c
Author: Chris B <chris.bieneman at me.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/lib/Parse/ParseHLSL.cpp
M clang/test/SemaHLSL/cb_error.hlsl
Log Message:
-----------
[HLSL] Allow EmptyDecl in cbuffer/tbuffer (#128250)
We do handle EmptyDecls in codegen already as of #124886, but we were
blocking them in Sema. EmptyDecls tend to be caused by extra semicolons
which are not illegal.
Fixes #128238
Commit: 56379b29042db9dfc63e74f065cc50b7fb01eddf
https://github.com/llvm/llvm-project/commit/56379b29042db9dfc63e74f065cc50b7fb01eddf
Author: Peng Liu <winner245 at hotmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M libcxx/include/bitset
M libcxx/test/std/utilities/template.bitset/bitset.members/flip_all.pass.cpp
M libcxx/test/std/utilities/template.bitset/bitset_test_cases.h
Log Message:
-----------
Simplify flip() for std::bitset (#120807)
This PR simplifies the internal bitwise logic of the `flip()` function
for `std::bitset`.
Commit: 2c1df2206189be8550a0e36a39cc185e9e3e0051
https://github.com/llvm/llvm-project/commit/2c1df2206189be8550a0e36a39cc185e9e3e0051
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/RegAllocFast.cpp
Log Message:
-----------
RegAllocFast: Fix 8634635d689c5a7adfb19cde4a313d7c02e95194 to not trip assertions
Commit: defe43bbffb0d25ec468f0e54b20548ec192ff90
https://github.com/llvm/llvm-project/commit/defe43bbffb0d25ec468f0e54b20548ec192ff90
Author: Chris B <chris.bieneman at me.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/test/CodeGenHLSL/builtins/abs.hlsl
Log Message:
-----------
Add unsigned integer overloads for abs (#128257)
This seems silly, but DXC supports unsigned integer versions of abs that
are just no-ops. This adds the overloads for source compatability
because apparently users actually use them...
Fixes #128249
Commit: 8dd8e5f7d692cc43f4322f04034f5c472381aa43
https://github.com/llvm/llvm-project/commit/8dd8e5f7d692cc43f4322f04034f5c472381aa43
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/DeclID.h
A clang/include/clang/Basic/BuiltinTemplates.td
M clang/include/clang/Basic/Builtins.h
M clang/include/clang/Basic/CMakeLists.txt
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/Lex/PPMacroExpansion.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/utils/TableGen/CMakeLists.txt
A clang/utils/TableGen/ClangBuiltinTemplatesEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
Log Message:
-----------
[Clang] Add BuiltinTemplates.td to generate code for builtin templates (#123736)
This makes it significantly easier to add new builtin templates, since
you only have to modify two places instead of a dozen or so.
The `BuiltinTemplates.td` could also be extended to generate
documentation from it in the future.
Commit: 7f332423b090abb396adb078000e0fa4958306ea
https://github.com/llvm/llvm-project/commit/7f332423b090abb396adb078000e0fa4958306ea
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/test/Transforms/MemCpyOpt/stack-move.ll
Log Message:
-----------
[MemCpyOpt] Add stack move test with ret-only capture (NFC)
From:
https://github.com/llvm/llvm-project/pull/125880#issuecomment-2685231008
Commit: 1b17d1ee6e6c9174d32d0bfb6b304917b2dcb2f3
https://github.com/llvm/llvm-project/commit/1b17d1ee6e6c9174d32d0bfb6b304917b2dcb2f3
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
Log Message:
-----------
[X86] Allow select(cond,pshufb,pshufb) -> or(pshufb,pshufb) fold to peek through bitcasts (#128876)
Peek through one use bitcasts and rescale the condition mask to a vXi8 type to allow more aggressive use of pshufb zeroing.
Commit: 35bf925f7ea95e71208a839cf4b02de2ee473f75
https://github.com/llvm/llvm-project/commit/35bf925f7ea95e71208a839cf4b02de2ee473f75
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp
M llvm/test/CodeGen/RISCV/rvv/expandload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
A llvm/test/CodeGen/RISCV/rvv/vmv0-elimination.mir
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
Log Message:
-----------
[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination
This fixes a crash reported at
https://github.com/llvm/llvm-project/pull/126850#issuecomment-2685166388,
where we may leave around a COPY to vmv0 after peeking through it.
Even though the COPY is dead, there's no pass between vmv0 elimination
and regalloc that will delete it so regalloc will try to allocate
something for it.
The test showcasing this is added in vmv0-elimination.mir. Removing
the dead COPY results in changes in spills in the >= LMUL 16 VP tests,
but it's worth noting that these tests are very noisy and not
representative of real world code.
Commit: ea294e3f1d3ca03a3a7e65a61d6b3945cc405200
https://github.com/llvm/llvm-project/commit/ea294e3f1d3ca03a3a7e65a61d6b3945cc405200
Author: Arnab Dutta <85476402+arnab-polymage at users.noreply.github.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
Log Message:
-----------
[MLIR][Affine] Make isValidLoopInterchangePermutation efficient (#128863)
Avoid doing dependency checks for the trivial case when size of `loops`
is 1.
Commit: fd08b0793fbb1729872a89ae9a7f1be662b4947f
https://github.com/llvm/llvm-project/commit/fd08b0793fbb1729872a89ae9a7f1be662b4947f
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[bazel] Port 8dd8e5f7d692cc43f4322f04034f5c472381aa43
Commit: 5c8e22bb2653b5229cb90b9e28c4a19692a2445b
https://github.com/llvm/llvm-project/commit/5c8e22bb2653b5229cb90b9e28c4a19692a2445b
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[bazel] Export BuiltinTemplates.inc from clang:basic
Commit: 3c8c0d4d8d9bbc160d160e683f7a74fd28574dc6
https://github.com/llvm/llvm-project/commit/3c8c0d4d8d9bbc160d160e683f7a74fd28574dc6
Author: Marco Elver <elver at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/lib/Analysis/ThreadSafety.cpp
M clang/test/Sema/warn-thread-safety-analysis.c
Log Message:
-----------
Thread Safety Analysis: Handle address-of followed by dereference
Correctly analyze expressions where the address of a guarded variable is
taken and immediately dereferenced, such as (*(type-specifier *)&x).
Previously, such patterns would result in false negatives.
Pull Request: https://github.com/llvm/llvm-project/pull/127396
Commit: de10e44b6fe7f3d3cfde3afd8e1222d251172ade
https://github.com/llvm/llvm-project/commit/de10e44b6fe7f3d3cfde3afd8e1222d251172ade
Author: Marco Elver <elver at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/docs/ThreadSafetyAnalysis.rst
M clang/include/clang/Analysis/Analyses/ThreadSafety.h
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Analysis/ThreadSafety.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/test/Sema/warn-thread-safety-analysis.c
M clang/test/SemaCXX/warn-thread-safety-analysis.cpp
Log Message:
-----------
Thread Safety Analysis: Support warning on passing/returning pointers to guarded variables
Introduce `-Wthread-safety-pointer` to warn when passing or returning
pointers to guarded variables or guarded data. This is is analogous to
`-Wthread-safety-reference`, which performs similar checks for C++
references.
Adding checks for pointer passing is required to avoid false negatives
in large C codebases, where data structures are typically implemented
through helpers that take pointers to instances of a data structure.
The feature is planned to be enabled by default under `-Wthread-safety`
in the next release cycle. This gives time for early adopters to address
new findings.
Pull Request: https://github.com/llvm/llvm-project/pull/127396
Commit: eeb8c2085fb96dbb59446ba1d142803b12a43e18
https://github.com/llvm/llvm-project/commit/eeb8c2085fb96dbb59446ba1d142803b12a43e18
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] Fix a warning
This patch fixes:
llvm/lib/Target/X86/X86ISelLowering.cpp:47257:15: error: comparison
of integers of different signs: 'int' and 'size_t' (aka 'unsigned
long') [-Werror,-Wsign-compare]
Commit: 30b021ffa483e7c0ea9b3b0526eb4597b7e31486
https://github.com/llvm/llvm-project/commit/30b021ffa483e7c0ea9b3b0526eb4597b7e31486
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
Log Message:
-----------
[lldb] Deindent UnwindAssemblyInstEmulation (#128874)
by three levels using early returns/continues.
Commit: bb62af7d14f7fe1301311234352f9652d45ba354
https://github.com/llvm/llvm-project/commit/bb62af7d14f7fe1301311234352f9652d45ba354
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
Log Message:
-----------
[AMDGPU][True16][CodeGen] true16 codegen for valu op (#124797)
true16 selection for valu ops, enable `real-true16` attribute and update
the codegen test
Commit: a955426a16bcbb9bf05eb0e3894663dff4983b00
https://github.com/llvm/llvm-project/commit/a955426a16bcbb9bf05eb0e3894663dff4983b00
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/literals.cpp
Log Message:
-----------
[clang][bytecode] Handle UsingDirectiveDecls (#128888)
By ignoring them.
Commit: 15ee9d91fbb55a507a8f0bce7d3d66a825c6ec30
https://github.com/llvm/llvm-project/commit/15ee9d91fbb55a507a8f0bce7d3d66a825c6ec30
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M lldb/include/lldb/API/SBSaveCoreOptions.h
M lldb/unittests/API/CMakeLists.txt
M lldb/unittests/API/SBCommandInterpreterTest.cpp
Log Message:
-----------
[lldb] Build the API unittests with -Wdocumentation (#128893)
The LLDB SB API headers should be -Wdocumentation clean as they might
get included by projects building with -Wdocumentation. Although I'd
love for all of LLDB to be clean, we're pretty far removed from that
goal. Until that changes, this PR will detect issues in the SB API
headers by including all the headers in the unittests (by including
LLDB/API.h) and building that with the warning, if the compiler supports
it.
rdar://143597614
Commit: 1ec1d25f691b92fb6aec8d0564139a5ba6c721b7
https://github.com/llvm/llvm-project/commit/1ec1d25f691b92fb6aec8d0564139a5ba6c721b7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/MachineOutliner.cpp
Log Message:
-----------
[MachineOutliner] Add skipModule call for opt-bisect-limit. (#128836)
Commit: 1d583ed2fb76c3d944ffab012c21b8fc0a93cac1
https://github.com/llvm/llvm-project/commit/1d583ed2fb76c3d944ffab012c21b8fc0a93cac1
Author: Peng Liu <winner245 at hotmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/ranges.fill.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/ranges.fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find/find.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find/ranges.find.pass.cpp
Log Message:
-----------
[libc++][test] Augment ranges::{fill, fill_n, find} with missing tests (#121209)
libc++ currently has very limited test coverage for `std::ranges{fill, fill_n, find}`
with `vector<bool>::iterator` optimizations. Specifically, the existing tests for
`std::ranges::fill` only covers cases of 1 - 2 bytes, which is merely 1/8 to 1/4
of the `__storage_type` word size. This renders the tests insufficient to validate
functionality for whole words, with or without partial words (which necessitates at
least 8 bytes of data). Moreover, no tests were provided for `ranges::{find, fill_n}`
with `vector<bool>::iterator` optimizations. This PR fills in the gap.
Commit: 14da7d5c1fc64006f731d7715a523d59a9e501e2
https://github.com/llvm/llvm-project/commit/14da7d5c1fc64006f731d7715a523d59a9e501e2
Author: Chris B <chris.bieneman at me.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/test/Driver/hip-gz-options.hip
Log Message:
-----------
Match .exe on Windows (#128894)
If you have zlib (not standard) on Windows, this test runs, and it was
missing a match for the file extension on lld.
Commit: 6c2e170d043d3a7d7b32635e887cfd255ef5c2ce
https://github.com/llvm/llvm-project/commit/6c2e170d043d3a7d7b32635e887cfd255ef5c2ce
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M clang/lib/CodeGen/Targets/NVPTX.cpp
M clang/test/CodeGenCUDA/launch-bounds.cu
M clang/test/OpenMP/ompx_attributes_codegen.cpp
M clang/test/OpenMP/thread_limit_nvptx.c
M llvm/docs/NVPTXUsage.rst
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXCtorDtorLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/lib/Target/NVPTX/NVVMIntrRange.cpp
M llvm/test/Analysis/KernelInfo/launch-bounds/nvptx.ll
M llvm/test/CodeGen/NVPTX/annotations.ll
M llvm/test/CodeGen/NVPTX/bug26185-2.ll
M llvm/test/CodeGen/NVPTX/cluster-dim.ll
M llvm/test/CodeGen/NVPTX/intr-range.ll
M llvm/test/CodeGen/NVPTX/lower-ctor-dtor.ll
M llvm/test/CodeGen/NVPTX/maxclusterrank.ll
M llvm/test/CodeGen/NVPTX/upgrade-nvvm-annotations.ll
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
[NVPTX] Convert vector function nvvm.annotations to attributes (#127736)
Replace some more nvvm.annotations with function attributes,
auto-upgrading the annotations as needed. These new attributes will be
more idiomatic and compile-time efficient than the annotations.
- !"maxntid[xyz]" -> "nvvm.maxntid"
- !"reqntid[xyz]" -> "nvvm.reqntid"
- !"cluster_dim_[xyz]" -> "nvvm.cluster_dim"
Commit: ffc5d2b5d46f979b41cfc822efe8017d919f3d58
https://github.com/llvm/llvm-project/commit/ffc5d2b5d46f979b41cfc822efe8017d919f3d58
Author: Peng Liu <winner245 at hotmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M libcxx/test/std/algorithms/alg.modifying.operations/alg.swap/iter_swap.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.swap/ranges.swap_ranges.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.swap/swap_ranges.pass.cpp
M libcxx/test/std/utilities/utility/utility.swap/swap_array.pass.cpp
Log Message:
-----------
[libc++][test] Refactor tests for ranges::swap_range algorithms (#121138)
This PR refactors tests for `ranges::swap_range`, `std::{swap_range,
iter_swap, swap}` algorithms to eliminate redundant code.
Commit: 3bb5867cd34e67d536aa8d73820a3451d214f7b4
https://github.com/llvm/llvm-project/commit/3bb5867cd34e67d536aa8d73820a3451d214f7b4
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M .github/workflows/release-binaries.yml
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Profile/DataAggregator.cpp
M bolt/test/X86/bolt-address-translation-yaml.test
A bolt/test/X86/entry-point-fallthru.s
M bolt/test/binary-analysis/AArch64/gs-pacret-autiasp.s
M bolt/test/binary-analysis/AArch64/gs-pacret-multi-bb.s
M clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt
M clang-tools-extra/clang-tidy/bugprone/StandaloneEmptyCheck.cpp
M clang-tools-extra/clang-tidy/performance/UnnecessaryValueParamCheck.cpp
M clang-tools-extra/clangd/ModulesBuilder.cpp
M clang-tools-extra/clangd/ProjectModules.h
M clang-tools-extra/clangd/ScanningProjectModules.cpp
M clang-tools-extra/clangd/unittests/PrerequisiteModulesTest.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/performance/unnecessary-value-param.rst
M clang-tools-extra/test/clang-tidy/checkers/performance/unnecessary-value-param.cpp
M clang/Maintainers.rst
M clang/cmake/caches/Release.cmake
M clang/docs/ReleaseNotes.rst
M clang/docs/ThreadSafetyAnalysis.rst
M clang/docs/analyzer/checkers.rst
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/DeclID.h
M clang/include/clang/AST/FormatString.h
M clang/include/clang/Analysis/Analyses/ThreadSafety.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
A clang/include/clang/Basic/BuiltinTemplates.td
M clang/include/clang/Basic/Builtins.h
M clang/include/clang/Basic/BuiltinsSPIRV.td
M clang/include/clang/Basic/CMakeLists.txt
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/LangOptions.h
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
A clang/include/clang/CIR/Passes.h
M clang/include/clang/Sema/HeuristicResolver.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaHLSL.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/AttrImpl.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/CXXInheritance.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/FormatString.cpp
M clang/lib/Analysis/ThreadSafety.cpp
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/Targets/NVPTX.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/WebAssembly.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Headers/cpuid.h
M clang/lib/Headers/hlsl/hlsl_detail.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Lex/HeaderSearch.cpp
M clang/lib/Lex/PPMacroExpansion.cpp
M clang/lib/Parse/ParseHLSL.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/HeuristicResolver.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaObjC.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaSPIRV.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ModuleManager.cpp
M clang/lib/StaticAnalyzer/Checkers/MacOSKeychainAPIChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/UndefinedAssignmentChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLocalVarsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
M clang/test/AST/ByteCode/arrays.cpp
A clang/test/AST/ByteCode/libcxx/make_unique.cpp
A clang/test/AST/ByteCode/libcxx/pointer-subscript.cpp
M clang/test/AST/ByteCode/literals.cpp
M clang/test/AST/ByteCode/unions.cpp
A clang/test/AST/HLSL/default_cbuffer.hlsl
A clang/test/Analysis/Checkers/WebKit/objc-mock-types.h
A clang/test/Analysis/Checkers/WebKit/unretained-local-vars-arc.mm
A clang/test/Analysis/Checkers/WebKit/unretained-local-vars.mm
M clang/test/Analysis/Inputs/expected-plists/edges-new.mm.plist
M clang/test/Analysis/Inputs/expected-plists/plist-output.m.plist
M clang/test/Analysis/a_flaky_crash.cpp
M clang/test/Analysis/analysis-after-multiple-dtors.cpp
M clang/test/Analysis/array-init-loop.cpp
M clang/test/Analysis/array-punned-region.c
M clang/test/Analysis/builtin_overflow_notes.c
M clang/test/Analysis/call-invalidation.cpp
M clang/test/Analysis/ctor-array.cpp
M clang/test/Analysis/ctor.mm
M clang/test/Analysis/diagnostics/no-store-func-path-notes.m
M clang/test/Analysis/fread.c
M clang/test/Analysis/implicit-ctor-undef-value.cpp
M clang/test/Analysis/initialization.c
M clang/test/Analysis/initialization.cpp
M clang/test/Analysis/kmalloc-linux.c
M clang/test/Analysis/malloc-annotations.c
M clang/test/Analysis/malloc.c
M clang/test/Analysis/misc-ps.c
M clang/test/Analysis/operator-calls.cpp
M clang/test/Analysis/stack-addr-ps.cpp
M clang/test/Analysis/undef-buffers.c
M clang/test/Analysis/uninit-const.c
M clang/test/Analysis/uninit-const.cpp
M clang/test/Analysis/uninit-structured-binding-array.cpp
M clang/test/Analysis/uninit-structured-binding-struct.cpp
M clang/test/Analysis/uninit-structured-binding-tuple.cpp
M clang/test/Analysis/uninit-vals.m
M clang/test/Analysis/zero-size-non-pod-array.cpp
A clang/test/CIR/IR/func.cir
A clang/test/CIR/IR/global.cir
M clang/test/CIR/func-simple.cpp
M clang/test/CIR/global-var-simple.cpp
M clang/test/CMakeLists.txt
M clang/test/CXX/drs/cwg29xx.cpp
M clang/test/CodeGen/AArch64/sve-vector-bits-codegen.c
M clang/test/CodeGen/memtag-globals-asm.cpp
M clang/test/CodeGenCUDA/launch-bounds.cu
A clang/test/CodeGenCXX/builtins-eh-wasm.cpp
M clang/test/CodeGenCXX/merge-functions.cpp
A clang/test/CodeGenHLSL/BasicFeatures/ArrayReturn.hlsl
M clang/test/CodeGenHLSL/basic_types.hlsl
M clang/test/CodeGenHLSL/builtins/abs.hlsl
A clang/test/CodeGenHLSL/builtins/reflect.hlsl
A clang/test/CodeGenHLSL/cbuffer_align.hlsl
A clang/test/CodeGenHLSL/default_cbuffer.hlsl
A clang/test/CodeGenSPIRV/Builtins/reflect.c
M clang/test/Driver/fprofile-continuous.c
M clang/test/Driver/hip-gz-options.hip
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/wasm-toolchain.c
M clang/test/Headers/cpuid.c
M clang/test/Modules/explicit-build.cpp
M clang/test/OpenMP/ompx_attributes_codegen.cpp
M clang/test/OpenMP/thread_limit_nvptx.c
A clang/test/Sema/format-string-matches.c
M clang/test/Sema/format-strings.c
M clang/test/Sema/warn-thread-safety-analysis.c
M clang/test/SemaCXX/warn-thread-safety-analysis.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-array.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-function-attr.cpp
M clang/test/SemaHLSL/BuiltIns/and-errors.hlsl
A clang/test/SemaHLSL/BuiltIns/reflect-errors.hlsl
M clang/test/SemaHLSL/cb_error.hlsl
A clang/test/SemaSPIRV/BuiltIns/reflect-errors.c
M clang/test/SemaTemplate/concepts-lambda.cpp
M clang/test/SemaTemplate/deduction-guide.cpp
M clang/test/lit.cfg.py
M clang/tools/CMakeLists.txt
A clang/tools/cir-opt/CMakeLists.txt
A clang/tools/cir-opt/cir-opt.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/utils/TableGen/CMakeLists.txt
A clang/utils/TableGen/ClangBuiltinTemplatesEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
R clang/utils/creduce-clang-crash.py
A clang/utils/reduce-clang-crash.py
M clang/www/cxx_dr_status.html
M flang-rt/CMakeLists.txt
M flang/docs/Extensions.md
M flang/examples/FlangOmpReport/FlangOmpReportVisitor.cpp
M flang/include/flang/Optimizer/Builder/FIRBuilder.h
M flang/include/flang/Optimizer/Builder/Runtime/RTBuilder.h
M flang/include/flang/Optimizer/Dialect/FIRDialect.td
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
A flang/include/flang/Optimizer/Transforms/RuntimeFunctions.inc
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Runtime/freestanding-tools.h
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/IO.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
A flang/lib/Optimizer/Transforms/GenRuntimeCallsForTest.cpp
A flang/lib/Optimizer/Transforms/SetRuntimeCallAttributes.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/module/cudadevice.f90
M flang/test/Driver/mlir-pass-pipeline.f90
M flang/test/Fir/basic-program.fir
M flang/test/Lower/CUDA/cuda-device-proc.cuf
A flang/test/Lower/CUDA/cuda-kernel-alloca-block.cuf
M flang/test/Lower/CUDA/cuda-return01.cuf
M flang/test/Lower/CUDA/cuda-return02.cuf
M flang/test/Lower/Intrinsics/ieee_rint_int.f90
M flang/test/Lower/Intrinsics/ieee_rounding.f90
A flang/test/Lower/OpenMP/Todo/assume.f90
A flang/test/Lower/OpenMP/Todo/assumes.f90
M flang/test/Lower/OpenMP/host-eval.f90
M flang/test/Lower/array-temp.f90
A flang/test/Parser/OpenMP/assumption.f90
A flang/test/Transforms/set-runtime-call-attributes.fir
A flang/test/Transforms/verify-known-runtime-functions.fir
A flang/test/Utils/generate-checks-for-runtime-funcs.py
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCArchitectures.cmake
M libc/cmake/modules/LLVMLibCHeaderRules.cmake
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/stdlib.yaml
M libc/src/stdio/generic/fileno.cpp
M libc/src/stdlib/CMakeLists.txt
A libc/src/stdlib/a64l.cpp
A libc/src/stdlib/a64l.h
M libc/test/src/stdlib/CMakeLists.txt
A libc/test/src/stdlib/a64l_test.cpp
M libclc/CMakeLists.txt
M libclc/amdgcn/lib/SOURCES
R libclc/amdgcn/lib/math/ldexp.cl
M libclc/amdgcn/lib/workitem/get_global_size.cl
M libclc/clc/include/clc/float/definitions.h
A libclc/clc/include/clc/math/clc_ldexp.h
A libclc/clc/include/clc/math/clc_ldexp.inc
A libclc/clc/include/clc/math/clc_log.h
A libclc/clc/include/clc/math/clc_log10.h
A libclc/clc/include/clc/math/clc_log2.h
A libclc/clc/include/clc/math/clc_nan.h
A libclc/clc/include/clc/math/clc_nan.inc
A libclc/clc/include/clc/math/clc_round.h
A libclc/clc/lib/amdgcn/SOURCES
A libclc/clc/lib/amdgcn/math/clc_ldexp_override.cl
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/math/clc_ldexp.cl
A libclc/clc/lib/generic/math/clc_log.cl
A libclc/clc/lib/generic/math/clc_log10.cl
A libclc/clc/lib/generic/math/clc_log2.cl
A libclc/clc/lib/generic/math/clc_log_base.h
A libclc/clc/lib/generic/math/clc_nan.cl
A libclc/clc/lib/generic/math/clc_nan.inc
A libclc/clc/lib/generic/math/clc_round.cl
M libclc/clspv/lib/SOURCES
M libclc/generic/include/clc/math/log10.h
R libclc/generic/include/math/binary_intrin.inc
R libclc/generic/include/math/clc_ldexp.h
R libclc/generic/include/math/ternary_intrin.inc
M libclc/generic/lib/SOURCES
R libclc/generic/lib/math/clc_ldexp.cl
M libclc/generic/lib/math/ldexp.cl
M libclc/generic/lib/math/ldexp.inc
M libclc/generic/lib/math/log.cl
M libclc/generic/lib/math/log10.cl
M libclc/generic/lib/math/log2.cl
R libclc/generic/lib/math/log_base.h
M libclc/generic/lib/math/nan.cl
M libclc/generic/lib/math/nan.inc
M libclc/generic/lib/math/round.cl
M libclc/spirv/lib/SOURCES
M libcxx/include/bitset
M libcxx/include/future
M libcxx/test/libcxx/atomics/atomics.syn/compatible_with_stdatomic.compile.pass.cpp
M libcxx/test/libcxx/input.output/file.streams/fstreams/filebuf/traits_mismatch.verify.cpp
M libcxx/test/libcxx/input.output/file.streams/fstreams/traits_mismatch.verify.cpp
M libcxx/test/libcxx/input.output/iostream.format/input.streams/traits_mismatch.verify.cpp
M libcxx/test/libcxx/input.output/iostream.format/output.streams/traits_mismatch.verify.cpp
M libcxx/test/libcxx/input.output/string.streams/traits_mismatch.verify.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/ranges.fill.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/ranges.fill_n.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.swap/iter_swap.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.swap/ranges.swap_ranges.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.swap/swap_ranges.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find/find.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find/ranges.find.pass.cpp
M libcxx/test/std/containers/sequences/array/array.fill/fill.verify.cpp
M libcxx/test/std/containers/sequences/array/array.swap/swap.verify.cpp
M libcxx/test/std/containers/sequences/array/array.tuple/get.verify.cpp
M libcxx/test/std/containers/sequences/array/array.tuple/tuple_element.verify.cpp
M libcxx/test/std/re/re.iter/re.tokiter/re.tokiter.comp/equal.pass.cpp
M libcxx/test/std/strings/basic.string/char.bad.verify.cpp
A libcxx/test/std/thread/futures/futures.async/thread_create_failure.pass.cpp
M libcxx/test/std/utilities/template.bitset/bitset.members/flip_all.pass.cpp
M libcxx/test/std/utilities/template.bitset/bitset_test_cases.h
M libcxx/test/std/utilities/utility/utility.swap/swap_array.pass.cpp
A lldb/examples/python/fzf_history.py
M lldb/include/lldb/API/SBSaveCoreOptions.h
M lldb/include/lldb/Core/ModuleList.h
M lldb/include/lldb/Core/Telemetry.h
M lldb/include/lldb/Symbol/UnwindPlan.h
M lldb/include/lldb/Target/ABI.h
M lldb/include/lldb/Target/RegisterContextUnwind.h
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/source/API/SBFrame.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Core/Telemetry.cpp
M lldb/source/Plugins/ABI/AArch64/ABIMacOSX_arm64.cpp
M lldb/source/Plugins/ABI/AArch64/ABIMacOSX_arm64.h
M lldb/source/Plugins/ABI/AArch64/ABISysV_arm64.cpp
M lldb/source/Plugins/ABI/AArch64/ABISysV_arm64.h
M lldb/source/Plugins/ABI/ARC/ABISysV_arc.cpp
M lldb/source/Plugins/ABI/ARC/ABISysV_arc.h
M lldb/source/Plugins/ABI/ARM/ABIMacOSX_arm.cpp
M lldb/source/Plugins/ABI/ARM/ABIMacOSX_arm.h
M lldb/source/Plugins/ABI/ARM/ABISysV_arm.cpp
M lldb/source/Plugins/ABI/ARM/ABISysV_arm.h
M lldb/source/Plugins/ABI/Hexagon/ABISysV_hexagon.cpp
M lldb/source/Plugins/ABI/Hexagon/ABISysV_hexagon.h
M lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
M lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.h
M lldb/source/Plugins/ABI/MSP430/ABISysV_msp430.cpp
M lldb/source/Plugins/ABI/MSP430/ABISysV_msp430.h
M lldb/source/Plugins/ABI/Mips/ABISysV_mips.cpp
M lldb/source/Plugins/ABI/Mips/ABISysV_mips.h
M lldb/source/Plugins/ABI/Mips/ABISysV_mips64.cpp
M lldb/source/Plugins/ABI/Mips/ABISysV_mips64.h
M lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc.cpp
M lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc.h
M lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc64.cpp
M lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc64.h
M lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
M lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
M lldb/source/Plugins/ABI/SystemZ/ABISysV_s390x.cpp
M lldb/source/Plugins/ABI/SystemZ/ABISysV_s390x.h
M lldb/source/Plugins/ABI/X86/ABIMacOSX_i386.cpp
M lldb/source/Plugins/ABI/X86/ABIMacOSX_i386.h
M lldb/source/Plugins/ABI/X86/ABISysV_i386.cpp
M lldb/source/Plugins/ABI/X86/ABISysV_i386.h
M lldb/source/Plugins/ABI/X86/ABISysV_x86_64.cpp
M lldb/source/Plugins/ABI/X86/ABISysV_x86_64.h
M lldb/source/Plugins/ABI/X86/ABIWindows_x86_64.cpp
M lldb/source/Plugins/ABI/X86/ABIWindows_x86_64.h
M lldb/source/Plugins/SymbolFile/CTF/SymbolFileCTF.cpp
M lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
M lldb/source/Plugins/UnwindAssembly/x86/UnwindAssembly-x86.cpp
M lldb/source/Plugins/UnwindAssembly/x86/x86AssemblyInspectionEngine.cpp
M lldb/source/Symbol/FuncUnwinders.cpp
M lldb/source/Symbol/UnwindPlan.cpp
M lldb/source/Target/RegisterContextUnwind.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/Target/ThreadPlanStepRange.cpp
M lldb/test/API/commands/frame/diagnose/dereference-function-return/TestDiagnoseDereferenceFunctionReturn.py
M lldb/test/API/python_api/run_locker/TestRunLocker.py
M lldb/test/API/tools/lldb-dap/output/TestDAP_output.py
M lldb/test/API/tools/lldb-dap/server/TestDAP_server.py
A lldb/test/API/tools/lldb-dap/source/Makefile
A lldb/test/API/tools/lldb-dap/source/TestDAP_source.py
A lldb/test/API/tools/lldb-dap/source/main.c
M lldb/tools/lldb-dap/CMakeLists.txt
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/EventHelper.cpp
M lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/BreakpointLocationsHandler.cpp
A lldb/tools/lldb-dap/Handler/CompileUnitsRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/CompletionsHandler.cpp
M lldb/tools/lldb-dap/Handler/ConfigurationDoneRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/ContinueRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/DataBreakpointInfoRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/DisassembleRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/DisconnectRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/EvaluateRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/ExceptionInfoRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/InitializeRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/LaunchRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/LocationsRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/ModulesRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/PauseRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/ReadMemoryRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
A lldb/tools/lldb-dap/Handler/ResponseHandler.cpp
A lldb/tools/lldb-dap/Handler/ResponseHandler.h
M lldb/tools/lldb-dap/Handler/RestartRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/ScopesRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/SetBreakpointsRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/SetDataBreakpointsRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/SetExceptionBreakpointsRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/SetFunctionBreakpointsRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/SetInstructionBreakpointsRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/SetVariableRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/SourceRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/StackTraceRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/StepInRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/StepInTargetsRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/StepOutRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/TestGetTargetBreakpointsRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/ThreadsRequestHandler.cpp
A lldb/tools/lldb-dap/Handler/VariablesRequestHandler.cpp
M lldb/tools/lldb-dap/JSONUtils.cpp
M lldb/tools/lldb-dap/lldb-dap.cpp
M lldb/unittests/API/CMakeLists.txt
M lldb/unittests/API/SBCommandInterpreterTest.cpp
M lldb/unittests/Core/TelemetryTest.cpp
M lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
M lldb/unittests/UnwindAssembly/PPC64/TestPPC64InstEmulation.cpp
M lldb/unittests/UnwindAssembly/x86/Testx86AssemblyInspectionEngine.cpp
M llvm/docs/CodingStandards.rst
M llvm/docs/GettingInvolved.rst
M llvm/docs/LangRef.rst
M llvm/docs/NVPTXUsage.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm-c/DebugInfo.h
M llvm/include/llvm/ADT/APFloat.h
M llvm/include/llvm/Analysis/DXILResource.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/include/llvm/CodeGen/Passes.h
A llvm/include/llvm/CodeGen/RegAllocGreedyPass.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.h
A llvm/include/llvm/ExecutionEngine/Orc/GetDylibInterface.h
R llvm/include/llvm/ExecutionEngine/Orc/JITLinkLazyCallThroughManager.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/Metadata.def
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/ObjectYAML/WasmYAML.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Support/AlignOf.h
M llvm/include/llvm/TableGen/Record.h
M llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h
M llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
M llvm/lib/Analysis/CostModel.cpp
M llvm/lib/Analysis/DXILResource.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/GlobalISel/LegacyLegalizerInfo.cpp
M llvm/lib/CodeGen/MachineBasicBlock.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/MachineOutliner.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
M llvm/lib/CodeGen/RegAllocBase.cpp
M llvm/lib/CodeGen/RegAllocBase.h
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegAllocGreedy.h
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/VirtRegMap.cpp
M llvm/lib/CodeGen/WasmEHPrepare.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.cpp
M llvm/lib/DebugInfo/DWARF/DWARFContext.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
M llvm/lib/DebugInfo/LogicalView/Readers/LVCodeViewReader.cpp
M llvm/lib/DebugInfo/LogicalView/Readers/LVCodeViewVisitor.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.cpp
A llvm/lib/ExecutionEngine/Orc/GetDylibInterface.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/LLVMContextImpl.h
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/ObjectYAML/WasmEmitter.cpp
M llvm/lib/ObjectYAML/WasmYAML.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/lib/Support/Unix/Program.inc
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
M llvm/lib/Target/AMDGPU/R600InstrInfo.h
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/ARC/ARCInstrInfo.cpp
M llvm/lib/Target/ARC/ARCInstrInfo.h
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
M llvm/lib/Target/ARM/Thumb1InstrInfo.h
M llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
M llvm/lib/Target/ARM/Thumb2InstrInfo.h
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.h
M llvm/lib/Target/BPF/BPFInstrInfo.cpp
M llvm/lib/Target/BPF/BPFInstrInfo.h
M llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
M llvm/lib/Target/CSKY/CSKYInstrInfo.h
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DXILPrettyPrinter.cpp
M llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
M llvm/lib/Target/DirectX/DirectXInstrInfo.h
M llvm/lib/Target/DirectX/DirectXRegisterInfo.cpp
M llvm/lib/Target/DirectX/DirectXRegisterInfo.h
M llvm/lib/Target/DirectX/DirectXSubtarget.h
M llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
M llvm/lib/Target/Hexagon/HexagonCallingConv.td
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
M llvm/lib/Target/Lanai/LanaiInstrInfo.h
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/lib/Target/M68k/M68kInstrInfo.h
M llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
M llvm/lib/Target/MSP430/MSP430InstrInfo.h
M llvm/lib/Target/Mips/Mips16InstrInfo.cpp
M llvm/lib/Target/Mips/Mips16InstrInfo.h
M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
M llvm/lib/Target/Mips/MipsSEInstrInfo.h
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXCtorDtorLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/lib/Target/NVPTX/NVVMIntrRange.cpp
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVBaseInfo.h
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVMCInstLower.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/Sparc/SparcInstrInfo.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.h
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
M llvm/lib/Target/VE/VEInstrInfo.cpp
M llvm/lib/Target/VE/VEInstrInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/lib/Target/XCore/XCoreInstrInfo.cpp
M llvm/lib/Target/XCore/XCoreInstrInfo.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.h
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanCFG.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/WindowsManifest/WindowsManifestMerger.cpp
M llvm/runtimes/CMakeLists.txt
M llvm/test/Analysis/CostModel/AArch64/div.ll
M llvm/test/Analysis/CostModel/AArch64/div_cte.ll
M llvm/test/Analysis/CostModel/AArch64/fshl.ll
M llvm/test/Analysis/CostModel/AArch64/fshr.ll
M llvm/test/Analysis/CostModel/AArch64/rem.ll
M llvm/test/Analysis/CostModel/AArch64/shuffle-reverse.ll
A llvm/test/Analysis/CostModel/AArch64/sincos.ll
M llvm/test/Analysis/CostModel/AArch64/sve-div.ll
M llvm/test/Analysis/CostModel/AArch64/sve-rem.ll
M llvm/test/Analysis/CostModel/AMDGPU/frexp.ll
M llvm/test/Analysis/DXILResource/buffer-frombinding.ll
M llvm/test/Analysis/KernelInfo/launch-bounds/nvptx.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform.mir
A llvm/test/Bitcode/subrange_type.ll
R llvm/test/CodeGen/AArch64/aarch64-build-attributes-all.ll
R llvm/test/CodeGen/AArch64/aarch64-build-attributes-bti.ll
R llvm/test/CodeGen/AArch64/aarch64-build-attributes-gcs.ll
R llvm/test/CodeGen/AArch64/aarch64-build-attributes-pac.ll
R llvm/test/CodeGen/AArch64/aarch64-build-attributes-pauthabi.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll
M llvm/test/CodeGen/AArch64/aarch64-sve-and-combine-crash.ll
M llvm/test/CodeGen/AArch64/alloca-load-store-scalable-array.ll
M llvm/test/CodeGen/AArch64/alloca-load-store-scalable-struct.ll
M llvm/test/CodeGen/AArch64/bfis-in-loop.ll
A llvm/test/CodeGen/AArch64/build-attributes-all.ll
A llvm/test/CodeGen/AArch64/build-attributes-bti.ll
A llvm/test/CodeGen/AArch64/build-attributes-gcs.ll
A llvm/test/CodeGen/AArch64/build-attributes-pac.ll
A llvm/test/CodeGen/AArch64/build-attributes-pauthabi.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
M llvm/test/CodeGen/AArch64/dag-combine-insert-subvector.ll
A llvm/test/CodeGen/AArch64/expand-load-got-pseudo.mir
A llvm/test/CodeGen/AArch64/inline-asm-speculation.ll
M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/nontemporal-load.ll
M llvm/test/CodeGen/AArch64/pr49781.ll
M llvm/test/CodeGen/AArch64/select_cc.ll
M llvm/test/CodeGen/AArch64/selectopt-const.ll
M llvm/test/CodeGen/AArch64/sinksplat.ll
M llvm/test/CodeGen/AArch64/sme-framelower-use-bp.ll
M llvm/test/CodeGen/AArch64/sme-peephole-opts.ll
M llvm/test/CodeGen/AArch64/sme-pstate-sm-changing-call-disable-coalescing.ll
M llvm/test/CodeGen/AArch64/sme-streaming-interface.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-faminmax.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlall.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-rshl.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-sqdmulh.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-vdot.ll
M llvm/test/CodeGen/AArch64/spillfill-sve.ll
M llvm/test/CodeGen/AArch64/split-vector-insert.ll
M llvm/test/CodeGen/AArch64/stack-guard-sve.ll
M llvm/test/CodeGen/AArch64/stack-hazard.ll
M llvm/test/CodeGen/AArch64/sub-splat-sub.ll
M llvm/test/CodeGen/AArch64/sve-aliasing.ll
M llvm/test/CodeGen/AArch64/sve-alloca.ll
M llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
M llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
M llvm/test/CodeGen/AArch64/sve-dead-masked-store.ll
M llvm/test/CodeGen/AArch64/sve-extload-icmp.ll
M llvm/test/CodeGen/AArch64/sve-extract-element.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-addressing-modes.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-mask-opt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
M llvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll
M llvm/test/CodeGen/AArch64/sve-fp-reduce-fadda.ll
M llvm/test/CodeGen/AArch64/sve-fp.ll
M llvm/test/CodeGen/AArch64/sve-fpext-load.ll
M llvm/test/CodeGen/AArch64/sve-fptrunc-store.ll
M llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
M llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll
M llvm/test/CodeGen/AArch64/sve-gep.ll
M llvm/test/CodeGen/AArch64/sve-insert-element.ll
M llvm/test/CodeGen/AArch64/sve-insert-vector-to-predicate-load.ll
M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
M llvm/test/CodeGen/AArch64/sve-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-int-log.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-scaled-offset.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-unscaled-offset.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-mask-ldst-ext.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-scalar-to-vec.ll
M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-ld1r.ll
M llvm/test/CodeGen/AArch64/sve-llrint.ll
M llvm/test/CodeGen/AArch64/sve-load-store-strict-align.ll
M llvm/test/CodeGen/AArch64/sve-lrint.ll
M llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll
M llvm/test/CodeGen/AArch64/sve-lsrchain.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-32b-signed-scaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-32b-signed-unscaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-32b-unsigned-scaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-32b-unsigned-unscaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-64b-scaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-64b-unscaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-vec-plus-imm.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-vec-plus-reg.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-nonext.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter-legalize.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter.ll
M llvm/test/CodeGen/AArch64/sve-min-max-pred.ll
M llvm/test/CodeGen/AArch64/sve-nontemporal-masked-ldst.ll
M llvm/test/CodeGen/AArch64/sve-pr92779.ll
M llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
M llvm/test/CodeGen/AArch64/sve-reassocadd.ll
M llvm/test/CodeGen/AArch64/sve-redundant-store.ll
M llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
M llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll
M llvm/test/CodeGen/AArch64/sve-split-load.ll
M llvm/test/CodeGen/AArch64/sve-split-store.ll
M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-stack-frame-layout.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reshuffle.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
M llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll
M llvm/test/CodeGen/AArch64/sve-unary-movprfx.ll
M llvm/test/CodeGen/AArch64/sve-uunpklo-load-uzp1-store-combine.ll
M llvm/test/CodeGen/AArch64/sve-vector-compress.ll
M llvm/test/CodeGen/AArch64/sve-vector-splat.ll
M llvm/test/CodeGen/AArch64/sve-vl-arith.ll
M llvm/test/CodeGen/AArch64/sve-vselect-imm.ll
M llvm/test/CodeGen/AArch64/sve2-intrinsics-combine-rshrnb.ll
M llvm/test/CodeGen/AArch64/sve2-rsh.ll
M llvm/test/CodeGen/AArch64/sve2-unary-movprfx.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx4.ll
M llvm/test/CodeGen/AArch64/vector-insert-dag-combines.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
A llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers-assertion-after-ra-failure.ll
R llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers-assertion-after-ra-failure.xfail.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll
M llvm/test/CodeGen/AMDGPU/copysign-simplify-demanded-bits.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/early-if-convert.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fold-operands-s-add-copy-to-vgpr.mir
M llvm/test/CodeGen/AMDGPU/fold-readlane.mir
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir
M llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-literal.mir
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
M llvm/test/CodeGen/AMDGPU/issue48473.mir
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll
M llvm/test/CodeGen/AMDGPU/licm-valu.mir
M llvm/test/CodeGen/AMDGPU/licm-wwm.mir
M llvm/test/CodeGen/AMDGPU/live-interval-bug-in-rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.append.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.consume.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.m0.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.ttracedata.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umax.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umin.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
M llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
A llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
A llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
M llvm/test/CodeGen/AMDGPU/remat-sop.mir
M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/shl64_reduce.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies-copy-to-sgpr.mir
A llvm/test/CodeGen/AMDGPU/si-fold-operands-commute-same-operands-assert.mir
A llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
M llvm/test/CodeGen/AMDGPU/wqm.mir
M llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
M llvm/test/CodeGen/ARM/select-imm.ll
M llvm/test/CodeGen/DirectX/CreateHandleFromBinding.ll
A llvm/test/CodeGen/DirectX/Metadata/cbuffer-only.ll
M llvm/test/CodeGen/DirectX/clamp.ll
M llvm/test/CodeGen/DirectX/discard.ll
A llvm/test/CodeGen/DirectX/unsupported_intrinsic.ll
A llvm/test/CodeGen/Hexagon/bittracker-regclass.ll
A llvm/test/CodeGen/Hexagon/calloperand-v128i1.ll
A llvm/test/CodeGen/Hexagon/calloperand-v16i1.ll
A llvm/test/CodeGen/Hexagon/calloperand-v32i1.ll
A llvm/test/CodeGen/Hexagon/calloperand-v4i1.ll
A llvm/test/CodeGen/Hexagon/calloperand-v64i1.ll
A llvm/test/CodeGen/Hexagon/calloperand-v8i1.ll
A llvm/test/CodeGen/LoongArch/lsx/vec-sext.ll
A llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll
M llvm/test/CodeGen/MSP430/shift-amount-threshold.ll
M llvm/test/CodeGen/NVPTX/annotations.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/atomics.ll
M llvm/test/CodeGen/NVPTX/bug26185-2.ll
M llvm/test/CodeGen/NVPTX/cluster-dim.ll
A llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
A llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
A llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
A llvm/test/CodeGen/NVPTX/cmpxchg.py
M llvm/test/CodeGen/NVPTX/intr-range.ll
M llvm/test/CodeGen/NVPTX/ldu-ldg.ll
M llvm/test/CodeGen/NVPTX/lit.local.cfg
M llvm/test/CodeGen/NVPTX/lower-ctor-dtor.ll
M llvm/test/CodeGen/NVPTX/maxclusterrank.ll
M llvm/test/CodeGen/NVPTX/upgrade-nvvm-annotations.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
A llvm/test/CodeGen/PowerPC/llvm.sincos.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/or-is-add.ll
M llvm/test/CodeGen/RISCV/rvv/expandload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
A llvm/test/CodeGen/RISCV/rvv/vmv0-elimination.mir
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
M llvm/test/CodeGen/RISCV/select-const.ll
M llvm/test/CodeGen/RISCV/select.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reflect.ll
A llvm/test/CodeGen/SPIRV/opencl/reflect-error.ll
M llvm/test/CodeGen/SPIRV/read_image.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpImageReadMS.ll
M llvm/test/CodeGen/Thumb/branchless-cmp.ll
A llvm/test/CodeGen/Thumb2/peephole-opt-check-reg-sequence-compose-supports-subreg-index.ll
M llvm/test/CodeGen/WebAssembly/exception.ll
M llvm/test/CodeGen/WebAssembly/half-precision.ll
A llvm/test/CodeGen/X86/andnot-blsmsk.ll
M llvm/test/CodeGen/X86/avx2-arith.ll
M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/X86/fp128-libcalls.ll
M llvm/test/CodeGen/X86/fp16-libcalls.ll
M llvm/test/CodeGen/X86/inline-asm-assertion.ll
M llvm/test/CodeGen/X86/llvm.acos.ll
M llvm/test/CodeGen/X86/llvm.asin.ll
M llvm/test/CodeGen/X86/llvm.atan.ll
M llvm/test/CodeGen/X86/llvm.atan2.ll
A llvm/test/CodeGen/X86/llvm.cos.ll
M llvm/test/CodeGen/X86/llvm.cosh.ll
A llvm/test/CodeGen/X86/llvm.sin.ll
M llvm/test/CodeGen/X86/llvm.sinh.ll
M llvm/test/CodeGen/X86/llvm.tan.ll
M llvm/test/CodeGen/X86/llvm.tanh.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
M llvm/test/CodeGen/X86/x86-win64-shrink-wrapping.ll
A llvm/test/ExecutionEngine/JITLink/AArch64/Inputs/MachO_Foo.tbd
A llvm/test/ExecutionEngine/JITLink/AArch64/Inputs/MachO_main_ret_foo.s
A llvm/test/ExecutionEngine/JITLink/AArch64/MachO_weak_link.test
M llvm/test/LTO/X86/coro.ll
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-all.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-bti.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-err-attrs.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-err-headers.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-gcs.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-none.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-numerical-tags.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-out-of-order.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-pac.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-private-subsections-err.s
R llvm/test/MC/AArch64/aarch64-build-attributes-asm-private-subsections.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-aeabi-known.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-bti.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-err-attrs.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-err-headers.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-gcs.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-mixed.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-none.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-numerical-tags.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-out-of-order.s
A llvm/test/MC/AArch64/build-attributes-asm-aeabi-pac.s
A llvm/test/MC/AArch64/build-attributes-asm-non_aeabi-err.s
A llvm/test/MC/AArch64/build-attributes-asm-non_aeabi.s
A llvm/test/MC/Disassembler/RISCV/xqci-invalid.txt
A llvm/test/MC/PowerPC/case-insensitive-regs.s
M llvm/test/MC/RISCV/xqcia-invalid.s
M llvm/test/MC/RISCV/xqcia-valid.s
A llvm/test/MC/RISCV/xqcilia-invalid.s
A llvm/test/MC/RISCV/xqcilia-valid.s
M llvm/test/MC/RISCV/xrivosvizip-invalid.s
M llvm/test/MC/RISCV/xrivosvizip-valid.s
M llvm/test/ObjectYAML/wasm/dylink_section.yaml
M llvm/test/Other/new-pm-defaults.ll
M llvm/test/Other/new-pm-lto-defaults.ll
M llvm/test/Transforms/ConstraintElimination/analysis-invalidation.ll
A llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll
R llvm/test/Transforms/InstCombine/AArch64/sve-inst-combine-cmpne.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-abs-srshl.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-all-active-lanes-cvt.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-fmul-idempotency.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-fmul_u-idempotency.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul-idempotency.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul_u-idempotency.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-cmpne.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
A llvm/test/Transforms/InstCombine/AMDGPU/bitcast-fold-lane-ops.ll
M llvm/test/Transforms/InstCombine/AMDGPU/permlane64.ll
M llvm/test/Transforms/InstCombine/load.ll
M llvm/test/Transforms/InstCombine/onehot_merge.ll
M llvm/test/Transforms/InstCombine/scalable-const-fp-splat.ll
M llvm/test/Transforms/InstCombine/scalable-select.ll
M llvm/test/Transforms/InstCombine/select-masked_gather.ll
M llvm/test/Transforms/InstCombine/udiv-pow2-vscale.ll
M llvm/test/Transforms/InstCombine/vector_gep1.ll
M llvm/test/Transforms/InstSimplify/ConstProp/extractelement-vscale.ll
M llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/divs-with-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-step.ll
M llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/pr54634.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-predication.ll
M llvm/test/Transforms/LoopVectorize/create-induction-resume.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/LoopVectorize/induction-step.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization-2.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/no_outside_user.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_hcfg_construction.ll
M llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/scalable-iv-outside-user.ll
M llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
M llvm/test/Transforms/MemCpyOpt/stack-move.ll
M llvm/test/Transforms/MergeFunc/comdat.ll
A llvm/test/Transforms/MergeFunc/linkonce.ll
M llvm/test/Transforms/MergeFunc/linkonce_odr.ll
M llvm/test/Transforms/MergeFunc/merge-linkonce-odr-used.ll
M llvm/test/Transforms/MergeFunc/merge-linkonce-odr-weak-odr-mixed-used.ll
M llvm/test/Transforms/MergeFunc/merge-linkonce-odr.ll
M llvm/test/Transforms/MergeFunc/merge-weak-odr-used.ll
M llvm/test/Transforms/MergeFunc/merge-weak-odr.ll
A llvm/test/Transforms/MergeFunc/metadata-call-arguments.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/math-function.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/spillcost.ll
A llvm/test/Transforms/SLPVectorizer/SystemZ/revec-fix-128169.ll
A llvm/test/Transforms/SimplifyCFG/X86/fake-use-considered-when-sinking.ll
M llvm/test/Verifier/invoke.ll
M llvm/test/tools/llvm-rc/windres-preproc.test
M llvm/test/tools/llvm-symbolizer/skip-line-zero.s
M llvm/test/tools/llvm-symbolizer/sym-verbose.test
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/tools/llvm-size/llvm-size.cpp
M llvm/tools/obj2yaml/wasm2yaml.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M llvm/unittests/IR/MetadataTest.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/utils/gn/secondary/bolt/lib/Passes/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/lldb/tools/lldb-dap/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
M llvm/utils/mlgo-utils/mlgo/corpus/combine_training_corpus.py
M llvm/utils/mlgo-utils/mlgo/corpus/extract_ir.py
A llvm/utils/mlgo-utils/mlgo/corpus/flags.py
M mlir/cmake/modules/CMakeLists.txt
M mlir/include/mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h
M mlir/include/mlir/Dialect/Affine/Analysis/LoopAnalysis.h
M mlir/include/mlir/Dialect/GPU/TransformOps/GPUTransformOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
M mlir/include/mlir/Dialect/Linalg/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.h
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgRelayoutOps.td
A mlir/include/mlir/Dialect/Linalg/IR/RelayoutOpInterface.h
A mlir/include/mlir/Dialect/Linalg/IR/RelayoutOpInterface.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrDialect.td
M mlir/include/mlir/Dialect/SCF/Transforms/Transforms.h
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVImageOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaProfileCompliance.h
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/include/mlir/IR/OperationSupport.h
M mlir/include/mlir/Interfaces/DataLayoutInterfaces.td
M mlir/include/mlir/Interfaces/LoopLikeInterface.td
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Bindings/Python/NanobindUtils.h
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h
M mlir/lib/Conversion/GPUCommon/IndexIntrinsicsOpLowering.h
M mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/GPUToNVVM/WmmaOpsToNvvm.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
M mlir/lib/Dialect/Affine/Analysis/LoopAnalysis.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OneShotModuleBufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/TensorCopyInsertion.cpp
M mlir/lib/Dialect/GPU/TransformOps/GPUTransformOps.cpp
M mlir/lib/Dialect/Math/Transforms/ExpandPatterns.cpp
M mlir/lib/Dialect/SPIRV/IR/CMakeLists.txt
A mlir/lib/Dialect/SPIRV/IR/ImageOps.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeTransposeConv.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaFolders.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaReduceTransposes.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/lib/Dialect/Tosa/Utils/ConversionUtils.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.h
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm-32b.mlir
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Dialect/Affine/loop-fusion-4.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir
M mlir/test/Dialect/Bufferization/Transforms/transform-ops.mlir
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
M mlir/test/Dialect/Math/expand-math.mlir
M mlir/test/Dialect/MemRef/resolve-dim-ops.mlir
M mlir/test/Dialect/SPIRV/IR/image-ops.mlir
M mlir/test/Dialect/Tosa/availability.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/constant-op-fold.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/profile_all_unsupported.mlir
M mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
M mlir/test/Dialect/Tosa/profile_pro_int_unsupported.mlir
M mlir/test/Dialect/Tosa/quant-test.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-transpose-conv.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/tosa-reduce-transposes.mlir
M mlir/test/Dialect/Tosa/transpose-fold.mlir
M mlir/test/Dialect/Vector/linearize.mlir
M mlir/test/Dialect/Vector/scalar-vector-transfer-to-memref.mlir
M mlir/test/Dialect/Vector/vector-gather-lowering.mlir
M mlir/test/Dialect/Vector/vector-rewrite-narrow-types.mlir
A mlir/test/Dialect/Vector/vector-rewrite-subbyte-ext-and-trunci.mlir
M mlir/test/Dialect/Vector/vector-transfer-permutation-lowering.mlir
M mlir/test/Dialect/Vector/vector-unroll-options.mlir
R mlir/test/Dialect/XeGPU/XeGPUOps.mlir
M mlir/test/Dialect/XeGPU/invalid.mlir
A mlir/test/Dialect/XeGPU/ops.mlir
M mlir/test/Examples/mlir-opt/loop_fusion_options.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
A mlir/test/Target/LLVMIR/openmp-target-spmd.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
M mlir/test/Target/SPIRV/image-ops.mlir
M mlir/test/Target/SPIRV/selection.mlir
A mlir/test/Target/SPIRV/selection.spv
M mlir/test/lib/Dialect/Test/TestTypeDefs.td
M mlir/test/lit.cfg.py
M mlir/test/python/ir/operation.py
M offload/plugins-nextgen/host/CMakeLists.txt
M offload/test/sanitizer/kernel_crash_many.c
M offload/test/sanitizer/kernel_trap.c
M offload/test/sanitizer/kernel_trap.cpp
M offload/test/sanitizer/kernel_trap_many.c
M openmp/tools/archer/ompt-tsan.cpp
M utils/bazel/llvm-project-overlay/clang-tools-extra/clang-tidy/BUILD.bazel
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/Target/BUILD.bazel
Log Message:
-----------
Fix formatting
Created using spr 1.3.5
Compare: https://github.com/llvm/llvm-project/compare/57a6b0526cbc...3bb5867cd34e
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