[all-commits] [llvm/llvm-project] 15fbdc: [AArch64][SVE] Lower unpredicated loads/stores as ...

[Ricardo Jesus via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 15fbdc2b9635b75f431a26b89b48fe03e7ed9d5c
      https://github.com/llvm/llvm-project/commit/15fbdc2b9635b75f431a26b89b48fe03e7ed9d5c
  Author: Ricardo Jesus <rjj at nvidia.com>
  Date:   2025-02-26 (Wed, 26 Feb 2025)

  Changed paths:
    M clang/test/CodeGen/AArch64/sve-vector-bits-codegen.c
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/alloca-load-store-scalable-array.ll
    M llvm/test/CodeGen/AArch64/alloca-load-store-scalable-struct.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
    M llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
    M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
    M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
    M llvm/test/CodeGen/AArch64/nontemporal-load.ll
    M llvm/test/CodeGen/AArch64/sinksplat.ll
    M llvm/test/CodeGen/AArch64/sme-framelower-use-bp.ll
    M llvm/test/CodeGen/AArch64/sme-peephole-opts.ll
    M llvm/test/CodeGen/AArch64/sme-pstate-sm-changing-call-disable-coalescing.ll
    M llvm/test/CodeGen/AArch64/sme-streaming-interface.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-faminmax.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlall.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-rshl.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-sqdmulh.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-vdot.ll
    M llvm/test/CodeGen/AArch64/spillfill-sve.ll
    M llvm/test/CodeGen/AArch64/split-vector-insert.ll
    M llvm/test/CodeGen/AArch64/stack-guard-sve.ll
    M llvm/test/CodeGen/AArch64/stack-hazard.ll
    M llvm/test/CodeGen/AArch64/sve-aliasing.ll
    M llvm/test/CodeGen/AArch64/sve-alloca.ll
    M llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
    M llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
    M llvm/test/CodeGen/AArch64/sve-dead-masked-store.ll
    M llvm/test/CodeGen/AArch64/sve-extload-icmp.ll
    M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
    M llvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll
    M llvm/test/CodeGen/AArch64/sve-fp-reduce-fadda.ll
    M llvm/test/CodeGen/AArch64/sve-fp.ll
    M llvm/test/CodeGen/AArch64/sve-fpext-load.ll
    M llvm/test/CodeGen/AArch64/sve-fptrunc-store.ll
    M llvm/test/CodeGen/AArch64/sve-insert-element.ll
    M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
    M llvm/test/CodeGen/AArch64/sve-int-arith.ll
    M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-ld1r.ll
    M llvm/test/CodeGen/AArch64/sve-llrint.ll
    M llvm/test/CodeGen/AArch64/sve-load-store-strict-align.ll
    M llvm/test/CodeGen/AArch64/sve-lrint.ll
    M llvm/test/CodeGen/AArch64/sve-lsrchain.ll
    M llvm/test/CodeGen/AArch64/sve-masked-scatter-legalize.ll
    M llvm/test/CodeGen/AArch64/sve-min-max-pred.ll
    M llvm/test/CodeGen/AArch64/sve-pr92779.ll
    M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
    M llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
    M llvm/test/CodeGen/AArch64/sve-reassocadd.ll
    M llvm/test/CodeGen/AArch64/sve-redundant-store.ll
    M llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
    M llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll
    M llvm/test/CodeGen/AArch64/sve-split-load.ll
    M llvm/test/CodeGen/AArch64/sve-split-store.ll
    M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-stack-frame-layout.ll
    M llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll
    M llvm/test/CodeGen/AArch64/sve-vector-compress.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-combine-rshrnb.ll
    M llvm/test/CodeGen/AArch64/sve2-rsh.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx4.ll
    M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
    M llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll

  Log Message:
  -----------
  [AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (#127837)

Currently, given:
```cpp
svuint8_t foo(uint8_t *x) {
  return svld1(svptrue_b8(), x);
}
```
We generate:
```gas
foo:
  ptrue   p0.b
  ld1b    { z0.b }, p0/z, [x0]
  ret
```
However, on little-endian and with unaligned memory accesses allowed, we
could instead be using LDR as follows:
```gas
foo:
  ldr     z0, [x0]
  ret
```

The second form avoids the predicate dependency.
Likewise for other types and stores.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications