[all-commits] [llvm/llvm-project] 0f0d3f: [AMDGPU] Do not allow M0 as v_readlane_b32 dst (#1...

[Pierre van Houtryve via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0f0d3fb6b59b27628a05f2da536b0294c99d61bc
      https://github.com/llvm/llvm-project/commit/0f0d3fb6b59b27628a05f2da536b0294c99d61bc
  Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
  Date:   2025-02-26 (Wed, 26 Feb 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/VOP2Instructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
    M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umax.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umin.mir
    M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
    M llvm/test/CodeGen/AMDGPU/wqm.mir

  Log Message:
  -----------
  [AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)

See #128851 - this is the same patch, but for v_readlane_b32.

This instruction is used much less often so there were less changes
required.



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