[all-commits] [llvm/llvm-project] fc655b: [DirectX] Fix printing of DXIL cbuffer info (#128698)
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Tue Feb 25 20:03:27 PST 2025
Branch: refs/heads/users/vitalybuka/spr/ubsan-remove-fsanitizervptr-from-fsanitizerundefined
Home: https://github.com/llvm/llvm-project
Commit: fc655b1ae78305ad0839c0311f72607775af0c73
https://github.com/llvm/llvm-project/commit/fc655b1ae78305ad0839c0311f72607775af0c73
Author: Justin Bogner <mail at justinbogner.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
Log Message:
-----------
[DirectX] Fix printing of DXIL cbuffer info (#128698)
Make sure we're able to print cbuffer comments in a way that's
compatible with DXC.
Fixes #128562
Commit: 1b39328d7440aa7a94af4083257ef1c2f9394887
https://github.com/llvm/llvm-project/commit/1b39328d7440aa7a94af4083257ef1c2f9394887
Author: Eli Friedman <efriedma at quicinc.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/MachineInstr.cpp
A llvm/test/CodeGen/AArch64/inline-asm-speculation.ll
M llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll
M llvm/test/CodeGen/AMDGPU/early-if-convert.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
M llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
M llvm/test/CodeGen/X86/x86-win64-shrink-wrapping.ll
Log Message:
-----------
[CodeGen] Fix MachineInstr::isSafeToMove handling of inline asm. (#126807)
Even if an inline asm doesn't have memory effects, we can't assume it's
safe to speculate: it could trap, or cause undefined behavior. At the
LLVM IR level, this is handled correctly: we don't speculate inline asm
(unless it's marked "speculatable", but I don't think anyone does that).
Codegen also needs to respect this restriction.
This change stops Early If Conversion and similar passes from
speculating an INLINEASM MachineInstr.
Some uses of isSafeToMove probably could be switched to a different API:
isSafeToMove assumes you're hoisting, but we could handle some forms of
sinking more aggressively. But I'll leave that for a followup, if it
turns out to be relevant.
See also discussion on gcc bugtracker
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102150 .
Commit: b7060d0183f8f23e4e1a8ce6222fa8fa51b26fbd
https://github.com/llvm/llvm-project/commit/b7060d0183f8f23e4e1a8ce6222fa8fa51b26fbd
Author: Justin Bogner <mail at justinbogner.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILPrettyPrinter.cpp
M llvm/test/CodeGen/DirectX/CreateHandleFromBinding.ll
Log Message:
-----------
[DirectX] Fix printing of DXIL cbuffer info (#128698)
Make sure we're able to print cbuffer comments in a way that's
compatible with DXC.
Fixes #128562
Note: This is a re-commit because I somehow managed to get a completely
empty commit the first time.
Commit: 09832777d830e0fddff84bf36793ec4e453656b0
https://github.com/llvm/llvm-project/commit/09832777d830e0fddff84bf36793ec4e453656b0
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/cmake/caches/Release.cmake
Log Message:
-----------
[CMake][Release] Statically link ZSTD on all OSes (#128554)
This will make the binaries more portable.
Commit: cd4c30bb224e432d8cd37f375c138cbaada14f6c
https://github.com/llvm/llvm-project/commit/cd4c30bb224e432d8cd37f375c138cbaada14f6c
Author: Ashley Coleman <ascoleman at microsoft.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/CodeGenHLSL/cbuffer_align.hlsl
Log Message:
-----------
[HLSL][Sema] Fix Struct Size Calculation containing 16/32 bit scalars (#128086)
Fixes #119641
Update SemaHLSL to correctly calculate the alignment barrier for scalars
that are not 4 bytes wide
Commit: 2db8386867c5083980ff00bf2eae8937457ab9da
https://github.com/llvm/llvm-project/commit/2db8386867c5083980ff00bf2eae8937457ab9da
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/include/clang/AST/Decl.h
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/AST/Decl.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/AST/HLSL/default_cbuffer.hlsl
M clang/test/CodeGenHLSL/basic_types.hlsl
A clang/test/CodeGenHLSL/default_cbuffer.hlsl
Log Message:
-----------
[HLSL] Implement default constant buffer $Globals (2nd attempt) (#128589)
All variable declarations in the global scope that are not resources,
static or empty are implicitly added to implicit constant buffer
`$Globals`. They are created in `hlsl_constant` address space and
collected in an implicit `HLSLBufferDecl` node that is added to the AST
at the end of the translation unit. Codegen is the same as for explicit
constant buffers.
Fixes #123801
This is a second attempt to implement this feature. The first attempt
had to be reverted because of memory leaks. The problem was adding a
`SmallVector` member on `HLSLBufferDecl` node to represent a list of
default buffer declarations. When this vector needed to grow, it
allocated memory that was never released, because all memory used by AST
nodes must be allocated by `ASTContext` allocator and is released all at
once. Destructors on AST nodes are never called.
It this change the list of default buffer declarations is collected in a
`SmallVector` instance on `SemaHLSL`. The `HLSLBufDecl` representing
`$Globals` is created at the end of the translation unit when the number
of declarations is known, and the list is copied into an array allocated
by the `ASTContext` allocator.
Commit: c8b40867d144395ad3c306a3cf87f970e0f97f07
https://github.com/llvm/llvm-project/commit/c8b40867d144395ad3c306a3cf87f970e0f97f07
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
Log Message:
-----------
[AMDGPU][True16][CodeGen] test fix for uaddsat/usubsat true16 selection (#128784)
This is a NFC change. Update the test file and fix the build
https://github.com/llvm/llvm-project/pull/128233 is causing a build
issue. This is caused by PR
https://github.com/llvm/llvm-project/pull/127945 being merged while the
128233 is pending for review.
Commit: f3000d7d27fab1d1bbf1d848c6f84d3f91931326
https://github.com/llvm/llvm-project/commit/f3000d7d27fab1d1bbf1d848c6f84d3f91931326
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M flang/lib/Lower/ConvertVariable.cpp
M flang/test/Lower/CUDA/cuda-return01.cuf
M flang/test/Lower/CUDA/cuda-return02.cuf
Log Message:
-----------
[flang][cuda] Do not trigger automatic deallocation in main (#128789)
Similar to host flow, do not trigger automatic deallocation at then end
of the main program since anything could happen like a
cudaDevcieReset().
Commit: e350485595d0694dbf5847d8d0eff1fb3df56e3b
https://github.com/llvm/llvm-project/commit/e350485595d0694dbf5847d8d0eff1fb3df56e3b
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
A flang/test/Lower/CUDA/cuda-kernel-alloca-block.cuf
Log Message:
-----------
[flang][cuda] Set alloca block in cuf kernel (#128776)
Temporary created during lowering in a cuf kernel must be set in the cuf
kernel itself otherwise they will be allocated on the host.
Commit: b1a735b45dcc194ad9be08d057bc853ad1c1467b
https://github.com/llvm/llvm-project/commit/b1a735b45dcc194ad9be08d057bc853ad1c1467b
Author: Kai Sasaki <lewuathe at gmail.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Math/Transforms/ExpandPatterns.cpp
M mlir/test/Dialect/Math/expand-math.mlir
Log Message:
-----------
[mlir][math] expand-math pass assumes the static shaped type (#128299)
In the process of `expand-math` pass, the conversion of ceil op assumes
the static shaped type as input as it needs create 0 and 1 constant
values whose type is aligned with the op type.
Fixes https://github.com/llvm/llvm-project/issues/128275
Commit: da37c76ac621c64216e56ead3efe1bd569250ee2
https://github.com/llvm/llvm-project/commit/da37c76ac621c64216e56ead3efe1bd569250ee2
Author: Prakhar Dixit <75660779+Prakhar-Dixit at users.noreply.github.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/test/Dialect/Vector/vector-unroll-options.mlir
Log Message:
-----------
[mlir][vector] Add a check to ensure input vector rank equals target shape rank (#127706)
Fixes issue #126197
The crash is caused because, during IR transformation, the
vector-unrolling pass (using ExtractStridedSliceOp) attempts to slice an
input vector of higher rank using a target vector of lower rank, which
is not supported.
Specific example :
```
module {
func.func @func1() {
%cst_25 = arith.constant dense<3.718400e+04> : vector<4x2x2xf16>
%cst_26 = arith.constant dense<1.000000e+00> : vector<24x2x2xf32>
%47 = vector.fma %cst_26, %cst_26, %cst_26 : vector<24x2x2xf32>
%818 = scf.execute_region -> vector<24x2x2xf32> {
scf.yield %47 : vector<24x2x2xf32>
}
%823 = vector.extract_strided_slice %cst_25 {offsets = [2], sizes = [1], strides = [1]} : vector<4x2x2xf16> to vector<1x2x2xf16>
return
}
}
```
---------
Co-authored-by: Kai Sasaki <lewuathe at gmail.com>
Commit: 439de05848b22e76d4fb377ef28587b3eba2a4c5
https://github.com/llvm/llvm-project/commit/439de05848b22e76d4fb377ef28587b3eba2a4c5
Author: Jim Lin <jim at andestech.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
Log Message:
-----------
[RISCV] Rename function name to start with prefix vpreduce for consistency. (NFC)
Commit: a565f9eb2997ab1614cad326b93ab21810e39f32
https://github.com/llvm/llvm-project/commit/a565f9eb2997ab1614cad326b93ab21810e39f32
Author: Jim Lin <jim at andestech.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
Log Message:
-----------
[RISCV] The test for vp.reduce.fminimum/fmaximum with fixed-length should stay in fixed-vectors-reduction-fp-vp.ll. (NFC)
Commit: 01cc1d13cd0c54bd4c29185b052fa5c16285dca7
https://github.com/llvm/llvm-project/commit/01cc1d13cd0c54bd4c29185b052fa5c16285dca7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
Log Message:
-----------
[RISCV] Use Priv tablegen class for sf.cease instruction.
The encoding for sf.cease is only one bit different than wfi which
I believe was an intentional choice. wfi uses the Priv class so
this makes them consistent.
Commit: c53eb93dd7e93988b8456d317e3ebffa0c809fb9
https://github.com/llvm/llvm-project/commit/c53eb93dd7e93988b8456d317e3ebffa0c809fb9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
A llvm/test/CodeGen/Thumb2/peephole-opt-check-reg-sequence-compose-supports-subreg-index.ll
Log Message:
-----------
PeepholeOpt: Immediately check if a reg_sequence compose supports a subregister (#128279)
This is a quick fix for EXPENSIVE_CHECKS bot failures. I still think we
could
defer looking for a compatible subregister further up the use-def chain,
and
should be able to check compatibilty with the ultimate found source.
Commit: 8fc8a84e23471fe56214e68706addc712b5a2949
https://github.com/llvm/llvm-project/commit/8fc8a84e23471fe56214e68706addc712b5a2949
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Allow breaking before kw___attribute (#128623)
Fixes #74784
Commit: 4d1c3abee5e3b6d4174ccc6911840e567574e76e
https://github.com/llvm/llvm-project/commit/4d1c3abee5e3b6d4174ccc6911840e567574e76e
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M clang/cmake/caches/Release.cmake
M clang/include/clang/AST/Decl.h
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/AST/Decl.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/AST/HLSL/default_cbuffer.hlsl
M clang/test/CodeGenHLSL/basic_types.hlsl
A clang/test/CodeGenHLSL/cbuffer_align.hlsl
A clang/test/CodeGenHLSL/default_cbuffer.hlsl
M clang/unittests/Format/FormatTest.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
A flang/test/Lower/CUDA/cuda-kernel-alloca-block.cuf
M flang/test/Lower/CUDA/cuda-return01.cuf
M flang/test/Lower/CUDA/cuda-return02.cuf
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
M llvm/lib/Target/DirectX/DXILPrettyPrinter.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
A llvm/test/CodeGen/AArch64/inline-asm-speculation.ll
M llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll
M llvm/test/CodeGen/AMDGPU/early-if-convert.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
M llvm/test/CodeGen/DirectX/CreateHandleFromBinding.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
A llvm/test/CodeGen/Thumb2/peephole-opt-check-reg-sequence-compose-supports-subreg-index.ll
M llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
M llvm/test/CodeGen/X86/x86-win64-shrink-wrapping.ll
M mlir/lib/Dialect/Math/Transforms/ExpandPatterns.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/test/Dialect/Math/expand-math.mlir
M mlir/test/Dialect/Vector/vector-unroll-options.mlir
Log Message:
-----------
rebase
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/d42618687b9f...4d1c3abee5e3
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