[all-commits] [llvm/llvm-project] e6f6a1: [AMDGPU][True16][CodeGen] uaddsat/usubsat true16 s...

[Brox Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e6f6a1e863895a3378e703525a6d0d293413be33
      https://github.com/llvm/llvm-project/commit/e6f6a1e863895a3378e703525a6d0d293413be33
  Author: Brox Chen <guochen2 at amd.com>
  Date:   2025-02-25 (Tue, 25 Feb 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
    M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
    M llvm/test/CodeGen/AMDGPU/fma.f16.ll
    M llvm/test/CodeGen/AMDGPU/fmed3.ll
    M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
    M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
    M llvm/test/CodeGen/AMDGPU/v_pack.ll

  Log Message:
  -----------
  [AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (#128233)

Enable gisel selection for uaddsat and usubsat in true16 flow

This patch includes:

1. Added VGPR_16_Lo128/VGPR_16 to register bank and update register info
for recognizing 16bit regclass id and bit width
2. uaddsat/usubsat test update



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