[all-commits] [llvm/llvm-project] 4f18f3: [RISCV] Use addiw for or_is_add when or input is s...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4f18f3f09a744ddd05de2188592fa11533ff3054
      https://github.com/llvm/llvm-project/commit/4f18f3f09a744ddd05de2188592fa11533ff3054
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-02-25 (Tue, 25 Feb 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/or-is-add.ll
    M llvm/test/CodeGen/RISCV/select-const.ll
    M llvm/test/CodeGen/RISCV/select.ll

  Log Message:
  -----------
  [RISCV] Use addiw for or_is_add when or input is sign extended. (#128635)

We prefer to emit addi instead of ori because its more compressible, but
this can pessimize the sext.w removal pass.

If the input to the OR is known to be a sign extended 32 bit value, we
can use addiw instead of addi which will give more power to the sext.w
removal pass. As it is known to produce sign a sign extended value and
only consume the lower 32 bits.

Fixes #128468.



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