[all-commits] [llvm/llvm-project] 9638d0: [NVPTX] Support for memory orderings for cmpxchg (...

[Akshay Deodhar via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9638d08af96c4cb8cf16785eed92179b2658bdfe
      https://github.com/llvm/llvm-project/commit/9638d08af96c4cb8cf16785eed92179b2658bdfe
  Author: Akshay Deodhar <adeodhar at nvidia.com>
  Date:   2025-02-24 (Mon, 24 Feb 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/AtomicExpandPass.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
    M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
    M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
    M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
    M llvm/test/CodeGen/NVPTX/atomics.ll
    A llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
    A llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
    A llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
    M llvm/test/CodeGen/NVPTX/cmpxchg.ll
    A llvm/test/CodeGen/NVPTX/cmpxchg.py
    M llvm/test/CodeGen/NVPTX/lit.local.cfg

  Log Message:
  -----------
  [NVPTX] Support for memory orderings for cmpxchg (#126159)

So far, all cmpxchg instructions were lowered to atom.cas. This change
adds support for memory orders in lowering. Specifically:
- For cmpxchg which are emulated, memory ordering is enforced by adding
fences around the emulation loops.
- For cmpxchg which are lowered to PTX directly, where the memory order
is supported in ptx, lower directly to the correct ptx instruction.
- For seq_cst cmpxchg which are lowered to PTX directly, use a sequence
(fence.sc; atom.cas.acquire) to provide the semantics that we want.

Also adds tests for all possible combinations of (size, memory ordering,
address space, SM/PTX versions)

This also adds `atomicOperationOrderAfterFenceSplit` in TargetLowering,
for specially handling seq_cst atomics.



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