[all-commits] [llvm/llvm-project] e23ab7: [VPlan] Don't convert widen recipes to VP intrinsi...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e23ab73335c857d1a4c6e695cb25a5cffb1329c6
      https://github.com/llvm/llvm-project/commit/e23ab73335c857d1a4c6e695cb25a5cffb1329c6
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-02-22 (Sat, 22 Feb 2025)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VPlan.h
    M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
    M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
    M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/lib/Transforms/Vectorize/VPlanValue.h
    M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
    A llvm/test/CodeGen/RISCV/rvv/vl-opt-evl-tail-folding.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-bin-unary-ops-args.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-call-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
    A llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-div.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-intermediate-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-known-no-overflow.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-masked-loadstore.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll

  Log Message:
  -----------
  [VPlan] Don't convert widen recipes to VP intrinsics in EVL transform (#127180)

This is a copy of #126177, since it was automatically and permanently
closed because I messed up the source branch on my remote

This patch proposes to avoid converting widening recipes to VP
intrinsics during the EVL transform.

IIUC we initially did this to avoid `vl` toggles on RISC-V. However we
now have the RISCVVLOptimizer pass which mostly makes this redundant.

Emitting regular IR instead of VP intrinsics allows more generic
optimisations, both in the middle end and DAGCombiner, and we generally
have better patterns in the RISC-V backend for non-VP nodes. Sticking to
regular IR instructions is likely a lot less work than reimplementing
all of these optimisations for VP intrinsics, and on SPEC CPU 2017 we get
noticeably better code generation.



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