[all-commits] [llvm/llvm-project] 9ee671: PeepholeOpt: Allow introducing subregister uses on...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/peephole-opt/allow-introducing-subreg-uses-reg-sequence
  Home:   https://github.com/llvm/llvm-project
  Commit: 9ee6711887cc04aa1fbe161566ba51136d7fe7c0
      https://github.com/llvm/llvm-project/commit/9ee6711887cc04aa1fbe161566ba51136d7fe7c0
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-02-21 (Fri, 21 Feb 2025)

  Changed paths:
    M llvm/lib/CodeGen/PeepholeOptimizer.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
    M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
    M llvm/test/CodeGen/AMDGPU/ctpop64.ll
    M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
    M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
    M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
    M llvm/test/CodeGen/AMDGPU/fptrunc.ll
    M llvm/test/CodeGen/AMDGPU/function-args.ll
    M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
    M llvm/test/CodeGen/AMDGPU/idot4s.ll
    M llvm/test/CodeGen/AMDGPU/idot4u.ll
    M llvm/test/CodeGen/AMDGPU/idot8u.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
    M llvm/test/CodeGen/AMDGPU/kernel-args.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
    M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
    M llvm/test/CodeGen/AMDGPU/mul.ll
    M llvm/test/CodeGen/AMDGPU/mul_int24.ll
    M llvm/test/CodeGen/AMDGPU/select.f16.ll
    M llvm/test/CodeGen/AMDGPU/shl.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
    M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
    M llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
    M llvm/test/CodeGen/AMDGPU/sra.ll
    M llvm/test/CodeGen/AMDGPU/srl.ll
    M llvm/test/CodeGen/AMDGPU/udiv.ll
    M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
    M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
    M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
    M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-mixed-cases.ll
    M llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
    M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
    M llvm/test/CodeGen/Thumb2/mve-vabdus.ll
    M llvm/test/CodeGen/Thumb2/mve-vld2.ll
    M llvm/test/CodeGen/Thumb2/mve-vld3.ll
    M llvm/test/CodeGen/Thumb2/mve-vld4.ll
    M llvm/test/CodeGen/Thumb2/mve-vldst4.ll
    M llvm/test/CodeGen/Thumb2/mve-vst2.ll
    M llvm/test/CodeGen/Thumb2/mve-vst3.ll
    M llvm/test/CodeGen/Thumb2/mve-vst4-post.ll
    M llvm/test/CodeGen/Thumb2/mve-vst4.ll

  Log Message:
  -----------
  PeepholeOpt: Allow introducing subregister uses on reg_sequence

This reverts d246cc618adc52fdbd69d44a2a375c8af97b6106. We now handle
composing subregister extracts through reg_sequence.



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