[all-commits] [llvm/llvm-project] 2bf473: [GlobalOpt] Don't query TTI on a llvm.memcpy decla...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Thu Feb 20 10:44:42 PST 2025
Branch: refs/heads/users/alexey-bataev/spr/slprepresent-slp-graph-as-a-tree
Home: https://github.com/llvm/llvm-project
Commit: 2bf473bd546e65f8fc2f0d5006b8c8ef07259e24
https://github.com/llvm/llvm-project/commit/2bf473bd546e65f8fc2f0d5006b8c8ef07259e24
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
Log Message:
-----------
[GlobalOpt] Don't query TTI on a llvm.memcpy declaration. (#127760)
Querying TTI creates a Subtarget object, but an llvm.memcpy declaration
doesn't have target-cpu and target-feature attributes like functions
with definitions. This can cause a warning to be printed on RISC-V
because the target-abi in the Module requires floating point, but the
subtarget features don't enable floating point. So far we've only seen
this in LTO when an -mcpu is not supplied for the TargetMachine.
To fix this, get TTI for the calling function instead.
Fixes the issue reported here
https://github.com/llvm/llvm-project/issues/69780#issuecomment-2665273161
Commit: a6f48ed01292d0007e19a2605cba1acd4ecd123a
https://github.com/llvm/llvm-project/commit/a6f48ed01292d0007e19a2605cba1acd4ecd123a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/Register.h
M llvm/include/llvm/MC/MCRegister.h
Log Message:
-----------
[MC] Remove MCRegister::isStackSlot. (#127755)
Stack slots should only be stored in Register. The only caller was
Register::isStackSlot so just inline it there.
Commit: d57479cfbe9a6b4dccedfd1221c04973ad90ec97
https://github.com/llvm/llvm-project/commit/d57479cfbe9a6b4dccedfd1221c04973ad90ec97
Author: Jerry-Ge <jerry.ge at arm.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaMakeBroadcastable.cpp
Log Message:
-----------
[mlir][tosa] Update SelectOp's input names to match TOSA specification (#127833)
Updated:
- pred to input1
- on_true to input2
- on_false to input3
Signed-off-by: Jerry Ge <jerry.ge at arm.com>
Commit: 1841bcd5d16310c052c424dec3bcf2b703badd40
https://github.com/llvm/llvm-project/commit/1841bcd5d16310c052c424dec3bcf2b703badd40
Author: David Goldman <dallasftball at gmail.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/clangd/unittests/SymbolCollectorTests.cpp
M clang-tools-extra/clangd/unittests/XRefsTests.cpp
Log Message:
-----------
[clangd] Update XRefs to support overridden ObjC methods (#127109)
- Support finding implementors of a protocol and discovering subclasses for ObjC interfaces via the implementations call
- Support jumping to the overridden method when you trigger goto definition on an override
- Properly find references to overridden methods
Commit: 8337d01e3058e7f47675f5b2b908b4e7821895d7
https://github.com/llvm/llvm-project/commit/8337d01e3058e7f47675f5b2b908b4e7821895d7
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/CMakeLists.txt
Log Message:
-----------
[MLIR] Fix doc build (NFC)
Commit: 36eaf0daf5d6dd665d7c7a9ec38ea22f27709fed
https://github.com/llvm/llvm-project/commit/36eaf0daf5d6dd665d7c7a9ec38ea22f27709fed
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
Log Message:
-----------
AMDGPU: Don't canonicalize fminnum/fmaxnum if targets support IEEE fminimum(maximum)_num (#127711)
For targets that support IEEE fminimum_num/fmaximum_num, the
corresponding *_min_num_fXY/*_max_num_fXY instructions themselves
already did the canonicalization for the inputs. As a result, we do not
need to explicitly canonicalize the inputs for fminnum/fmaxnum.
Commit: 85e23fe9c71f97280c804a139c3d014092b30c7f
https://github.com/llvm/llvm-project/commit/85e23fe9c71f97280c804a139c3d014092b30c7f
Author: Qiongsi Wu <qiongsiwu at gmail.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M clang/include/module.modulemap
Log Message:
-----------
[Modules] Add `clang/Lex/HLSLRootSignatureTokenKinds.def` to clang's `modulemap` (#127839)
b41b86a907f653f79bab10d4c80b3a41d146c71b added a new textual header
`clang/Lex/HLSLRootSignatureTokenKinds.def` but did not add it to
`clang`'s module map. This causes build failure when building llvm with
`-DLLVM_ENABLE_MODULES=ON`. This PR adds the new textual header to the
module map and fixes the build break.
Fixing rdar://145148093.
Commit: 1c762c288ff4ff613cf26833ef55100fd0da0a34
https://github.com/llvm/llvm-project/commit/1c762c288ff4ff613cf26833ef55100fd0da0a34
Author: Deric Cheung <cheung.deric at gmail.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/CodeGenHLSL/builtins/and.hlsl
A clang/test/SemaHLSL/BuiltIns/and-errors.hlsl
Log Message:
-----------
[HLSL] Implement the 'and' HLSL function (#127098)
Addresses #125604
- Implements `and` as an HLSL builtin function
- The `and` HLSL builtin function gets lowered to the the LLVM `and`
instruction
Commit: 5caefe261fb20a70497772c24bf4e9af0ff52aef
https://github.com/llvm/llvm-project/commit/5caefe261fb20a70497772c24bf4e9af0ff52aef
Author: Letu Ren <fantasquex at gmail.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
[MLIR][LLVMIR] Add support for asin acos atan intrinsics op (#127317)
This is similar to https://github.com/llvm/llvm-project/pull/125748
Commit: c3ebbfd7368ec3e4737427eef602296a868a4ecd
https://github.com/llvm/llvm-project/commit/c3ebbfd7368ec3e4737427eef602296a868a4ecd
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/CMakeLists.txt
M llvm/lib/Target/RISCV/RISCV.h
A llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
A llvm/test/CodeGen/RISCV/fold-mem-offset.ll
M llvm/test/CodeGen/RISCV/split-offsets.ll
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
Log Message:
-----------
[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store address. (#127151)
SelectionDAG will not reassociate adds to the end of a chain if
there are multiple users of later additions. This prevents isel
from folding the immediate into a load/store address.
One easy way to see this is accessing an array in a struct with
two different indices. An ADDI will be used to get to the start
of the array then 2 different SHXADD instructions will be used to
add the scaled indices. Finally the SHXADD will be used by different
load instructions. We can remove the ADDI by folding the offset into
each load.
This patch adds a new pass that analyzes how an ADDI constant
propagates through address arithmetic. If the arithmetic is only
used by a load/store and the offset is small enough, we can adjust
the load/store offset and remove the ADDI.
This pass is placed before MachineCSE to allow cleanups if some
instructions become common after removing offsets from their inputs.
This pass gives ~3% improvement on dynamic instruction count on
541.leela_r and 544.nab_r from SPEC2017 for the train data set. There's
a ~1% improvement on 557.xz_r.
Commit: b1f882f86a5ba87ac77ed0f31e06e77a34f8303b
https://github.com/llvm/llvm-project/commit/b1f882f86a5ba87ac77ed0f31e06e77a34f8303b
Author: Jonathan Peyton <jonathan.l.peyton at intel.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_global.cpp
Log Message:
-----------
[OpenMP][NFC] Remove unused clock function types and globals (#127684)
Commit: 851177c2e35e17d5bca68521a473f0dad1ad29ec
https://github.com/llvm/llvm-project/commit/851177c2e35e17d5bca68521a473f0dad1ad29ec
Author: Jonathan Peyton <jonathan.l.peyton at intel.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_global.cpp
M openmp/runtime/src/kmp_runtime.cpp
Log Message:
-----------
[OpenMP][NFC] Remove unused __kmp_dispatch_lock global (#127686)
Commit: dca73063653ca7d35afb3226ae66623495086204
https://github.com/llvm/llvm-project/commit/dca73063653ca7d35afb3226ae66623495086204
Author: Petr Hosek <phosek at google.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M clang/utils/perf-training/CMakeLists.txt
M clang/utils/perf-training/lit.cfg
M clang/utils/perf-training/lit.site.cfg.in
Log Message:
-----------
[clang][perf-training] Support excluding LLVM build from PGO training (#126876)
Using LLVM build itself for PGO training is convenient and a great
starting point but it also has several issues:
* LLVM build implicitly depends on tools other than CMake and C/C++
compiler and if those tools aren't available in PATH, the build will
fail.
* LLVM build also requires standard headers and libraries which may not
always be available in the default location requiring an explicit
sysroot.
* Building a single configuration (-DCMAKE_BUILD_TYPE=Release) only
exercises the -O3 pipeline and can pesimize other configurations.
* Building for the host target doesn't exercise all other targets.
* Since LLVMSupport is a static library, this doesn't exercise the
linker (beyond what the CMake itself does).
Rather than using LLVM build, ideally we would provide a more minimal,
purpose built corpus. While we're working on building such a corpus,
provide a CMake option that lets vendors disable the use LLVM build for
PGO training.
Commit: 4a411eb4ee673e2687d38fda16d6db6b907f37d2
https://github.com/llvm/llvm-project/commit/4a411eb4ee673e2687d38fda16d6db6b907f37d2
Author: Benoit Jacob <jacob.benoit.1 at gmail.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h
M mlir/test/Conversion/MathToROCDL/math-to-rocdl.mlir
Log Message:
-----------
[MLIR] Fix rewrite of ops with vector operands to LLVM on GPU (#127844)
There was a discrepancy between the type-converter and rewrite-pattern
parts of conversion to LLVM used in various GPU targets, at least ROCDL
and NVVM:
- The TypeConverter part was handling vectors of arbitrary rank,
converting them to nests of `!llvm.array< ... >` with a vector at the
inner-most dimension:
https://github.com/llvm/llvm-project/blob/8337d01e3058e7f47675f5b2b908b4e7821895d7/mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp#L629-L655
- The rewrite pattern part was not handling `llvm.array`:
https://github.com/llvm/llvm-project/blob/8337d01e3058e7f47675f5b2b908b4e7821895d7/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp#L594-L596
That led to conversion failures when lowering `math` dialect ops on
rank-2 vectors, as in the testcase being added in this PR.
This PR fixes this by reusing a shared utility already used in other
conversions to LLVM:
https://github.com/llvm/llvm-project/blob/8337d01e3058e7f47675f5b2b908b4e7821895d7/mlir/lib/Conversion/LLVMCommon/VectorPattern.cpp#L80-L104
---------
Signed-off-by: Benoit Jacob <jacob.benoit.1 at gmail.com>
Commit: 1987f93d03cec41f2599752cb63c9d130b901de3
https://github.com/llvm/llvm-project/commit/1987f93d03cec41f2599752cb63c9d130b901de3
Author: vporpo <vporpodas at google.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/include/llvm/SandboxIR/Value.h
M llvm/include/llvm/SandboxIR/Values.def
M llvm/lib/SandboxIR/BasicBlock.cpp
M llvm/lib/SandboxIR/Context.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
Log Message:
-----------
[SandboxIR] OpaqueValue (#127699)
This patch implements a new subclass of the Value class used for Sandbox
IR Values that we don't support, like metadata or inline asm. The goal
is to never have null sandboxir::Value objects, because this is not the
expected behavior.
Commit: 37d0f20593a65c552d717561efb64c8cf29c1d3c
https://github.com/llvm/llvm-project/commit/37d0f20593a65c552d717561efb64c8cf29c1d3c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/CMakeLists.txt
M llvm/lib/Target/RISCV/RISCV.h
R llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
R llvm/test/CodeGen/RISCV/fold-mem-offset.ll
M llvm/test/CodeGen/RISCV/split-offsets.ll
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
Log Message:
-----------
Revert "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store address. (#127151)"
This reverts commit c3ebbfd7368ec3e4737427eef602296a868a4ecd.
Seeing some test failures on the build bot.
Commit: c9ff8399647cd15cdb9f8853b45854920de17162
https://github.com/llvm/llvm-project/commit/c9ff8399647cd15cdb9f8853b45854920de17162
Author: Kunwar Grover <groverkss at gmail.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/test/Dialect/Linalg/fuse-with-reshape-by-collapsing.mlir
M mlir/test/Dialect/Linalg/fusion-push-reshape.mlir
Log Message:
-----------
[mlir][Linalg] Fix linalg.generic iteration domain collapse for dynamic dims (#118208)
This pr fixes how iteration domain of linalg.generic is collapsed when
fusing with tensor.expand_shape. Previously, the output_shape for
tensor.expand shape was infered, which doesn't always work except some
special cases.
This patch makes the logic explicitly set the bounds of the new
collapsed iteration domain, because we already know them.
---------
Co-authored-by: Jakub Kuderski <kubakuderski at gmail.com>
Commit: 26e375046dbde27957548d5e9a9885c3eff29019
https://github.com/llvm/llvm-project/commit/26e375046dbde27957548d5e9a9885c3eff29019
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/CMakeLists.txt
M llvm/lib/Target/RISCV/RISCV.h
A llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
A llvm/test/CodeGen/RISCV/fold-mem-offset.ll
M llvm/test/CodeGen/RISCV/split-offsets.ll
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
Log Message:
-----------
Recommit "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store address. (#127151)"
Tests have been re-generated with recent scheduler changes.
Original message:
SelectionDAG will not reassociate adds to the end of a chain if
there are multiple users of later additions. This prevents isel
from folding the immediate into a load/store address.
One easy way to see this is accessing an array in a struct with
two different indices. An ADDI will be used to get to the start
of the array then 2 different SHXADD instructions will be used to
add the scaled indices. Finally the SHXADD will be used by different
load instructions. We can remove the ADDI by folding the offset into
each load.
This patch adds a new pass that analyzes how an ADDI constant
propagates through address arithmetic. If the arithmetic is only
used by a load/store and the offset is small enough, we can adjust
the load/store offset and remove the ADDI.
This pass is placed before MachineCSE to allow cleanups if some
instructions become common after removing offsets from their inputs.
This pass gives ~3% improvement on dynamic instruction count on
541.leela_r and 544.nab_r from SPEC2017 for the train data set. There's
a ~1% improvement on 557.xz_r.
Commit: 84eacd302e54a8a1b2b56684efb422911707c6af
https://github.com/llvm/llvm-project/commit/84eacd302e54a8a1b2b56684efb422911707c6af
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
Log Message:
-----------
[gn build] Port 26e375046dbd
Commit: c833746c6c062677a040d18d837c7fad71939171
https://github.com/llvm/llvm-project/commit/c833746c6c062677a040d18d837c7fad71939171
Author: Björn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
Log Message:
-----------
[DSE] Make iter order deterministic in removePartiallyOverlappedStores. NFC (#127678)
In removePartiallyOverlappedStores we iterate over
InstOverlapIntervalsTy which is a DenseMap. Change that map into using
MapVector to ensure that we apply the transforms in a deterministic
order. I've only seen that the order matters if starting to use names
for the instructions created when doing the transforms. But such things
are a bit annoying when debugging etc.
Commit: 1761066fc641be529ca45b3cfcf4788b8a7a688d
https://github.com/llvm/llvm-project/commit/1761066fc641be529ca45b3cfcf4788b8a7a688d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
Log Message:
-----------
[GlobalOpt] Remove Function* argument from tryWidenGlobalArrayAndDests. NFC (#127848)
This is only used to get the Module and the LLVMContext. We can get both
of those from the GlobalVariable*.
Commit: 1a6ed4d06e3c5b05e5ed9873888165c671292b06
https://github.com/llvm/llvm-project/commit/1a6ed4d06e3c5b05e5ed9873888165c671292b06
Author: Kunwar Grover <groverkss at gmail.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
Log Message:
-----------
[mlir][Vector] Deprecate vector.extractelement/vector.insertelement (#113829)
See
https://discourse.llvm.org/t/rfc-psa-remove-vector-extractelement-and-vector-insertelement-ops-in-favor-of-vector-extract-and-vector-insert-ops/71116/6
for more information.
Commit: 92b07520bcba1134f60d368c3f0d9216ebbe76e5
https://github.com/llvm/llvm-project/commit/92b07520bcba1134f60d368c3f0d9216ebbe76e5
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/test/ThinLTO/X86/memprof-recursive.ll
M llvm/test/Transforms/MemProfContextDisambiguation/recursive.ll
Log Message:
-----------
[MemProf] Support cloning through recursive cycles (#127429)
In order to facilitate cloning of recursive cycles, we first identify
backedges using a standard DFS search from the root callers, then
initially defer recursively invoking the cloning function via those
edges. This is because the cloning opportunity along the backedge may
not be exposed until the current node is cloned for other non-backedge
callers that are cold after the earlier recursive cloning, resulting
in a cold predecessor of the backedge. So we recursively invoke the
cloning function for the backedges during the cloning of the current
node for its caller edges (which were sorted to enable handling cold
callers first).
There was no significant time or memory overhead measured for several
large applications.
Commit: 3836559e65b002579e2c6697969557ffbbb8cc7d
https://github.com/llvm/llvm-project/commit/3836559e65b002579e2c6697969557ffbbb8cc7d
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/test/Transforms/InstCombine/select-icmp-and.ll
Log Message:
-----------
[InstCombine] Test for regession with trunc in foldSelectICmpAnd
Commit: c0c42c8b3213520700f15587ab8aa4477a286ff9
https://github.com/llvm/llvm-project/commit/c0c42c8b3213520700f15587ab8aa4477a286ff9
Author: vporpo <vporpodas at google.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/lib/SandboxIR/Context.cpp
Log Message:
-----------
[SandboxIR][NFC] Change order of ifs in Context::getOrCreateValueInternal() (#127891)
Move the most common if statement to the top and the least common ones
to the bottom. This should save CPU cycles during compilation.
This patch also prefixes the llvm variables with the LLVM prefix to make
the naming convention in this function more uniform. For example `C` to
`LLVMC`.
Commit: 5f8b2568219d5e516928aed67f13b59de8ccee17
https://github.com/llvm/llvm-project/commit/5f8b2568219d5e516928aed67f13b59de8ccee17
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefMemberChecker.cpp
A clang/test/Analysis/Checkers/WebKit/unchecked-members-objc.mm
A clang/test/Analysis/Checkers/WebKit/uncounted-members-objc.mm
Log Message:
-----------
Check the type of Objective-C++ instance variables in WebKit member variable checkers. (#127570)
Like a C++ member variable, every Objective-C++ instance variable must
be a RefPtr, Ref CheckedPtr, or CheckedRef to an object, not a raw
pointer or reference.
Commit: 8363b0a6bab041b54316962e3e8948098148baeb
https://github.com/llvm/llvm-project/commit/8363b0a6bab041b54316962e3e8948098148baeb
Author: Baranov Victor <70346889+vbvictor at users.noreply.github.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.cpp
M clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/const-correctness.rst
A clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-allowed-types.cpp
Log Message:
-----------
[clang-tidy] add AllowedTypes option to misc-const-correctness (#122951)
Add option `AllowedTypes` which allow users to specify types they want
to exclude from const-correctness check.
Small real-world example:
```cpp
#include <mutex>
int main() {
std::mutex m;
std::lock_guard<std::mutex> l(m); // we want to ignore it since std::lock_guard is already immutable.
}
```
Closes issue https://github.com/llvm/llvm-project/issues/122592
Commit: 0fe0968c936b5e3ea83ed75ad8f8bb56e517eebe
https://github.com/llvm/llvm-project/commit/0fe0968c936b5e3ea83ed75ad8f8bb56e517eebe
Author: David Tellenbach <dtellenbach at apple.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
A llvm/test/CodeGen/AArch64/cmpbr-branch-relaxation.mir
A llvm/test/CodeGen/AArch64/cmpbr-early-ifcvt.mir
A llvm/test/CodeGen/AArch64/cmpbr-reg-imm-at-bounds.ll
A llvm/test/CodeGen/AArch64/cmpbr-reg-imm.ll
A llvm/test/CodeGen/AArch64/cmpbr-reg-reg.ll
Log Message:
-----------
[AArch64][FEAT_CMPBR] Codegen for Armv9.6-a compare-and-branch (#116465)
This patch adds codegen for all Arm9.6-a compare-and-branch
instructions, that operate on full w or x registers. The instruction
variants operating on half-words (cbh) and bytes (cbb) are added in a
subsequent patch.
Since CB doesn't use standard 4-bit Arm condition codes but a reduced
set of conditions, encoded in 3 bits, some conditions are expressed by
modifying operands, namely incrementing or decrementing immediate
operands and swapping register operands. To invert a CB instruction it's
therefore not enough to just modify the condition code which doesn't
play particularly well with how the backend is currently organized. We
therefore introduce a number of pseudos which operate on the standard
4-bit condition codes and lower them late during codegen.
Commit: ef49760fa94d1d75cf42b0666b2ee29f9b13d5a2
https://github.com/llvm/llvm-project/commit/ef49760fa94d1d75cf42b0666b2ee29f9b13d5a2
Author: Zaky Hermawan <44158147+ZakyHermawan at users.noreply.github.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/unistd.yaml
M libc/src/unistd/CMakeLists.txt
A libc/src/unistd/getsid.h
M libc/src/unistd/linux/CMakeLists.txt
A libc/src/unistd/linux/getsid.cpp
M libc/test/src/unistd/CMakeLists.txt
A libc/test/src/unistd/getsid_test.cpp
Log Message:
-----------
[libc][POSIX][unistd] implement getsid (#127341)
Fixes https://github.com/llvm/llvm-project/issues/126603
---------
Signed-off-by: ZakyHermawan <zaky.hermawan9615 at gmail.com>
Commit: 6342095bce61f18baf7c305716be3239a274fb6d
https://github.com/llvm/llvm-project/commit/6342095bce61f18baf7c305716be3239a274fb6d
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
Log Message:
-----------
[memprof] Fix a warning
This patch fixes:
llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp:3409:8:
error: unused variable 'I' [-Werror,-Wunused-variable]
Commit: 0127f169dc8e0b5b6c2a24f74cd42d9d277916f6
https://github.com/llvm/llvm-project/commit/0127f169dc8e0b5b6c2a24f74cd42d9d277916f6
Author: Sebastian Jodłowski <jodelek at gmail.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsNVPTX.td
M clang/include/clang/Basic/Cuda.h
M clang/lib/Basic/Cuda.cpp
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/test/Misc/target-invalid-cpu-note/nvptx.c
Log Message:
-----------
[CUDA] Add support for sm101 and sm120 target architectures (#127187)
Add support for sm101 and sm120 target architectures. It requires CUDA
12.8.
---------
Co-authored-by: Sebastian Jodlowski <sjodlowski at nuro.ai>
Commit: 6cc7ca084a5bbb7ccf606cab12065604453dde59
https://github.com/llvm/llvm-project/commit/6cc7ca084a5bbb7ccf606cab12065604453dde59
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M clang/lib/Headers/gpuintrin.h
M clang/lib/Headers/nvptxintrin.h
M libc/test/integration/src/__support/GPU/scan_reduce.cpp
Log Message:
-----------
[Clang] Fix cross-lane scan when given divergent lanes (#127703)
Summary:
The scan operation implemented here only works if there are contiguous
ones in the executation mask that can be used to propagate the result.
There are two solutions to this, one is to enter 'whole-wave-mode' and
forcibly turn them back on, or to do this serially. This implementation
does the latter because it's more portable, but checks to see if the
parallel fast-path is applicable.
Needs to be backported for correct behavior and because it fixes a
failing libc test.
Commit: 5622f2232b3564e86e207401f6c196ba9ea01fb7
https://github.com/llvm/llvm-project/commit/5622f2232b3564e86e207401f6c196ba9ea01fb7
Author: youngd007 <davidayoung at meta.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
A llvm/test/tools/llvm-dwarfdump/X86/debug-names-verify-completeness-json-output.s
A llvm/test/tools/llvm-dwarfdump/X86/debug-names-verify-cu-lists-json-output.s
Log Message:
-----------
Add back deleted test for llvm-dwarfdump JSON output (#127685)
Looks like https://github.com/llvm/llvm-project/pull/124936 was reverted
(for modifying JSON output), but the test for JSON output with errors
was deleted in https://github.com/llvm/llvm-project/pull/126587 (to
attempt to fix failing build)
This will add back a test and a new one for llvm-dwarfdump to validate
the JSON for errors. One case where the sub-categories will eventually
appear and another where not.
test plan:
ninja check-llvm-tools-llvm-dwarfdump
Commit: b0e24d17f294ce421ebf7174d8c74cdae374d7e7
https://github.com/llvm/llvm-project/commit/b0e24d17f294ce421ebf7174d8c74cdae374d7e7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
M llvm/test/CodeGen/RISCV/rvv/vleff.ll
Log Message:
-----------
[RISCV] Use opaque pointers in some tests. NFC (#127906)
Commit: f62f13d5db212b4bebe6fc143fb9827703e88dfd
https://github.com/llvm/llvm-project/commit/f62f13d5db212b4bebe6fc143fb9827703e88dfd
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M lldb/include/lldb/API/SBCommandReturnObject.h
M lldb/include/lldb/API/SBValue.h
M lldb/include/lldb/Interpreter/CommandReturnObject.h
M lldb/include/lldb/ValueObject/ValueObjectList.h
M lldb/source/API/SBCommandReturnObject.cpp
M lldb/source/Commands/CommandObjectDWIMPrint.cpp
M lldb/source/Commands/CommandObjectExpression.cpp
M lldb/source/Commands/CommandObjectFrame.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/ValueObject/ValueObjectList.cpp
M lldb/test/API/api/command-return-object/TestSBCommandReturnObject.py
M lldb/test/API/commands/frame/var/TestFrameVar.py
M lldb/test/API/functionalities/target_var/TestTargetVar.py
Log Message:
-----------
[lldb] Store the return SBValueList in the CommandReturnObject (#127566)
There are a lot of lldb commands whose result is really one or more
ValueObjects that we then print with the ValueObjectPrinter. Now that we
have the ability to access the SBCommandReturnObject through a callback
(#125006), we can store the resultant ValueObjects in the return object,
allowing an IDE to access the SBValues and do its own rich formatting.
rdar://143965453
Commit: 9107ad41bb4a0a00db2a5fcc435a2907fa67c7bc
https://github.com/llvm/llvm-project/commit/9107ad41bb4a0a00db2a5fcc435a2907fa67c7bc
Author: Peng Liu <winner245 at hotmail.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M libcxx/test/std/utilities/template.bitset/bitset_test_cases.h
Log Message:
-----------
Apply clang-format to bitset_test_cases.h to make PR#120807 cleaner
Applying this formatting per reviewer comment on PR #120807: https://github.com/llvm/llvm-project/pull/120807/files#r1961834956
Commit: 86f0e6dc1177fe45ec6b0ed0707053b28c227321
https://github.com/llvm/llvm-project/commit/86f0e6dc1177fe45ec6b0ed0707053b28c227321
Author: Roland McGrath <mcgrathr at google.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M libc/utils/hdrgen/header.py
M libc/utils/hdrgen/main.py
A libc/utils/hdrgen/tests/expected_output/test_small.json
M libc/utils/hdrgen/tests/test_integration.py
Log Message:
-----------
[libc] Add --json mode for hdrgen (#127847)
This adds a feature to hdrgen to emit JSON summaries of header
files for build system integration. For now the summaries have
only the basic information about each header that is relevant for
build and testing purposes: the standards and includes lists.
Commit: 131a3cfab46ff8eb03ae102a39ea35b7f5e11d1b
https://github.com/llvm/llvm-project/commit/131a3cfab46ff8eb03ae102a39ea35b7f5e11d1b
Author: Christopher Di Bella <cjdb at google.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M clang/test/CIR/emit-actions.cpp
Log Message:
-----------
[CIR] updates test for 75ea7aed (#127917)
Commit: 19bad2ac4a4b809b5442023ac85fb0b7cf26dd7c
https://github.com/llvm/llvm-project/commit/19bad2ac4a4b809b5442023ac85fb0b7cf26dd7c
Author: YongKang Zhu <yongzhu at fb.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M bolt/lib/RuntimeLibs/InstrumentationRuntimeLibrary.cpp
Log Message:
-----------
[BOLT][NFC] Fix an incorrect address used in a BOLT-INFO message (#127902)
Commit: 75bd46e01ff5c4f34e7b7fd8382f7f1028d81440
https://github.com/llvm/llvm-project/commit/75bd46e01ff5c4f34e7b7fd8382f7f1028d81440
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/include/llvm/Analysis/GlobalsModRef.h
M llvm/lib/Analysis/GlobalsModRef.cpp
M llvm/test/Analysis/GlobalsModRef/nonescaping-noalias.ll
Log Message:
-----------
[globals-aa] Improved isNonEscapingGlobalNoAlias. (#127707)
A non-escaping global should never alias with non-pointer values
and `ptr null`. This should improve disambiguation of global
pointers with relation to Flang runtime calls (given that
`nosync nocallback` attributes are properly set).
It also seems to be an obvious improvement with little overhead.
Commit: 007f601f15059520b64c09a32b7bb9d99b845d7e
https://github.com/llvm/llvm-project/commit/007f601f15059520b64c09a32b7bb9d99b845d7e
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
Log Message:
-----------
[Clang][Docs] Document -Xarch_ better (#127890)
Summary:
This argument is esoteric and previously didn't even work consistently
across the targets. Now that's fixed we should document it better.
---------
Co-authored-by: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Commit: 5d4998bc02cebd77e70f0fa712ab8e1eb8f643f0
https://github.com/llvm/llvm-project/commit/5d4998bc02cebd77e70f0fa712ab8e1eb8f643f0
Author: Jinsong Ji <jinsong.ji at intel.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/global_none_meta.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/global_none_meta.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/global_none_meta.test
M llvm/utils/UpdateTestChecks/common.py
M llvm/utils/update_cc_test_checks.py
M llvm/utils/update_test_checks.py
Log Message:
-----------
UpdateTestChecks: Don't check meta details in func definition w/--global none (#124205)
When --check-globals none, we skipped all the globals in check lines.
However, we are still checking the meta info in function defintion.
The generated checks are still sensitive to metadata changes.
This is to scrub the meta info and match them with {{.*}} instead.
Commit: f5b311e47de044160aeb25221095898c35c4847f
https://github.com/llvm/llvm-project/commit/f5b311e47de044160aeb25221095898c35c4847f
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M clang/cmake/caches/Release.cmake
Log Message:
-----------
[CMake][Release] Statically link clang with stage1 runtimes (#127268)
This change will cause clang and the other tools to statically link
against the runtimes built in stage1. This will make the built binaries
more portable by eliminating dependencies on system libraries like
libgcc and libstdc++.
Commit: ab7664c02cfe6791d20a887ae0bc0653223e3fbf
https://github.com/llvm/llvm-project/commit/ab7664c02cfe6791d20a887ae0bc0653223e3fbf
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M mlir/include/mlir/Analysis/DataFlow/IntegerRangeAnalysis.h
M mlir/lib/Analysis/DataFlow/IntegerRangeAnalysis.cpp
M mlir/lib/Dialect/Arith/Transforms/UnsignedWhenEquivalent.cpp
M mlir/lib/Interfaces/InferIntRangeInterface.cpp
Log Message:
-----------
[mlir][integer-range-analysis] expose helpers in header and fix ConstantIntRange print (#127888)
Commit: bf9b72e134bff7eb6861e07752d70cb33348b540
https://github.com/llvm/llvm-project/commit/bf9b72e134bff7eb6861e07752d70cb33348b540
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
A clang/test/CodeGenCUDA/increment-index-for-thunks.cu
Log Message:
-----------
[NFC][Clang] Precommit test for VTable codegen (#124983)
Associated PR: https://github.com/llvm/llvm-project/pull/124989
Commit: a16fa3a965eac8966d5a6faba0bf373af1300f21
https://github.com/llvm/llvm-project/commit/a16fa3a965eac8966d5a6faba0bf373af1300f21
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/tools/libclang/CXString.cpp
Log Message:
-----------
Reland "[libclang] Always Dup in createRef(StringRef)" (#127078)
Reverts #127076 to reland #125020.
Use-after-free should be fixed here #127063
Commit: f178e51747b47a181cd6be8dc4ad8943ea5728b3
https://github.com/llvm/llvm-project/commit/f178e51747b47a181cd6be8dc4ad8943ea5728b3
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
A llvm/test/CodeGen/PowerPC/llvm.modf.ll
Log Message:
-----------
[SDAG] Add missing ppc_fp128 ExpandFloatRes legalization for modf (#127895)
Should fix: https://lab.llvm.org/buildbot/#/builders/72/builds/8380
(`test_modf_ppcf128` is the test case that needed the additional
legalization)
Commit: 3e5ae5777d92b6f8c647c3f6969fbca0f0f769ff
https://github.com/llvm/llvm-project/commit/3e5ae5777d92b6f8c647c3f6969fbca0f0f769ff
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M .github/workflows/release-binaries.yml
Log Message:
-----------
workflows/release-binaries: Disable Flang on x86_64 macOS (#127216)
The flang build was taking 2-3 hours and causing the entire job to
timeout, so we need to disable it.
Commit: 37c341df283fa028c6e3849d4c024456e4d197c5
https://github.com/llvm/llvm-project/commit/37c341df283fa028c6e3849d4c024456e4d197c5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
Log Message:
-----------
Revert "AMDGPU: Don't canonicalize fminnum/fmaxnum if targets support IEEE fminimum(maximum)_num (#127711)"
This reverts commit 36eaf0daf5d6dd665d7c7a9ec38ea22f27709fed.
This is not a sound approach to dealing with this instruction change.
The new behavior is a different opcode pair, not a modifier on the
existing opcode.
Commit: 1fd280d0f2a31a41e74374c7757a8a4d01e116b5
https://github.com/llvm/llvm-project/commit/1fd280d0f2a31a41e74374c7757a8a4d01e116b5
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/test/Dialect/Affine/affine-data-copy.mlir
Log Message:
-----------
[MLIR][Affine] Add missing check in affine data copy nest generation (#127809)
Handle case where no lower or upper bound could be found for a
dimension. Invalid IR was being generated silently for a test case.
Fixes: https://github.com/llvm/llvm-project/issues/127808
Commit: f8bdbed5b3f12c5e1c38a29cd71df286a9e2725c
https://github.com/llvm/llvm-project/commit/f8bdbed5b3f12c5e1c38a29cd71df286a9e2725c
Author: David Olsen <dolsen at nvidia.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
A clang/include/clang/CIR/TypeEvaluationKind.h
A clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
A clang/lib/CIR/CodeGen/CIRGenFunction.cpp
A clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
A clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.h
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
A clang/test/CIR/func-simple.cpp
M clang/test/CIR/global-var-simple.cpp
R clang/test/CIR/hello.c
Log Message:
-----------
[CIR] Upstream simple function bodies (#127674)
Enable ClangIR generation for very simple functions. The functions have
to return `void` or an integral type, contain only compound statements
or `return` statements, and `return` statement expressions can only be
integral literals of the correct type. The functions can have
parameters, but those are currently ignored because there is no way to
access them.
This change intentionally focuses on breadth (introducing scopes,
statements, and expressions) rather than depth, because it enables
people to work on upstreaming in parallel without interference.
The new ClangIR ops in this change are `ReturnOp`, `YieldOp`, `ScopeOp`,
and `TrapOp`. These operations are complete (except for the
`ParentOneOf` property) and shouldn't require further upstreaming
changes. Significant additions were made to `FuncOp`, adding a type and
a region, but that operation is still far from complete.
The classes `ScalarExprEmitter` and `CIRGenFunction`, along with the
`emit*` functions in `CIRGenFunction` that generate ClangIR for
statements, are new in this change. All of these are very incomplete and
will be filled out in later upstreaming patches.
Existing test `hello.c` is removed and replaced by the new test
`func-simple.cpp`. This tests all forms of functions that are currently
supported.
Commit: c58011dc65719c4207c2e641a6e32af1c60cdbe8
https://github.com/llvm/llvm-project/commit/c58011dc65719c4207c2e641a6e32af1c60cdbe8
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
Log Message:
-----------
[RISCV][VLOPT] Peek through copies in checkUsers (#127656)
Currently if a user of an instruction isn't a vector pseudo we bail. For
simple non-subreg virtual COPYs, we can peek through their uses by using
a worklist.
This is extracted from a loop in TSVC2 (s273) that contains a fcmp +
select, which produces a copy that doesn't seem to be coalesced away.
Commit: 557628dbe6a935b1ad5e1bcfd51ac3a65e35d874
https://github.com/llvm/llvm-project/commit/557628dbe6a935b1ad5e1bcfd51ac3a65e35d874
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
A llvm/include/llvm/CodeGen/RegAllocPriorityAdvisor.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
M llvm/lib/CodeGen/MLRegAllocPriorityAdvisor.cpp
M llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegAllocGreedy.h
M llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp
R llvm/lib/CodeGen/RegAllocPriorityAdvisor.h
M llvm/lib/Passes/PassBuilder.cpp
Log Message:
-----------
[CodeGen][NewPM] Port RegAllocPriorityAdvisor analysis to NPM (#118462)
Similar to #117309.
The advisor and logger are accessed through the provider, which is
served by the new PM. Legacy PM forwards calls to the provider.
New PM is a machine function analysis that lazily initializes the
provider.
Commit: 58279d1ee1b567e8ca793d6d1eb6e0f1d5e7279e
https://github.com/llvm/llvm-project/commit/58279d1ee1b567e8ca793d6d1eb6e0f1d5e7279e
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/IOHandler.h
M lldb/include/lldb/Host/Editline.h
M lldb/include/lldb/Host/File.h
M lldb/include/lldb/Host/StreamFile.h
M lldb/include/lldb/Interpreter/ScriptInterpreter.h
M lldb/include/lldb/lldb-forward.h
M lldb/source/Commands/CommandObjectBreakpointCommand.cpp
M lldb/source/Commands/CommandObjectCommands.cpp
M lldb/source/Commands/CommandObjectExpression.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Commands/CommandObjectType.cpp
M lldb/source/Commands/CommandObjectWatchpointCommand.cpp
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/IOHandler.cpp
M lldb/source/Core/IOHandlerCursesGUI.cpp
M lldb/source/Expression/REPL.cpp
M lldb/source/Host/common/Editline.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Interpreter/ScriptInterpreter.cpp
M lldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/unittests/Editline/EditlineTest.cpp
Log Message:
-----------
[lldb] Synchronize the debuggers output & error streams
This patch improves the synchronization of the debugger's output and error
streams using two new abstractions: `LockableStreamFile` and
`LockedStreamFile`.
- `LockableStreamFile` is a wrapper around a `StreamFile` and a mutex. Client
cannot use the `StreamFile` without calling `Lock`, which returns a
`LockedStreamFile`.
- `LockedStreamFile` is an RAII object that locks the stream for the duration
of its existence. As long as you hold on to the returned object you are
permitted to write to the stream. The destruction of the object
automatically flush the output stream.
Commit: df96b56b9fad29ff0a8654730952d02e7ef6cc50
https://github.com/llvm/llvm-project/commit/df96b56b9fad29ff0a8654730952d02e7ef6cc50
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp
M llvm/test/CodeGen/RISCV/O0-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/commutable.ll
M llvm/test/CodeGen/RISCV/rvv/copyprop.mir
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
M llvm/test/CodeGen/RISCV/rvv/vector-reassociations.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
Log Message:
-----------
[RISCV] Move VMV0 elimination past machine SSA opts (#126850)
This is the follow up to #125026 that keeps mask operands in virtual
register form for as long as possible throughout the backend.
The diffs in this patch are from MachineCSE/MachineSink/RISCVVLOptimizer
kicking in.
The invariant that the mask COPY never has a subreg no longer holds
after MachineCSE (it coalesces some copies), so it needed to be relaxed.
Commit: 95000fdb9e98a88b923fa7aa4bdeffbc618a323c
https://github.com/llvm/llvm-project/commit/95000fdb9e98a88b923fa7aa4bdeffbc618a323c
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGVTables.cpp
M clang/test/CodeGenCUDA/increment-index-for-thunks.cu
Log Message:
-----------
[CUDA] Increment VTable index for device thunks (#124989)
Currently, the clang frontend incorrectly emits the callee instead of
the thunk for the callee in the VTable. This is the case because the
thunk index is not incremented when their callees cannot be emitted.
This patch fixes the bug.
Commit: 62e4436bb80b82c836fb747b391696700f089e6b
https://github.com/llvm/llvm-project/commit/62e4436bb80b82c836fb747b391696700f089e6b
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
M llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h
M llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
Log Message:
-----------
[NVPTX] Use appropriate operands in ReplaceImageHandles (NFC) (#127898)
Prior to this change NVPTXReplaceImageHandles replaced operands with
indices and populated a table matching these indices to strings to be
used in AsmPrinter. We can clean this up by simply inserting the correct
external symbol or global address operands during
NVPTXReplaceImageHandles, largely removing the need for the table.
Commit: 57bac14f4bcc8b43edc3e27be3d93609f7f4037b
https://github.com/llvm/llvm-project/commit/57bac14f4bcc8b43edc3e27be3d93609f7f4037b
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
Log Message:
-----------
[lldb] Fix header include order in ScriptInterpreterPython.cpp
Should fix the following compile error on Windows:
C:\Python312\include\pyconfig.h(225): error C2371: 'pid_t': redefinition; different basic types
C:\buildbot\as-builder-10\lldb-x-aarch64\llvm-project\lldb\include\lldb/Host/windows/PosixApi.h(80): note: see declaration of 'pid_t'
Commit: 92ddbbd89fa2a904119267d3565bed8e95f4f8e2
https://github.com/llvm/llvm-project/commit/92ddbbd89fa2a904119267d3565bed8e95f4f8e2
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/RDFRegisters.h
M llvm/include/llvm/CodeGen/Register.h
M llvm/lib/CodeGen/InlineSpiller.cpp
M llvm/lib/CodeGen/RDFRegisters.cpp
Log Message:
-----------
[CodeGen] Remove static member functions Register::stackSlot2Index/isStackSlot. NFC
Migrate the few users to the nonstatic member functions.
Commit: 77a8338fa65b959794c4ab9b2afd1d08deed49fe
https://github.com/llvm/llvm-project/commit/77a8338fa65b959794c4ab9b2afd1d08deed49fe
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/lib/Target/ARC/ARCOptAddrMode.cpp
Log Message:
-----------
[ARC] Update code after removal of Register::isStackSlot. NFC
Commit: 8b58cb853a3805e2c58177c2646d6320c8750c98
https://github.com/llvm/llvm-project/commit/8b58cb853a3805e2c58177c2646d6320c8750c98
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SelectionDAG][NFC] Refactor duplicate code into SDNode::bitcastToAPInt() (#127503)
Commit: a6eb7d6acc268bd9507bf1c6e2c433174d8fd0c2
https://github.com/llvm/llvm-project/commit/a6eb7d6acc268bd9507bf1c6e2c433174d8fd0c2
Author: Fangrui Song <i at maskray.me>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/lib/Target/ARC/ARCOptAddrMode.cpp
Log Message:
-----------
[ARC] Remove unneeded isStackSlot
Commit: 2130b9cea4c3274375be53c981d23b1838897e38
https://github.com/llvm/llvm-project/commit/2130b9cea4c3274375be53c981d23b1838897e38
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Coroutines/MaterializationUtils.cpp
Log Message:
-----------
[Coroutines] Avoid repeated hash lookups (NFC) (#127956)
Commit: 77183a46a5fd4e0b92ea91096c6d58bea7a7f43b
https://github.com/llvm/llvm-project/commit/77183a46a5fd4e0b92ea91096c6d58bea7a7f43b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/Register.h
M llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
M llvm/lib/CodeGen/DetectDeadLanes.cpp
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
M llvm/lib/Target/Hexagon/BitTracker.cpp
M llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
M llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp
Log Message:
-----------
[CodeGen] Remove static member function Register::virtReg2Index. NFC (#127962)
Use the nonstatic member instead.
I'm pretty sure the code in SPRIV is a layering violation. MC layer
files are using a CodeGen header.
Commit: 7d03c8e256a78b67a645b78e3ca93287bee0cd37
https://github.com/llvm/llvm-project/commit/7d03c8e256a78b67a645b78e3ca93287bee0cd37
Author: Matthias Springer <me at m-sp.org>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M mlir/lib/AsmParser/Parser.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/test/Dialect/SCF/invalid.mlir
Log Message:
-----------
[mlir][Parser] Fix use-after-free when parsing invalid reference to nested definition (#127778)
This commit fixes a use-after-free crash when parsing the following
invalid IR:
```mlir
scf.for ... iter_args(%var = %foo) -> tensor<?xf32> {
%foo = "test.inner"() : () -> (tensor<?xf32>)
scf.yield %arg0 : tensor<?xf32>
}
```
The `scf.for` parser was implemented as follows:
1. Resolve operands (including `%foo`).
2. Parse the region.
During operand resolution, a forward reference
(`unrealized_conversion_cast`) is added by the parser because `%foo` has
not been defined yet. During region parsing, the definition of `%foo` is
found and the forward reference is replaced with the actual definition.
(And the forward reference is deleted.) However, the operand of the
`scf.for` op is not updated because the `scf.for` op has not been
created yet; all we have is an `OperationState` object.
All parsers should be written in such a way that they first parse the
region and then resolve the operands. That way, no forward reference is
inserted in the first place. Before parsing the region, it may be
necessary to set the argument types if they are defined as part of the
assembly format of the op (as is the case with `scf.for`). Note: Ops in
generic format are parsed in the same way.
To make the parsing infrastructure more robust, this commit also delays
the erase of forward references until the end of the lifetime of the
parser. Instead of a use-after-free crash, users will then see more
descriptive error messages such as:
```
error: operation's operand is unlinked
```
Note: The proper way to fix the parser is to first parse the region,
then resolve the operands. The change to `Parser.cpp` is merely to help
users finding the root cause of the problem.
Commit: 2d6330f83a64a414f83d647bba7f23928f66aa5c
https://github.com/llvm/llvm-project/commit/2d6330f83a64a414f83d647bba7f23928f66aa5c
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Fix indent for deref assume bundle note added in 65640c1d4c.
Fixes odd whitespace rendering.
Commit: 507e413a2d85fb25f70caa9ef843f7c7cffb94c6
https://github.com/llvm/llvm-project/commit/507e413a2d85fb25f70caa9ef843f7c7cffb94c6
Author: Ming-Yi Lai <ming-yi.lai at mediatek.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M libunwind/src/CMakeLists.txt
M libunwind/src/Registers.hpp
M libunwind/src/UnwindCursor.hpp
M libunwind/src/UnwindLevel1.c
R libunwind/src/cet_unwind.h
A libunwind/src/shadow_stack_unwind.h
Log Message:
-----------
[libunwind][NFC] Remove the CET keyword in shadow stack-related stuffs (#126663)
libunwind currently supports shadow stack based on the Intel CET and
AArch64 GCS technology, but throughout related codes, the Intel-specific
keyword, "CET", is used to refer to the generic concept of control-flow
integrity/shadow stack. This patch replaces such wordings with
architecture-neutral term "shadow stack" (abbr. "shstk") to allow future
implementation to avoid using the Intel-specific "CET" term.
Commit: 44dc5729b07890cbedae6b1bdb6fcef038021ebc
https://github.com/llvm/llvm-project/commit/44dc5729b07890cbedae6b1bdb6fcef038021ebc
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/libunwind/src/BUILD.gn
Log Message:
-----------
[gn build] Port 507e413a2d85
Commit: 611a648327e9f6dad174e5c4427b27b8b7830fc0
https://github.com/llvm/llvm-project/commit/611a648327e9f6dad174e5c4427b27b8b7830fc0
Author: Diana Picus <Diana-Magda.Picus at amd.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
Log Message:
-----------
[AMDGPU] Add llvm.amdgcn.dead intrinsic (#123190)
Shaders that use the llvm.amdgcn.init.whole.wave intrinsic need to
explicitly preserve the inactive lanes of VGPRs of interest by adding
them as dummy arguments. The code usually looks something like this:
```
define amdgcn_cs_chain void f(active vgpr args..., i32 %inactive.vgpr1, ..., i32 %inactive.vgprN) {
entry:
%c = call i1 @llvm.amdgcn.init.whole.wave()
br i1 %c, label %shader, label %tail
shader:
[...]
tail:
%inactive.vgpr.arg1 = phi i32 [ %inactive.vgpr1, %entry], [poison, %shader]
[...]
; %inactive.vgpr* then get passed into a llvm.amdgcn.cs.chain call
```
Unfortunately, this kind of phi node will get optimized away and the
backend won't be able to figure out that it's ok to use the active lanes
of `%inactive.vgpr*` inside `shader`.
This patch fixes the issue by introducing a llvm.amdgcn.dead intrinsic,
whose result can be used as a PHI operand instead of the poison. This
will be selected to an IMPLICIT_DEF, which the backend can work with.
At the moment, the llvm.amdgcn.dead intrinsic works only on i32 values.
Support for other types can be added later if needed.
Commit: 3df03db689f1072d04a815a8893c395010988c53
https://github.com/llvm/llvm-project/commit/3df03db689f1072d04a815a8893c395010988c53
Author: Narayan <32898329+vortex73 at users.noreply.github.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/include/llvm/CGData/CodeGenData.h
M llvm/lib/CGData/CodeGenData.cpp
Log Message:
-----------
[CodeGen] Refactor `warn()` to use StringRef (NFCI) (#127537)
closes #100064
Commit: 079115e6eac0412214104b593849ee805d8921ce
https://github.com/llvm/llvm-project/commit/079115e6eac0412214104b593849ee805d8921ce
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
A libclc/clc/include/clc/math/clc_modf.h
A libclc/clc/include/clc/math/unary_decl_with_ptr.inc
A libclc/clc/include/clc/math/unary_def_with_ptr.inc
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/math/clc_modf.cl
A libclc/clc/lib/generic/math/clc_modf.inc
M libclc/generic/include/clc/math/modf.h
R libclc/generic/include/clc/math/modf.inc
M libclc/generic/lib/math/modf.cl
R libclc/generic/lib/math/modf.inc
Log Message:
-----------
[libclc] Move modf to the CLC library (#127828)
The "generic" unary_(def|decl)_with_ptr files are intended to be re-used
by the sincos and fract builtins in the future as they share an
identical type signature.
Commit: 684ad25dfc487476132b429dc92fca934460a8e3
https://github.com/llvm/llvm-project/commit/684ad25dfc487476132b429dc92fca934460a8e3
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
A libclc/clc/include/clc/math/clc_frexp.h
A libclc/clc/include/clc/math/unary_decl_with_int_ptr.inc
A libclc/clc/include/clc/math/unary_def_with_int_ptr.inc
M libclc/clc/include/clc/relational/clc_select.h
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/math/clc_frexp.cl
A libclc/clc/lib/generic/math/clc_frexp.inc
M libclc/generic/lib/math/frexp.cl
R libclc/generic/lib/math/frexp.inc
Log Message:
-----------
[libclc] Move frexp to CLC library; optimize half vecs (#127836)
This commit moves the frexp builtin to the CLC library.
It simultaneously optimizes the code generated for half vectors, which
was previously scalarizing and casting up to float. With this commit it
still casts up to float, but keeps it in the vector form.
Commit: 0cd5a1f3090beee88d34d22c6733c6df473877db
https://github.com/llvm/llvm-project/commit/0cd5a1f3090beee88d34d22c6733c6df473877db
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M clang/lib/AST/APValue.cpp
M clang/lib/Sema/SemaInit.cpp
Log Message:
-----------
[NFC][clang] Cleanup in APValue and SemaInit (#127790)
APValue:
Additional assignment of AllowConstexprUnknown is not required since it
will be handled by copy constructor called above.
SemaInit:
Remove unnecessary null check. DestRecordDecl can't be null due to being
obtained using `cast` and assertion that DestRecordType is present.
Spotted by a static analysis tool.
Commit: 62d77fcb3cebe80b3cf88588b5f94778799e86f3
https://github.com/llvm/llvm-project/commit/62d77fcb3cebe80b3cf88588b5f94778799e86f3
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
Log Message:
-----------
[X86] combineX86ShuffleChain - don't combine to VPERM2W/VPERM2B from just any single variable mask (#127914)
Despite them being more expensive than other variable mask shuffles, we
were combining shuffle chains to VPERM2W/VPERM2B if any shuffle in the
chain was a variable shuffle - including very cheap shuffles like PSHUFB
or AND mask patterns.
This patch adjusts the BWI VPERMV3 threshold - it still always permits
the merge if the chain (of 2 or more shuffles) contains any
X86ISD::VPERMV/VPERMV3 shuffles (including DQ variants), but otherwise
only reduces the depth threshold based off the number of other variable
shuffles we'd fold away.
Commit: 2c022e3617ec9bab3c9ab17464610843563ed9ed
https://github.com/llvm/llvm-project/commit/2c022e3617ec9bab3c9ab17464610843563ed9ed
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M lldb/include/lldb/Symbol/LineTable.h
M lldb/source/Symbol/LineTable.cpp
M lldb/unittests/Symbol/LineTableTest.cpp
Log Message:
-----------
[lldb] Replace LineTable::upper_bound with GetLineEntryIndexRange (#127806)
After (too) much deliberation, I came to the conclusion that this isn't
the right abstraction, as it doesn't behave completely like the standard
upper_bound method. What I really wanted was to get the range of line
entries for a given address range -- so I implement just that.
lower_bound is still useful as a primitive for building other kinds of
lookups.
Commit: e264317b45163f5c3ba7fc5375dcdecd827fce95
https://github.com/llvm/llvm-project/commit/e264317b45163f5c3ba7fc5375dcdecd827fce95
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M lldb/include/lldb/Utility/RangeMap.h
M lldb/test/Shell/Commands/command-disassemble.s
M lldb/unittests/Utility/RangeMapTest.cpp
Log Message:
-----------
[lldb] Fix RangeDataVector::CombineConsecutiveEntriesWithEqualData (#127059)
Function was merging equal data even if they weren't adjecant. This
caused a problem in command-disassemble.s test because the two ranges
describing the function would be merged and "swallow" the function
between them.
This PR copies/adapts the algorithm from
RangeVector::CombineConsecutiveEntries (which does not have the same
problem) and also adds a call to ComputeUpperBounds as moving entries
around invalidates the binary tree. (The lack of this call wasn't
noticed until now either because we were not calling methods which rely
on upper bounds (right now, it's only the ill-named FindEntryIndexes
method), or because we weren't merging anything.
Commit: 55fa2fa3480928d2ce6e06336842f673ac92f9d3
https://github.com/llvm/llvm-project/commit/55fa2fa3480928d2ce6e06336842f673ac92f9d3
Author: Dmitry Sidorov <dmitry.sidorov at intel.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/docs/SPIRVUsage.rst
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bindless_images/bindless_images_generic.ll
Log Message:
-----------
[SPIR-V] Add SPV_INTEL_bindless_images extension (#127737)
Adds instructions to convert convert unsigned integer handles to images,
samplers and sampled images.
Spec:
https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_bindless_images.asciidoc
---------
Signed-off-by: Sidorov, Dmitry <dmitry.sidorov at intel.com>
Commit: 44feae869570201e9920c26b151ce7ce24f0418d
https://github.com/llvm/llvm-project/commit/44feae869570201e9920c26b151ce7ce24f0418d
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
Log Message:
-----------
[RISCV][VLOPT] Mark some methods + arguments as const. NFC
Commit: a60675d22723d682ba66c769ccb2b42e0b825a04
https://github.com/llvm/llvm-project/commit/a60675d22723d682ba66c769ccb2b42e0b825a04
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
R clang/test/Analysis/builtin_signbit.cpp
A clang/test/CodeGen/builtin_signbit.cpp
Log Message:
-----------
[CodeGen][NFC] Move test builtin_signbit.cpp to CodeGen (#127814)
Because it is one of the three "misplaced" test files that appeared
under `/clang/test/Analysis` but were unrelated to the clang static
analyzer. For background see the following discourse thread:
https://discourse.llvm.org/t/taking-ownership-of-clang-test-analysis/84689/2
I placed this file in `clang/test/CodeGen` because as far as I see it
tests the code generated from `__builtin_signbit` (and there are many
other `builtin_*` test files in that directory); but I'm not familiar
with that area, so I'm not certain that it's the best place.
Commit: 6e047a5ab42698165a4746ef681396fab1698327
https://github.com/llvm/llvm-project/commit/6e047a5ab42698165a4746ef681396fab1698327
Author: Hans Wennborg <hans at hanshq.net>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/utils/release/build_llvm_release.bat
Log Message:
-----------
Add Wasm, RISC-V, BPF, and NVPTX targets back to Windows release packaging (#127794)
In #106059 we reduced the targets to those supported by Windows (X86 and
ARM) to avoid running into size limitations of the NSIS compiler.
Since then, people complained about the lack of Wasm [1], RISC-V [2],
BPF [3], and NVPTX [4]. These do seem to fit in the installer (at least
for 20.1.0-rc2), so let's add them back.
[1]
https://discourse.llvm.org/t/llvm-19-x-release-third-party-binaries/80374/26
[2]
https://discourse.llvm.org/t/llvm-19-x-release-third-party-binaries/80374/53
[3] https://github.com/llvm/llvm-project/issues/127120
[4]
https://github.com/llvm/llvm-project/pull/127794#issuecomment-2668677203
Commit: e09fc394b7c4606099b3466bb076a19327b9e16b
https://github.com/llvm/llvm-project/commit/e09fc394b7c4606099b3466bb076a19327b9e16b
Author: David <davidgmbb at gmail.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/include/llvm/Frontend/Driver/CodeGenOptions.h
M llvm/lib/Frontend/Driver/CodeGenOptions.cpp
Log Message:
-----------
[llvm] Make target triple in TLII const reference (#127718)
Commit: dc326d0b01f63e49f4f11c0c332369bf109721df
https://github.com/llvm/llvm-project/commit/dc326d0b01f63e49f4f11c0c332369bf109721df
Author: Sjoerd Meijer <smeijer at nvidia.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M clang/docs/UsersManual.rst
Log Message:
-----------
[Clang][doc] -ffp-contract options and standard compliance (#127621)
We had an discussion about -ffp-contract, how it compared to GCC which defaults
to fast, and standard compliance. Looking at our docs, most information is
there, but this clarifies when this option is and isn't standard compliant.
Commit: d595fc91aeb35cb7fad8ad37fa84a70863b09f69
https://github.com/llvm/llvm-project/commit/d595fc91aeb35cb7fad8ad37fa84a70863b09f69
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGen/X86/math-builtins.c
M clang/test/CodeGen/aix-builtin-mapping.c
M clang/test/CodeGen/builtin-attributes.c
M clang/test/CodeGen/math-builtins-long.c
M clang/test/CodeGen/math-libcalls.c
Log Message:
-----------
Revert "[clang] Lower modf builtin using `llvm.modf` intrinsic" (#127987)
Reverts llvm/llvm-project#126750
Revering while I investigate:
https://lab.llvm.org/buildbot/#/builders/72/builds/8406
Commit: 747588dc642b32210f918b6d5e3a31663167c382
https://github.com/llvm/llvm-project/commit/747588dc642b32210f918b6d5e3a31663167c382
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/PrivateReductionUtils.cpp
M flang/lib/Lower/OpenMP/PrivateReductionUtils.h
M flang/test/Lower/OpenMP/delayed-privatization-array.f90
M flang/test/Lower/OpenMP/different_vars_lastprivate_barrier.f90
Log Message:
-----------
[flang][Lower][OpenMP] Don't read moldarg for static sized array (#127838)
This should further reduce the number of spurious barriers
Commit: 97872409125bd9972ab7c74f1fe25539820f6631
https://github.com/llvm/llvm-project/commit/97872409125bd9972ab7c74f1fe25539820f6631
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
A llvm/test/CodeGen/RISCV/rvv/mask-exts-not.ll
Log Message:
-----------
[RISCV][test] Add tests for extending negated mask
Commit: 544a161c9a16283c3c1508bd5eec0f99d6614ac1
https://github.com/llvm/llvm-project/commit/544a161c9a16283c3c1508bd5eec0f99d6614ac1
Author: Dmitry Sidorov <dmitry.sidorov at intel.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
Log Message:
-----------
[NFC][SPIR-V] Remove unused variable (#127985)
Fix warning after https://github.com/llvm/llvm-project/pull/127737
Signed-off-by: Sidorov, Dmitry <dmitry.sidorov at intel.com>
Commit: 367ecc63338da1ff98d63a41bafc9b54d5c3eb6d
https://github.com/llvm/llvm-project/commit/367ecc63338da1ff98d63a41bafc9b54d5c3eb6d
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M lldb/include/lldb/Symbol/LineTable.h
M lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
M lldb/source/Plugins/SymbolFile/PDB/SymbolFilePDB.cpp
M lldb/source/Symbol/LineTable.cpp
M lldb/unittests/Symbol/LineTableTest.cpp
Log Message:
-----------
[lldb] Renaissance LineTable sequences (#127800)
LineSeqeunce is basically a vector, except that users aren't supposed to
know that. This implements the same concept in a slightly simpler
fashion.
Commit: d7784a649e80d346ba57ccc39f5e2a3e2f7e0a51
https://github.com/llvm/llvm-project/commit/d7784a649e80d346ba57ccc39f5e2a3e2f7e0a51
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Semantics/OpenMP/threadprivate02.f90
Log Message:
-----------
[flang][OpenMP] Catch threadprivate common block vars that appear in equivalence (#127642)
Semantics were not checking for variables appearing in equivalence
statements when those were part of a threadprivate common block.
Fixes #122825
Commit: 0948fc85aa99a8fd193d2d66a517e31b8b639f20
https://github.com/llvm/llvm-project/commit/0948fc85aa99a8fd193d2d66a517e31b8b639f20
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaAttr.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/CXX/drs/cwg0xx.cpp
M clang/test/CXX/drs/cwg4xx.cpp
M clang/test/CXX/temp/temp.arg/temp.arg.type/p2.cpp
M clang/test/SemaCXX/anonymous-struct.cpp
M clang/test/SemaCXX/bool-increment-SFINAE.cpp
M clang/test/SemaCXX/cxx98-compat-flags.cpp
M clang/test/SemaCXX/cxx98-compat.cpp
M clang/test/SemaCXX/deprecated.cpp
M clang/test/SemaCXX/lambda-expressions.cpp
M clang/test/SemaCXX/undefined-internal.cpp
M clang/test/SemaTemplate/recovery-crash.cpp
M clang/test/SemaTemplate/temp_arg_nontype.cpp
Log Message:
-----------
[clang] print correct context for diagnostics suppressed by deduction (#125453)
This patch makes it so the correct instantiation context is printed for
diagnostics suppessed by template argument deduction.
The context is saved along with the suppressed diagnostic, and when the
declaration they were attached to becomes used, we print the correct
context, instead of whatever context was at this point.
Commit: 66cf2a88a4cae8de25d7a36bce9dcc87a76010e2
https://github.com/llvm/llvm-project/commit/66cf2a88a4cae8de25d7a36bce9dcc87a76010e2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/sext-vsetcc.ll
Log Message:
-----------
[X86] sext-vsetcc.ll - regenerate VPTERNLOG comments
Commit: 92a3192a963c75bdd60874e273403340acc9c8fc
https://github.com/llvm/llvm-project/commit/92a3192a963c75bdd60874e273403340acc9c8fc
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-v192.ll
Log Message:
-----------
[X86] vector-shuffle-v192.ll - regenerate VPTERNLOG comments
Commit: 505d35aad3aa3989727fa7b49b7e8ced38071770
https://github.com/llvm/llvm-project/commit/505d35aad3aa3989727fa7b49b7e8ced38071770
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
Log Message:
-----------
[X86] getFauxShuffleMask - relax one use limit for insert_subvector concat splat pattern (#127981)
If we're splatting a subvector using a insert_subvector(insert_subvector(undef,sub,0),sub,c) pattern then permit multiuse of the sub as long as the insert_subvector nodes are the only users.
Commit: 9855d761f36f08a7d23e52c62cf1932e386669fc
https://github.com/llvm/llvm-project/commit/9855d761f36f08a7d23e52c62cf1932e386669fc
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
A llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.h
M llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir
Log Message:
-----------
[AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM (#125351)
Commit: 458b1e9d2c61945f62b5bdfda93914d6a46b6cc7
https://github.com/llvm/llvm-project/commit/458b1e9d2c61945f62b5bdfda93914d6a46b6cc7
Author: Bruno De Fraine <brunodf at synopsys.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CodeGenTBAA.cpp
M clang/lib/CodeGen/CodeGenTBAA.h
M clang/test/CXX/drs/cwg158.cpp
M clang/test/CodeGen/tbaa-pointers.c
Log Message:
-----------
[TBAA] Refine pointer-tbaa for void pointers by pointer depth (#126047)
Commit 77d3f8a avoids distinct tags for any pointers where the ultimate
pointee type is `void`, to solve breakage in real-world code that uses
(indirections to) `void*` for polymorphism over different pointer types.
While this matches the TBAA implementation in GCC, this patch implements
a refinement that distinguishes void pointers by pointer depth, as
described in the "strict aliasing" documentation included in the
aforementioned commit:
> `void*` is permitted to alias any pointer type, `void**` is permitted
> to alias any pointer to pointer type, and so on.
For example, `void**` is no longer considered to alias `int*` in this
refinement, but it remains possible to use `void**` for polymorphism
over pointers to pointers.
Commit: 54f14d96bb275a129321f9377987efcb43d773fa
https://github.com/llvm/llvm-project/commit/54f14d96bb275a129321f9377987efcb43d773fa
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/test/Transforms/FunctionAttrs/nocapture.ll
Log Message:
-----------
[FunctionAttrs] Add test for incorrect predicate in capture analysis (NFC)
Commit: 6361a8a1b763d6915636eb8cfaf64f2d8fe60a03
https://github.com/llvm/llvm-project/commit/6361a8a1b763d6915636eb8cfaf64f2d8fe60a03
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Analysis/CaptureTracking.cpp
M llvm/test/Transforms/FunctionAttrs/nocapture.ll
Log Message:
-----------
[CaptureTracking] Check for equality predicate for null comparisons
The logic here is not valid for non-equality comparisons. E.g.
using slt will leak the sign bit, regardless of whether the
pointer is dereferenceable.
This fix is split out from https://github.com/llvm/llvm-project/pull/125880.
Commit: f4f7c71c55da442dc18e872d3c5db760a9ad43ba
https://github.com/llvm/llvm-project/commit/f4f7c71c55da442dc18e872d3c5db760a9ad43ba
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
Log Message:
-----------
[RISCV][VLOPT] Move mayReadPastVL check into getMinimumVLForUser. NFC (#127972)
checkUsers currently does two things, a) work out the minimum VL read by
every user and b) check that the operand info of the MI and users match.
getMinimumVLForUser handles most of a), with the exception of the check
for instructions that read past VL e.g. vrgather which is still in
checkUsers.
This moves it into getMinimumVLForUser to keep all that logic in one
place and simplifies an upcoming patch.
Commit: 70ed381b1693697dec3efcaed161d3626d16cff1
https://github.com/llvm/llvm-project/commit/70ed381b1693697dec3efcaed161d3626d16cff1
Author: David Green <david.green at arm.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
Log Message:
-----------
[GlobalISel][AArch64] Fix fptoi.sat lowering. (#127901)
The SDAG version uses fminnum/fmaxnum, in converting it to fcmp+select
it appears the order of the operands was chosen badly. This switches the
conditions used to keep the constant on the RHS.
Commit: 58571c82ef93b32cd0ea757e23ec4ff83f8fc3c0
https://github.com/llvm/llvm-project/commit/58571c82ef93b32cd0ea757e23ec4ff83f8fc3c0
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M lldb/test/API/functionalities/dead-strip/TestDeadStrip.py
Log Message:
-----------
[lldb] Un-XFAIL TestDeadStrip.py on windows
I suspect it was fixed by #127059. aarch64 is the only windows bot we have now, so it's can't be certain it's fixed everywhere, but also I have no reason to believe otherwise.
Fixes #43774.
Commit: 0a8341fdb2f574019fb6cf99e207754e962dc81d
https://github.com/llvm/llvm-project/commit/0a8341fdb2f574019fb6cf99e207754e962dc81d
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/mask-exts-not.ll
Log Message:
-----------
[RISCV] Avoid VMNOT by swapping VMERGE operands for mask extensions (#126751)
Fold:
(select (not m), 1, 0) -> (select m, 0, 1)
(select (not m), -1, 0) -> (select m, 0, -1)
Commit: 0c809ea336143f6118339521cbebe9e182e7a5e5
https://github.com/llvm/llvm-project/commit/0c809ea336143f6118339521cbebe9e182e7a5e5
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
M llvm/test/CodeGen/Mips/readcyclecounter.ll
Log Message:
-----------
[Mips] Reserve hardware register HWR2 (#127775)
Fix pr https://github.com/llvm/llvm-project/pull/127553.
x86_64 failed to run readcyclecounter.ll when enable expensive_check,
it would error "Using an undefined physical register".
Commit: 12f8ed58a039ff3a3365591203f76ae07a179215
https://github.com/llvm/llvm-project/commit/12f8ed58a039ff3a3365591203f76ae07a179215
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/test/Lexer/cxx-features.cpp
M clang/www/cxx_status.html
Log Message:
-----------
[Clang] Mark P1061 (Structured Bindings can introduce a Pack) as implemented (#127980)
Implemented in abc8812df02599fc413d9ed77b992f8236ed2af9
Commit: 8feb5bac3279f7c7fbbdd741a70d8debd519aa00
https://github.com/llvm/llvm-project/commit/8feb5bac3279f7c7fbbdd741a70d8debd519aa00
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
R libcxx/test/benchmarks/algorithms/copy.bench.cpp
R libcxx/test/benchmarks/algorithms/copy_backward.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/copy.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/copy_backward.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/copy_if.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/copy_n.bench.cpp
Log Message:
-----------
[libc++] Add benchmarks for copy algorithms (#127328)
This patch adds benchmarks for the copy family of algorithms (copy,
copy_n, copy_if, copy_backward).
Commit: f00b32e2d0ee666d32f1ddd0c687e269fab95b44
https://github.com/llvm/llvm-project/commit/f00b32e2d0ee666d32f1ddd0c687e269fab95b44
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M libcxx/include/__locale_dir/locale_base_api.h
M libcxx/include/__locale_dir/support/bsd_like.h
M libcxx/include/__locale_dir/support/fuchsia.h
M libcxx/include/__locale_dir/support/no_locale/characters.h
M libcxx/include/__locale_dir/support/windows.h
A libcxx/test/libcxx/xopen_source.gen.py
Log Message:
-----------
[libc++] Reduce the dependency of the locale base API on the base system from the headers (#117764)
Many parts of the locale base API are only required when building the
shared/static library, but not from the headers. Document those
functions and carve out a few of those that don't work when
_XOPEN_SOURCE is defined to something old.
Fixes #117630
Commit: a03f064b60f0ccfe9bf31046bc944087ed2fad6c
https://github.com/llvm/llvm-project/commit/a03f064b60f0ccfe9bf31046bc944087ed2fad6c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
Log Message:
-----------
[X86] combineX86ShufflesRecursively - peek through one use bitcasts to find additional (free) extract_subvector nodes
Commit: 41cece8c86399dd1ffcb6b7a8b50c10083fe5a40
https://github.com/llvm/llvm-project/commit/41cece8c86399dd1ffcb6b7a8b50c10083fe5a40
Author: David Truby <david.truby at arm.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/CommonArgs.h
M clang/lib/Driver/ToolChains/Flang.cpp
M flang/include/flang/Frontend/CodeGenOptions.def
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Frontend/FrontendActions.cpp
M flang/test/Driver/optimization-remark.f90
M flang/test/Integration/unroll-loops.f90
M flang/test/Lower/HLFIR/unroll-loops.fir
Log Message:
-----------
[flang] Add -f[no-]vectorize flags (#119718)
This patch adds the -fvectorize and -fno-vectorize flags to flang.
Note that this also changes the behaviour of `flang -fc1` to match that
of `clang -cc1`, which is that vectorization is only enabled in the
presence of the `-vectorize-loops` flag.
Additionally, this patch changes the behaviour of the default
optimisation levels to match clang, such that vectorization only happens
at the same levels as it does there.
This patch is in draft while I write an RFC to discuss the above two
changes.
Commit: 1c4e9863fa1cba6d28be92026e0912808b01780d
https://github.com/llvm/llvm-project/commit/1c4e9863fa1cba6d28be92026e0912808b01780d
Author: Jonathan Peyton <jonathan.l.peyton at intel.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_global.cpp
M openmp/runtime/src/kmp_runtime.cpp
Log Message:
-----------
[OpenMP][NFC] Remove unused debug lock (#127928)
Commit: 24cd933d02b820f73c4ee6e4277ed1b6e95b570a
https://github.com/llvm/llvm-project/commit/24cd933d02b820f73c4ee6e4277ed1b6e95b570a
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/test/Transforms/MemCpyOpt/memcpy.ll
Log Message:
-----------
[MemCpyOpt] Add test for call slot opt with ret-only capture (NFC)
From: https://github.com/llvm/llvm-project/pull/125880#issuecomment-2671725079
Commit: 9ffab5637c803d1ff8aaf94972b9d40108d450c9
https://github.com/llvm/llvm-project/commit/9ffab5637c803d1ff8aaf94972b9d40108d450c9
Author: Viktoria Maximova <viktoria.maksimova at intel.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-type-struct.ll
Log Message:
-----------
[SPIR-V] Initial implementation of SPV_INTEL_long_composites (#126545)
This change introduces support of `OpTypeStructContinuedINTEL`
instruction.
Specification:
https://github.khronos.org/SPIRV-Registry/extensions/INTEL/SPV_INTEL_long_composites.html
Commit: 6eba2775e22fe812ebc2cbb73d71c1e989b9306c
https://github.com/llvm/llvm-project/commit/6eba2775e22fe812ebc2cbb73d71c1e989b9306c
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
Log Message:
-----------
[LAA] Scale strides using type-size (NFC) (#124529)
Change getDependenceDistanceStrideAndSize to scale strides by
TypeByteSize, scaling the returned CommonStride and MaxStride. Even
though there is a seemingly-functional change of setting CommonStride
when scaled strides are equal, it ends up being a non-functional change
due to aggressive HasSameSize checking.
Commit: ae5785460dfdee82b9b3fe08fb5f2da73c91cec0
https://github.com/llvm/llvm-project/commit/ae5785460dfdee82b9b3fe08fb5f2da73c91cec0
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M libclc/clc/include/clc/integer/gentype.inc
M libclc/clc/include/clc/math/gentype.inc
M libclc/clc/include/clc/relational/clc_select_decl.inc
M libclc/clc/include/clc/relational/clc_select_impl.inc
M libclc/clc/lib/generic/integer/clc_rotate.inc
M libclc/clc/lib/generic/math/clc_frexp.inc
M libclc/clspv/lib/shared/vstore_half.inc
M libclc/generic/include/clc/math/nan.h
M libclc/generic/include/clc/math/nan.inc
M libclc/generic/include/clc/relational/select.h
M libclc/generic/lib/math/maxmag.inc
M libclc/generic/lib/math/nan.cl
M libclc/generic/lib/math/nan.inc
M libclc/generic/lib/shared/vload_half.inc
M libclc/generic/lib/shared/vstore_half.inc
Log Message:
-----------
[libclc] Define macros for users of gentype.inc (#128012)
Several users of (mostly math/) gentype.inc rely on types other than the
'gentype'. This is commonly intN as several maths builtins expose this
as a return or paramter type. We were previously explicitly defining
this type for every gentype.
Other implementations rely on integer types of the same size and element
width as the gentype, such as short/ushort for half, long/ulong for
double, etc.
Users might also rely on as_type or convert_type builtins to/from these
types.
The previous method we used to define intN was unscalable if we wanted
to expose more types and helpers.
This commit introduces a simpler system whereby several macros are
defined at the beginning of gentype.inc. These rely on concatenating
with the vector size. To facilitate this system, scalar gentypes now
define an empty vector size. It was previously undefined, which was
dangerous. An added benefit is that it matches how the integer
gentype.inc vector size has been working.
These macros will be especially helpful for the definitions of
logb/ilogb in an upcoming patch.
Commit: 3b9f9645e017a9160bf78ec1630420e181c7bd90
https://github.com/llvm/llvm-project/commit/3b9f9645e017a9160bf78ec1630420e181c7bd90
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/PowerPC/large-loop-rdx.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll
Log Message:
-----------
[LV] Regen a couple of tests with UTC (#127785)
Commit: 04b5c63ddfe9e7091b600ea8d768659705082697
https://github.com/llvm/llvm-project/commit/04b5c63ddfe9e7091b600ea8d768659705082697
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
Log Message:
-----------
[LV] Add inbounds to interleave test.
In preparation for https://github.com/llvm/llvm-project/pull/127543
Commit: 43f2968a028fbc6b4fac5ba6d18ad9d27eb4ef76
https://github.com/llvm/llvm-project/commit/43f2968a028fbc6b4fac5ba6d18ad9d27eb4ef76
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
Log Message:
-----------
[RISCV] Recognize VLA shift pairs from shuffle masks (#127710)
If we have a shuffle mask which can be represented as two slides + some
conditional masking, we can emit a VLA sequence which is at most
O(2*LMUL). This is essentially a generalization of the existing
isElementRotate, but is staged to only introduce the new match for the
moment. A follow up change will start consolidating code - see the notes
below.
A couple of notes:
1) I'm excluding bit rotates mostly to keep the diffs manageable.
2) The existing isElementRotate logic is nearly redundant after this
change. However, we have some intersection between the bit rotate
and element rotate matching. To keep things simple, I left that in
place for now, and will merge/cleanup in a separate change.
3) The individual asVSlideup and asVSlidedown are closely related, but
the former looks through extracts and the later changes VL. I'm leaving
these in place for now, but hope to common them up a bit as well.
Commit: 1b78ff6972789d189fe0b403b403626328bf6a65
https://github.com/llvm/llvm-project/commit/1b78ff6972789d189fe0b403b403626328bf6a65
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
M llvm/test/Transforms/InstCombine/store.ll
A llvm/test/Transforms/PhaseOrdering/load-store-sameval.ll
Log Message:
-----------
[InstCombine] Simplify the pointer operand of store if writing to null is UB (#127979)
Proof: https://alive2.llvm.org/ce/z/mzVj-u
I will add some follow-up patches to avoid duplicate code, support more
memory instructions, and bypass gep instructions.
Commit: 1b610e69d9621e00714b126e646bebb912b1e9a1
https://github.com/llvm/llvm-project/commit/1b610e69d9621e00714b126e646bebb912b1e9a1
Author: William Moses <gh at wsmoses.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Math/IR/MathOps.td
M mlir/lib/Dialect/Math/IR/MathOps.cpp
M mlir/test/Dialect/Math/canonicalize.mlir
Log Message:
-----------
[MLIR][Math] Add floating point value folders (#127947)
Commit: c2e51428bf86def5094a3f14029f75f3ac0e477e
https://github.com/llvm/llvm-project/commit/c2e51428bf86def5094a3f14029f75f3ac0e477e
Author: William Moses <gh at wsmoses.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/test/Dialect/LLVMIR/canonicalize.mlir
Log Message:
-----------
[MLIR][LLVM] Fold extract of constant (#127927)
Co-authored-by: Christian Ulmann <christianulmann at gmail.com>
Commit: 404af37175a5a1f2755fb5707487b39e83b1929d
https://github.com/llvm/llvm-project/commit/404af37175a5a1f2755fb5707487b39e83b1929d
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanHCFGBuilder.cpp
A llvm/test/Transforms/LoopVectorize/loop-with-constant-exit-condition.ll
Log Message:
-----------
[VPlan] Remove stale assertion in HCFG builder.
The assertion was left over from a time when VPBBs still had an
associated condition bit. This is not the case any more (comment was
stale). In case a branch on condition is needed, a BranchOnCond
VPInstruction is added when constructing recipes. That's also where it
is checked if the condition is available.
Exposed by 38376dee9.
Commit: 60c620272db2b3cb71b973c9ae45a639aa492164
https://github.com/llvm/llvm-project/commit/60c620272db2b3cb71b973c9ae45a639aa492164
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/include/llvm/ADT/SetOperations.h
M llvm/unittests/ADT/SetOperationsTest.cpp
Log Message:
-----------
[ADT] Add set_intersects to check if there is any intersection (#127907)
Add a facility to check if there is any intersection between 2 sets.
This will be used in some follow on changes to MemProf.
Commit: a72616de18c0814ad37b5748d6bdc60b825dd889
https://github.com/llvm/llvm-project/commit/a72616de18c0814ad37b5748d6bdc60b825dd889
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M mlir/docs/Dialects/Linalg/_index.md
M mlir/python/mlir/dialects/LinalgOps.td
M mlir/python/mlir/dialects/linalg/__init__.py
M mlir/test/python/dialects/linalg/ops.py
Log Message:
-----------
[mlir][python] fix linalg.pack/unpack (#127729)
This PR https://github.com/llvm/llvm-project/pull/123902 broke python
bindings for `tensor.pack`/`unpack`. This PR fixes that. It also
1. adds convenience wrappers for pack/unpack
2. cleans up matmul-like ops in the linalg bindings
3. fixes linalg docs missing pack/unpack
Commit: 81ed48531d51754fe4aac7a149ee4534a9ffda1b
https://github.com/llvm/llvm-project/commit/81ed48531d51754fe4aac7a149ee4534a9ffda1b
Author: Petr Hosek <phosek at google.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M clang/utils/perf-training/CMakeLists.txt
Log Message:
-----------
[CMake] Fix variable name (#127967)
This was accidentaly introduced in #126876.
Commit: c48e0c182c5a9e19062677cbca17c89ea586e033
https://github.com/llvm/llvm-project/commit/c48e0c182c5a9e19062677cbca17c89ea586e033
Author: kper <kevin.per at protonmail.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
M lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
A lldb/test/API/functionalities/gdb_remote_client/basic_eh_frame-riscv64.yaml
M lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
A lldb/test/Shell/Register/Inputs/riscv64-gp-read.cpp
A lldb/test/Shell/Register/riscv64-gp-read.test
M llvm/utils/lit/lit/llvm/config.py
Log Message:
-----------
[lldb][RISC-V] Extended if conditions to support alias names for registers (#124475)
Extending the conditionals in `AugmentRegisterInfo` to support
alternative names for lldb.
Fixes #124023
There is an exception with register `X8` which is not covered here but
more details can be found in the issue
https://github.com/llvm/llvm-project/issues/127900.
Commit: 81bc28d0bcaca3e7386ced2138566e4d0a838ad5
https://github.com/llvm/llvm-project/commit/81bc28d0bcaca3e7386ced2138566e4d0a838ad5
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
A lldb/test/API/macosx/thread_start_bps/Makefile
A lldb/test/API/macosx/thread_start_bps/TestBreakpointsThreadInit.py
A lldb/test/API/macosx/thread_start_bps/main.c
Log Message:
-----------
[lldb] Update PlatformDarwin list of libraries with thread functions (#127922)
Recent versions of the system changed where these functions live.
Commit: 609732cc2e6572b25ce195cc009e2b4bae42dcda
https://github.com/llvm/llvm-project/commit/609732cc2e6572b25ce195cc009e2b4bae42dcda
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Fix warnings
This patch fixes:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp:5723:24: error: captured
structured bindings are a C++20 extension
[-Werror,-Wc++20-extensions]
llvm/lib/Target/RISCV/RISCVISelLowering.cpp:5728:76: error: captured
structured bindings are a C++20 extension
[-Werror,-Wc++20-extensions]
Commit: ff99af7ea03b3be46bec7203bd2b74048d29a52a
https://github.com/llvm/llvm-project/commit/ff99af7ea03b3be46bec7203bd2b74048d29a52a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/RDFRegisters.h
M llvm/include/llvm/CodeGen/Register.h
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/LiveInterval.cpp
M llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
M llvm/lib/CodeGen/MachineTraceMetrics.cpp
M llvm/lib/CodeGen/RegisterPressure.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/ARC/ARCOptAddrMode.cpp
M llvm/lib/Target/ARM/A15SDOptimizer.cpp
M llvm/lib/Target/ARM/ARMLatencyMutations.cpp
M llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
M llvm/lib/Target/Hexagon/HexagonCopyHoisting.cpp
M llvm/lib/Target/M68k/M68kISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
M llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
M llvm/lib/Target/PowerPC/PPCVSXCopy.cpp
M llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
Log Message:
-----------
[CodeGen] Remove static member function Register::isVirtualRegister. NFC (#127968)
Use nonstatic member instead. This requires explicit conversions, but
many will go away as we continue converting unsigned to Register.
In a few places where it was simple, I changed unsigned to Register.
Commit: 1e1bf7971b1b8c74aa4de2c055c402d0085e87b8
https://github.com/llvm/llvm-project/commit/1e1bf7971b1b8c74aa4de2c055c402d0085e87b8
Author: Andrey Timonin <timonina1909 at gmail.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/test/Dialect/EmitC/invalid_ops.mlir
M mlir/test/Dialect/EmitC/ops.mlir
Log Message:
-----------
[mlir][emitc] Add an option to cast array type to ptr type (#126385)
Commit: e83ad816992838781c70d0af895100a5c78268d1
https://github.com/llvm/llvm-project/commit/e83ad816992838781c70d0af895100a5c78268d1
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M libcxx/src/experimental/tzdb.cpp
Log Message:
-----------
[NFC][libc++][TZDB] Fixes formatting.
This was broken by #127339
Commit: c0c172213b6124a672ee64786260f8860027413f
https://github.com/llvm/llvm-project/commit/c0c172213b6124a672ee64786260f8860027413f
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
Log Message:
-----------
[Analysis] Avoid repeated hash lookups (NFC) (#127955)
Commit: 506b31ec36746732b84fb0e9cd74af3ca885fa86
https://github.com/llvm/llvm-project/commit/506b31ec36746732b84fb0e9cd74af3ca885fa86
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Transforms/IPO/PartialInlining.cpp
Log Message:
-----------
[IPO] Avoid repeated hash lookups (NFC) (#127957)
Commit: c612f7961219adfad617a05b3d5f07bb05d52df3
https://github.com/llvm/llvm-project/commit/c612f7961219adfad617a05b3d5f07bb05d52df3
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/ObjectYAML/XCOFFEmitter.cpp
Log Message:
-----------
[ObjectYAML] Avoid repeated hash lookups (NFC) (#127958)
Commit: 4a8f41456515953cb8a5f9f1b927c9f60436f56a
https://github.com/llvm/llvm-project/commit/4a8f41456515953cb8a5f9f1b927c9f60436f56a
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Utils/AssumeBundleBuilder.cpp
Log Message:
-----------
[Utils] Avoid repeated hash lookups (NFC) (#127959)
Commit: be51ef4518ad3375e267667a89d379ce46efc4bb
https://github.com/llvm/llvm-project/commit/be51ef4518ad3375e267667a89d379ce46efc4bb
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblySortRegion.cpp
Log Message:
-----------
[WebAssembly] Avoid repeated hash lookups (NFC) (#127960)
Commit: 02e8fd7a30903d65c85b3cfb56e8039b71c31972
https://github.com/llvm/llvm-project/commit/02e8fd7a30903d65c85b3cfb56e8039b71c31972
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/AST/RecordLayoutBuilder.cpp
M clang/lib/Basic/TargetInfo.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/test/CodeGen/aapcs-align.cpp
M clang/test/CodeGen/aapcs64-align.cpp
M clang/test/CodeGenCXX/debug-info-structured-binding-bitfield.cpp
Log Message:
-----------
[ARM,AArch64] Fix ABI bugs with over-sized bitfields (#126774)
This fixes two bugs in the ABI for over-sized bitfields for ARM and
AArch64:
The container type picked for an over-sized bitfield already contributes
to the alignment of the structure, but it should also contribute to the
"unadjusted alignment" which is used by the ARM and AArch64 PCS.
AAPCS64 defines the bitfield layout algorithm for over-sized bitfields
as picking a container which is the fundamental integer data type with
the largest size less than or equal to the bit-field width. Since
AAPCS64 has a 128-bit integer fundamental data type, we need to consider
Int128 as a container type for AArch64.
Commit: 726c4b9f77862d83b6e5e16c8d5a2fc4fb1589a2
https://github.com/llvm/llvm-project/commit/726c4b9f77862d83b6e5e16c8d5a2fc4fb1589a2
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Semantics/tools.h
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
M flang/module/cudadevice.f90
M flang/test/Lower/CUDA/cuda-device-proc.cuf
Log Message:
-----------
[flang][cuda] Lower match_all_sync functions to nvvm intrinsics (#127940)
Commit: f7a10f0e8d46085cfebfbd53c3ab19a5ab37774f
https://github.com/llvm/llvm-project/commit/f7a10f0e8d46085cfebfbd53c3ab19a5ab37774f
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M clang/test/Index/comment-to-html-xml-conversion.cpp
Log Message:
-----------
[Index] Un-XFAIL test with msan
Passing after #127078.
Commit: d09e52bc4df65ac734aab74af1156be403743e09
https://github.com/llvm/llvm-project/commit/d09e52bc4df65ac734aab74af1156be403743e09
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M .github/workflows/release-binaries.yml
M bolt/lib/RuntimeLibs/InstrumentationRuntimeLibrary.cpp
M clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.cpp
M clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.h
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/clangd/unittests/SymbolCollectorTests.cpp
M clang-tools-extra/clangd/unittests/XRefsTests.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/const-correctness.rst
A clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-allowed-types.cpp
M clang/cmake/caches/Release.cmake
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/UsersManual.rst
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsNVPTX.td
M clang/include/clang/Basic/Cuda.h
M clang/include/clang/Basic/TargetInfo.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
A clang/include/clang/CIR/TypeEvaluationKind.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Sema/Sema.h
M clang/include/module.modulemap
M clang/lib/AST/APValue.cpp
M clang/lib/AST/RecordLayoutBuilder.cpp
M clang/lib/Basic/Cuda.cpp
M clang/lib/Basic/TargetInfo.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/NVPTX.cpp
A clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
A clang/lib/CIR/CodeGen/CIRGenFunction.cpp
A clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
A clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.h
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CodeGen/CGVTables.cpp
M clang/lib/CodeGen/CodeGenTBAA.cpp
M clang/lib/CodeGen/CodeGenTBAA.h
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/CommonArgs.h
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/lib/Headers/gpuintrin.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Headers/nvptxintrin.h
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaAttr.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefMemberChecker.cpp
A clang/test/Analysis/Checkers/WebKit/unchecked-members-objc.mm
A clang/test/Analysis/Checkers/WebKit/uncounted-members-objc.mm
R clang/test/Analysis/builtin_signbit.cpp
M clang/test/CIR/emit-actions.cpp
A clang/test/CIR/func-simple.cpp
M clang/test/CIR/global-var-simple.cpp
R clang/test/CIR/hello.c
M clang/test/CXX/drs/cwg0xx.cpp
M clang/test/CXX/drs/cwg158.cpp
M clang/test/CXX/drs/cwg4xx.cpp
M clang/test/CXX/temp/temp.arg/temp.arg.type/p2.cpp
M clang/test/CodeGen/X86/math-builtins.c
M clang/test/CodeGen/aapcs-align.cpp
M clang/test/CodeGen/aapcs64-align.cpp
M clang/test/CodeGen/aix-builtin-mapping.c
M clang/test/CodeGen/builtin-attributes.c
A clang/test/CodeGen/builtin_signbit.cpp
M clang/test/CodeGen/math-builtins-long.c
M clang/test/CodeGen/math-libcalls.c
M clang/test/CodeGen/tbaa-pointers.c
A clang/test/CodeGenCUDA/increment-index-for-thunks.cu
M clang/test/CodeGenCXX/debug-info-structured-binding-bitfield.cpp
A clang/test/CodeGenHLSL/builtins/and.hlsl
M clang/test/Index/comment-to-html-xml-conversion.cpp
M clang/test/Lexer/cxx-features.cpp
M clang/test/Misc/target-invalid-cpu-note/nvptx.c
M clang/test/SemaCXX/anonymous-struct.cpp
M clang/test/SemaCXX/bool-increment-SFINAE.cpp
M clang/test/SemaCXX/cxx98-compat-flags.cpp
M clang/test/SemaCXX/cxx98-compat.cpp
M clang/test/SemaCXX/deprecated.cpp
M clang/test/SemaCXX/lambda-expressions.cpp
M clang/test/SemaCXX/undefined-internal.cpp
A clang/test/SemaHLSL/BuiltIns/and-errors.hlsl
M clang/test/SemaTemplate/recovery-crash.cpp
M clang/test/SemaTemplate/temp_arg_nontype.cpp
M clang/tools/libclang/CXString.cpp
M clang/utils/perf-training/CMakeLists.txt
M clang/utils/perf-training/lit.cfg
M clang/utils/perf-training/lit.site.cfg.in
M clang/www/cxx_status.html
M flang/include/flang/Frontend/CodeGenOptions.def
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Semantics/tools.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/PrivateReductionUtils.cpp
M flang/lib/Lower/OpenMP/PrivateReductionUtils.h
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/module/cudadevice.f90
M flang/test/Driver/optimization-remark.f90
M flang/test/Integration/unroll-loops.f90
M flang/test/Lower/CUDA/cuda-device-proc.cuf
M flang/test/Lower/HLFIR/unroll-loops.fir
M flang/test/Lower/OpenMP/delayed-privatization-array.f90
M flang/test/Lower/OpenMP/different_vars_lastprivate_barrier.f90
M flang/test/Semantics/OpenMP/threadprivate02.f90
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/unistd.yaml
M libc/src/unistd/CMakeLists.txt
A libc/src/unistd/getsid.h
M libc/src/unistd/linux/CMakeLists.txt
A libc/src/unistd/linux/getsid.cpp
M libc/test/integration/src/__support/GPU/scan_reduce.cpp
M libc/test/src/unistd/CMakeLists.txt
A libc/test/src/unistd/getsid_test.cpp
M libc/utils/hdrgen/header.py
M libc/utils/hdrgen/main.py
A libc/utils/hdrgen/tests/expected_output/test_small.json
M libc/utils/hdrgen/tests/test_integration.py
M libclc/clc/include/clc/integer/gentype.inc
A libclc/clc/include/clc/math/clc_frexp.h
A libclc/clc/include/clc/math/clc_modf.h
M libclc/clc/include/clc/math/gentype.inc
A libclc/clc/include/clc/math/unary_decl_with_int_ptr.inc
A libclc/clc/include/clc/math/unary_decl_with_ptr.inc
A libclc/clc/include/clc/math/unary_def_with_int_ptr.inc
A libclc/clc/include/clc/math/unary_def_with_ptr.inc
M libclc/clc/include/clc/relational/clc_select.h
M libclc/clc/include/clc/relational/clc_select_decl.inc
M libclc/clc/include/clc/relational/clc_select_impl.inc
M libclc/clc/lib/generic/SOURCES
M libclc/clc/lib/generic/integer/clc_rotate.inc
A libclc/clc/lib/generic/math/clc_frexp.cl
A libclc/clc/lib/generic/math/clc_frexp.inc
A libclc/clc/lib/generic/math/clc_modf.cl
A libclc/clc/lib/generic/math/clc_modf.inc
M libclc/clspv/lib/shared/vstore_half.inc
M libclc/generic/include/clc/math/modf.h
R libclc/generic/include/clc/math/modf.inc
M libclc/generic/include/clc/math/nan.h
M libclc/generic/include/clc/math/nan.inc
M libclc/generic/include/clc/relational/select.h
M libclc/generic/lib/math/frexp.cl
R libclc/generic/lib/math/frexp.inc
M libclc/generic/lib/math/maxmag.inc
M libclc/generic/lib/math/modf.cl
R libclc/generic/lib/math/modf.inc
M libclc/generic/lib/math/nan.cl
M libclc/generic/lib/math/nan.inc
M libclc/generic/lib/shared/vload_half.inc
M libclc/generic/lib/shared/vstore_half.inc
M libcxx/include/__locale_dir/locale_base_api.h
M libcxx/include/__locale_dir/support/bsd_like.h
M libcxx/include/__locale_dir/support/fuchsia.h
M libcxx/include/__locale_dir/support/no_locale/characters.h
M libcxx/include/__locale_dir/support/windows.h
M libcxx/src/experimental/tzdb.cpp
R libcxx/test/benchmarks/algorithms/copy.bench.cpp
R libcxx/test/benchmarks/algorithms/copy_backward.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/copy.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/copy_backward.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/copy_if.bench.cpp
A libcxx/test/benchmarks/algorithms/modifying/copy_n.bench.cpp
A libcxx/test/libcxx/xopen_source.gen.py
M libcxx/test/std/utilities/template.bitset/bitset_test_cases.h
M libunwind/src/CMakeLists.txt
M libunwind/src/Registers.hpp
M libunwind/src/UnwindCursor.hpp
M libunwind/src/UnwindLevel1.c
R libunwind/src/cet_unwind.h
A libunwind/src/shadow_stack_unwind.h
M lldb/include/lldb/API/SBCommandReturnObject.h
M lldb/include/lldb/API/SBValue.h
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/IOHandler.h
M lldb/include/lldb/Host/Editline.h
M lldb/include/lldb/Host/File.h
M lldb/include/lldb/Host/StreamFile.h
M lldb/include/lldb/Interpreter/CommandReturnObject.h
M lldb/include/lldb/Interpreter/ScriptInterpreter.h
M lldb/include/lldb/Symbol/LineTable.h
M lldb/include/lldb/Utility/RangeMap.h
M lldb/include/lldb/ValueObject/ValueObjectList.h
M lldb/include/lldb/lldb-forward.h
M lldb/source/API/SBCommandReturnObject.cpp
M lldb/source/Commands/CommandObjectBreakpointCommand.cpp
M lldb/source/Commands/CommandObjectCommands.cpp
M lldb/source/Commands/CommandObjectDWIMPrint.cpp
M lldb/source/Commands/CommandObjectExpression.cpp
M lldb/source/Commands/CommandObjectFrame.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Commands/CommandObjectType.cpp
M lldb/source/Commands/CommandObjectWatchpointCommand.cpp
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/IOHandler.cpp
M lldb/source/Core/IOHandlerCursesGUI.cpp
M lldb/source/Expression/REPL.cpp
M lldb/source/Host/common/Editline.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Interpreter/ScriptInterpreter.cpp
M lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
M lldb/source/Plugins/SymbolFile/PDB/SymbolFilePDB.cpp
M lldb/source/Symbol/LineTable.cpp
M lldb/source/ValueObject/ValueObjectList.cpp
M lldb/test/API/api/command-return-object/TestSBCommandReturnObject.py
M lldb/test/API/commands/frame/var/TestFrameVar.py
M lldb/test/API/functionalities/dead-strip/TestDeadStrip.py
M lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
A lldb/test/API/functionalities/gdb_remote_client/basic_eh_frame-riscv64.yaml
M lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
M lldb/test/API/functionalities/target_var/TestTargetVar.py
A lldb/test/API/macosx/thread_start_bps/Makefile
A lldb/test/API/macosx/thread_start_bps/TestBreakpointsThreadInit.py
A lldb/test/API/macosx/thread_start_bps/main.c
M lldb/test/Shell/Commands/command-disassemble.s
A lldb/test/Shell/Register/Inputs/riscv64-gp-read.cpp
A lldb/test/Shell/Register/riscv64-gp-read.test
M lldb/unittests/Editline/EditlineTest.cpp
M lldb/unittests/Symbol/LineTableTest.cpp
M lldb/unittests/Utility/RangeMapTest.cpp
M llvm/docs/LangRef.rst
M llvm/docs/SPIRVUsage.rst
M llvm/include/llvm/ADT/SetOperations.h
M llvm/include/llvm/Analysis/GlobalsModRef.h
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/include/llvm/CGData/CodeGenData.h
M llvm/include/llvm/CodeGen/RDFRegisters.h
A llvm/include/llvm/CodeGen/RegAllocPriorityAdvisor.h
M llvm/include/llvm/CodeGen/Register.h
M llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/Frontend/Driver/CodeGenOptions.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/MC/MCRegister.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/SandboxIR/Value.h
M llvm/include/llvm/SandboxIR/Values.def
M llvm/lib/Analysis/CaptureTracking.cpp
M llvm/lib/Analysis/GlobalsModRef.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/CGData/CodeGenData.cpp
M llvm/lib/CodeGen/DetectDeadLanes.cpp
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/InlineSpiller.cpp
M llvm/lib/CodeGen/LiveInterval.cpp
M llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
M llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
M llvm/lib/CodeGen/MLRegAllocPriorityAdvisor.cpp
M llvm/lib/CodeGen/MachineTraceMetrics.cpp
M llvm/lib/CodeGen/RDFRegisters.cpp
M llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegAllocGreedy.h
M llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp
R llvm/lib/CodeGen/RegAllocPriorityAdvisor.h
M llvm/lib/CodeGen/RegisterPressure.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
M llvm/lib/Frontend/Driver/CodeGenOptions.cpp
M llvm/lib/ObjectYAML/XCOFFEmitter.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/SandboxIR/BasicBlock.cpp
M llvm/lib/SandboxIR/Context.cpp
M llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
A llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.h
M llvm/lib/Target/ARC/ARCOptAddrMode.cpp
M llvm/lib/Target/ARM/A15SDOptimizer.cpp
M llvm/lib/Target/ARM/ARMLatencyMutations.cpp
M llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
M llvm/lib/Target/Hexagon/BitTracker.cpp
M llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
M llvm/lib/Target/Hexagon/HexagonCopyHoisting.cpp
M llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
M llvm/lib/Target/M68k/M68kISelLowering.cpp
M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
M llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h
M llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
M llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
M llvm/lib/Target/PowerPC/PPCVSXCopy.cpp
M llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
M llvm/lib/Target/RISCV/CMakeLists.txt
M llvm/lib/Target/RISCV/RISCV.h
A llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
M llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp
M llvm/lib/Target/WebAssembly/WebAssemblySortRegion.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/Coroutines/MaterializationUtils.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/IPO/PartialInlining.cpp
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/lib/Transforms/Utils/AssumeBundleBuilder.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanHCFGBuilder.cpp
M llvm/test/Analysis/GlobalsModRef/nonescaping-noalias.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
A llvm/test/CodeGen/AArch64/cmpbr-branch-relaxation.mir
A llvm/test/CodeGen/AArch64/cmpbr-early-ifcvt.mir
A llvm/test/CodeGen/AArch64/cmpbr-reg-imm-at-bounds.ll
A llvm/test/CodeGen/AArch64/cmpbr-reg-imm.ll
A llvm/test/CodeGen/AArch64/cmpbr-reg-reg.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/Mips/readcyclecounter.ll
A llvm/test/CodeGen/PowerPC/llvm.modf.ll
M llvm/test/CodeGen/RISCV/O0-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
A llvm/test/CodeGen/RISCV/fold-mem-offset.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/commutable.ll
M llvm/test/CodeGen/RISCV/rvv/copyprop.mir
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
A llvm/test/CodeGen/RISCV/rvv/mask-exts-not.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
M llvm/test/CodeGen/RISCV/rvv/vector-reassociations.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
M llvm/test/CodeGen/RISCV/rvv/vleff.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/RISCV/split-offsets.ll
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bindless_images/bindless_images_generic.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-type-struct.ll
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
M llvm/test/CodeGen/X86/sext-vsetcc.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-v192.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/ThinLTO/X86/memprof-recursive.ll
M llvm/test/Transforms/FunctionAttrs/nocapture.ll
M llvm/test/Transforms/InstCombine/select-icmp-and.ll
M llvm/test/Transforms/InstCombine/store.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/large-loop-rdx.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
A llvm/test/Transforms/LoopVectorize/loop-with-constant-exit-condition.ll
M llvm/test/Transforms/MemCpyOpt/memcpy.ll
M llvm/test/Transforms/MemProfContextDisambiguation/recursive.ll
A llvm/test/Transforms/PhaseOrdering/load-store-sameval.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/global_none_meta.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/global_none_meta.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/global_none_meta.test
A llvm/test/tools/llvm-dwarfdump/X86/debug-names-verify-completeness-json-output.s
A llvm/test/tools/llvm-dwarfdump/X86/debug-names-verify-cu-lists-json-output.s
M llvm/unittests/ADT/SetOperationsTest.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/utils/UpdateTestChecks/common.py
M llvm/utils/gn/secondary/libunwind/src/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
M llvm/utils/lit/lit/llvm/config.py
M llvm/utils/release/build_llvm_release.bat
M llvm/utils/update_cc_test_checks.py
M llvm/utils/update_test_checks.py
M mlir/docs/Dialects/Linalg/_index.md
M mlir/include/mlir/Analysis/DataFlow/IntegerRangeAnalysis.h
M mlir/include/mlir/Dialect/EmitC/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/Math/IR/MathOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/lib/Analysis/DataFlow/IntegerRangeAnalysis.cpp
M mlir/lib/AsmParser/Parser.cpp
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Arith/Transforms/UnsignedWhenEquivalent.cpp
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/Dialect/Math/IR/MathOps.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaMakeBroadcastable.cpp
M mlir/lib/Interfaces/InferIntRangeInterface.cpp
M mlir/python/mlir/dialects/LinalgOps.td
M mlir/python/mlir/dialects/linalg/__init__.py
M mlir/test/Conversion/MathToROCDL/math-to-rocdl.mlir
M mlir/test/Dialect/Affine/affine-data-copy.mlir
M mlir/test/Dialect/EmitC/invalid_ops.mlir
M mlir/test/Dialect/EmitC/ops.mlir
M mlir/test/Dialect/LLVMIR/canonicalize.mlir
M mlir/test/Dialect/Linalg/fuse-with-reshape-by-collapsing.mlir
M mlir/test/Dialect/Linalg/fusion-push-reshape.mlir
M mlir/test/Dialect/Math/canonicalize.mlir
M mlir/test/Dialect/SCF/invalid.mlir
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
M mlir/test/python/dialects/linalg/ops.py
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_global.cpp
M openmp/runtime/src/kmp_runtime.cpp
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