[all-commits] [llvm/llvm-project] c48e0c: [lldb][RISC-V] Extended if conditions to support a...

[kper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c48e0c182c5a9e19062677cbca17c89ea586e033
      https://github.com/llvm/llvm-project/commit/c48e0c182c5a9e19062677cbca17c89ea586e033
  Author: kper <kevin.per at protonmail.com>
  Date:   2025-02-20 (Thu, 20 Feb 2025)

  Changed paths:
    M lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
    M lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
    A lldb/test/API/functionalities/gdb_remote_client/basic_eh_frame-riscv64.yaml
    M lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
    A lldb/test/Shell/Register/Inputs/riscv64-gp-read.cpp
    A lldb/test/Shell/Register/riscv64-gp-read.test
    M llvm/utils/lit/lit/llvm/config.py

  Log Message:
  -----------
  [lldb][RISC-V] Extended if conditions to support alias names for registers (#124475)

Extending the conditionals in `AugmentRegisterInfo` to support
alternative names for lldb.

Fixes #124023

There is an exception with register `X8` which is not covered here but
more details can be found in the issue
https://github.com/llvm/llvm-project/issues/127900.



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