[all-commits] [llvm/llvm-project] df96b5: [RISCV] Move VMV0 elimination past machine SSA opt...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: df96b56b9fad29ff0a8654730952d02e7ef6cc50
      https://github.com/llvm/llvm-project/commit/df96b56b9fad29ff0a8654730952d02e7ef6cc50
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-02-20 (Thu, 20 Feb 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp
    M llvm/test/CodeGen/RISCV/O0-pipeline.ll
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/commutable.ll
    M llvm/test/CodeGen/RISCV/rvv/copyprop.mir
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
    M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-reassociations.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll

  Log Message:
  -----------
  [RISCV] Move VMV0 elimination past machine SSA opts (#126850)

This is the follow up to #125026 that keeps mask operands in virtual
register form for as long as possible throughout the backend.

The diffs in this patch are from MachineCSE/MachineSink/RISCVVLOptimizer
kicking in.

The invariant that the mask COPY never has a subreg no longer holds
after MachineCSE (it coalesces some copies), so it needed to be relaxed.



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