[all-commits] [llvm/llvm-project] 50bdd1: [AMDGPU] Change SGPR layout to striped caller/call...

Shilei Tian via All-commits all-commits at lists.llvm.org
Tue Feb 18 09:49:02 PST 2025 

  Branch: refs/heads/users/shiltian/striped-sgpr-cc
  Home:   https://github.com/llvm/llvm-project
  Commit: 50bdd130ec56864afccdd99b405f28249d148dbe
      https://github.com/llvm/llvm-project/commit/50bdd130ec56864afccdd99b405f28249d148dbe
  Author: Shilei Tian <i at tianshilei.me>
  Date:   2025-02-18 (Tue, 18 Feb 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
    M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
    M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
    M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
    M llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
    M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
    M llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
    M llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
    M llvm/test/CodeGen/AMDGPU/ds_read2.ll
    M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
    M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
    M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
    M llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
    M llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir
    M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
    M llvm/test/CodeGen/AMDGPU/indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/issue48473.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
    M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
    M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
    M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
    M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
    M llvm/test/CodeGen/AMDGPU/mcexpr-knownbits-assign-crash-gh-issue-110930.ll
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
    M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
    M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll
    M llvm/test/CodeGen/AMDGPU/select.f16.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
    M llvm/test/CodeGen/AMDGPU/sibling-call.ll
    M llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir
    M llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
    M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
    M llvm/test/CodeGen/AMDGPU/stack-realign.ll
    M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
    M llvm/test/CodeGen/AMDGPU/unallocatable-bundle-regression.mir
    M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
    M llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll
    M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir

  Log Message:
  -----------
  [AMDGPU] Change SGPR layout to striped caller/callee saved

This PR updates the SGPR layout to a striped caller/callee-saved design, similar
to the VGPR layout. The stripe width is set to 8.

Fixes #113782.


  Commit: 5478409c9853daef8d8e7aaee7d40655b8b76f04
      https://github.com/llvm/llvm-project/commit/5478409c9853daef8d8e7aaee7d40655b8b76f04
  Author: Shilei Tian <i at tianshilei.me>
  Date:   2025-02-18 (Tue, 18 Feb 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
    M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
    M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
    M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
    M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
    M llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
    M llvm/test/CodeGen/AMDGPU/ds_read2.ll
    M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
    M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
    M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
    M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
    M llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
    M llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir
    M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
    M llvm/test/CodeGen/AMDGPU/indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/issue48473.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
    M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
    M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
    M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
    M llvm/test/CodeGen/AMDGPU/mcexpr-knownbits-assign-crash-gh-issue-110930.ll
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
    M llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
    M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
    M llvm/test/CodeGen/AMDGPU/select.f16.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
    M llvm/test/CodeGen/AMDGPU/sibling-call.ll
    M llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir
    M llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
    M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
    M llvm/test/CodeGen/AMDGPU/stack-realign.ll
    M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
    M llvm/test/CodeGen/AMDGPU/unallocatable-bundle-regression.mir
    M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
    M llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll

  Log Message:
  -----------
  Start the partition from s40


Compare: https://github.com/llvm/llvm-project/compare/178dd48d6ef1...5478409c9853

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