[all-commits] [llvm/llvm-project] d4a084: [SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes...

[James Chesterman via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d4a0848dc6678bc4ce8c74855a818dfc8c30a088
      https://github.com/llvm/llvm-project/commit/d4a0848dc6678bc4ce8c74855a818dfc8c30a088
  Author: James Chesterman <James.Chesterman at arm.com>
  Date:   2025-02-18 (Tue, 18 Feb 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/ISDOpcodes.h
    M llvm/include/llvm/CodeGen/SelectionDAG.h
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/CodeGen/TargetLoweringBase.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
    M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
    M llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll

  Log Message:
  -----------
  [SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (#125207)

Add signed and unsigned PARTIAL_REDUCE_MLA ISD nodes. Add command line
argument (aarch64-enable-partial-reduce-nodes) that indicates whether the
intrinsic experimental_vector_partial_ reduce_add will be transformed
into the new ISD node. Lowering with the new ISD nodes will, for now,
always be done as an expand.



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