[all-commits] [llvm/llvm-project] 6b2e51: [RISCV] Implement isHighLatencyDef() (#127476)

[Pengcheng Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6b2e511aedb1b372ecd6eaa89720dc3586f3ae19
      https://github.com/llvm/llvm-project/commit/6b2e511aedb1b372ecd6eaa89720dc3586f3ae19
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2025-02-18 (Tue, 18 Feb 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.h
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll

  Log Message:
  -----------
  [RISCV] Implement isHighLatencyDef() (#127476)

And returns true for div/rem/sqrt/... operations.

This is an alternative if we don't support generic scheduling model.



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