[all-commits] [llvm/llvm-project] ef9f0b: [DAGCombiner] Don't peek through truncates of shif...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ef9f0b3c414a5d55e694829514d7b2ff8736d3c3
      https://github.com/llvm/llvm-project/commit/ef9f0b3c414a5d55e694829514d7b2ff8736d3c3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-02-17 (Mon, 17 Feb 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll

  Log Message:
  -----------
  [DAGCombiner] Don't peek through truncates of shift amounts in takeInexpensiveLog2. (#126957)

Shift amounts in SelectionDAG don't have to match the result type
of the shift. SelectionDAGBuilder will aggressively truncate shift
amounts to the target's preferred type. This may result in a zero extend
that existed in IR being removed.
    
If we look through a truncate here, we can't guarantee the upper bits
of the truncate input are zero. There may have been a zext that was
removed. Unfortunately, this regresses tests where no truncate was
involved. The only way I can think to fix this is to add an assertzext
when SelectionDAGBuilder truncates a shift amount or remove the
early truncation of shift amounts from SelectionDAGBuilder all together.
    
Fixes #126889.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications