[all-commits] [llvm/llvm-project] ab2d33: TableGen: Generate reverseComposeSubRegIndices (#1...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ab2d330feab3e1d9927a3c0de1a9d6e9bda5abe9
      https://github.com/llvm/llvm-project/commit/ab2d330feab3e1d9927a3c0de1a9d6e9bda5abe9
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-02-17 (Mon, 17 Feb 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  TableGen: Generate reverseComposeSubRegIndices (#127050)

This is necessary to enable composing subregisters in peephole-opt.
For now use a brute force table to find the return value. The worst
case target is AMDGPU with a 399 x 399 entry table.



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