[all-commits] [llvm/llvm-project] ea7897: [WebAssembly] Enable interleaved memory accesses (...

[Sam Parker via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ea7897a617b897f87f148db48cda9fcc7c1c53dc
      https://github.com/llvm/llvm-project/commit/ea7897a617b897f87f148db48cda9fcc7c1c53dc
  Author: Sam Parker <sam.parker at arm.com>
  Date:   2025-02-17 (Mon, 17 Feb 2025)

  Changed paths:
    M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
    A llvm/test/CodeGen/WebAssembly/interleave.ll

  Log Message:
  -----------
  [WebAssembly] Enable interleaved memory accesses (#125696)

Enable the vectorizer to access interleaved memory. This means that,
when it's decided to be profitable, the memory accesses can be
vectorized instead of the value being built up by a sequence of
load_lane instructions. This will often increase the vectorization
factor of the loop, leading to significantly better performance.

I run a reasonably large collection of benchmarks and most are not
affected by this change, with most performance changes <1%. But I see a
2.5% speedup for the total run time of TSVC, 1% speedup for SPEC2017
x265, 28% speedup for a ResNet workload and 95% for libyuv. This is
running V8 on an AArch64 box.



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