[all-commits] [llvm/llvm-project] b16ce8: [X86] getFauxShuffleMask - match 256-bit CONCAT(SU...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b16ce8fc24f32aa0614562de0a2d0916118398fb
      https://github.com/llvm/llvm-project/commit/b16ce8fc24f32aa0614562de0a2d0916118398fb
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2025-02-17 (Mon, 17 Feb 2025)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
    M llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
    M llvm/test/CodeGen/X86/widen_fadd.ll
    M llvm/test/CodeGen/X86/widen_fdiv.ll
    M llvm/test/CodeGen/X86/widen_fmul.ll
    M llvm/test/CodeGen/X86/widen_fsub.ll

  Log Message:
  -----------
  [X86] getFauxShuffleMask - match 256-bit CONCAT(SUB0, SUB1) 64-bit elt patterns as well as 512-bit (#127392)

The 512-bit filter was to prevent AVX1/2 regressions, but most of that is now handled by canonicalizeShuffleWithOp

Ideally we need to support smaller element widths as well.

Noticed while triaging #116931



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