[all-commits] [llvm/llvm-project] 781704: [RISCV] Support [mh]edelegh CSRs (#121634)

[dong-miao via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7817045e5c5cfbcbf3428ace7a4b3bfb5281a641
      https://github.com/llvm/llvm-project/commit/7817045e5c5cfbcbf3428ace7a4b3bfb5281a641
  Author: dong-miao <miaozhendong24 at mails.ucas.ac.cn>
  Date:   2025-02-16 (Sun, 16 Feb 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSystemOperands.td
    M llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
    M llvm/test/MC/RISCV/rv32-machine-csr-names.s
    M llvm/test/MC/RISCV/rv32-only-csr-names.s

  Log Message:
  -----------
  [RISCV] Support [mh]edelegh CSRs (#121634)

These RV32-only CSRs are defined in privileged spec v1.13.



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