[all-commits] [llvm/llvm-project] bfdf30: [AArch64] Add patterns for addv(sext) and addv(zext)

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bfdf30e9b3d0b49344a651a5c7cd87be31d255c4
      https://github.com/llvm/llvm-project/commit/bfdf30e9b3d0b49344a651a5c7cd87be31d255c4
  Author: David Green <david.green at arm.com>
  Date:   2025-02-15 (Sat, 15 Feb 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-vabs.ll
    M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
    M llvm/test/CodeGen/AArch64/vecreduce-add.ll

  Log Message:
  -----------
  [AArch64] Add patterns for addv(sext) and addv(zext)

This adds patterns for v8i8->i16 vaddlv and v4i16->i32 vaddlv, for both signed
and unsigned extends.



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