[all-commits] [llvm/llvm-project] 7eadc1: [RISCV] Add a generic OOO CPU (#120712)

[Pengcheng Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7eadc1960d199676f04add402bb0aa6f65b7b234
      https://github.com/llvm/llvm-project/commit/7eadc1960d199676f04add402bb0aa6f65b7b234
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2025-02-14 (Fri, 14 Feb 2025)

  Changed paths:
    M clang/docs/ReleaseNotes.rst
    M clang/test/Misc/target-invalid-cpu-note/riscv.c
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    A llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
    A llvm/test/tools/llvm-mca/RISCV/GenericOOO/atomic.s
    A llvm/test/tools/llvm-mca/RISCV/GenericOOO/floating-point.s
    A llvm/test/tools/llvm-mca/RISCV/GenericOOO/integer.s

  Log Message:
  -----------
  [RISCV] Add a generic OOO CPU (#120712)

We add a generic out-of-order CPU model here just like what GCC
has done.
    
People may use this model to evaluate some optimizations, and more
importantly, people can use this model as a template to customize
their own CPU models.
    
The design (units, cycles, ...) of this model is random so don't
take it seriously.



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