[all-commits] [llvm/llvm-project] 16a5f7: [libc] Fix implict cast to time_t warning (#126947)
Michael Kruse via All-commits
all-commits at lists.llvm.org
Thu Feb 13 15:04:15 PST 2025
Branch: refs/heads/users/meinersbur/flang_runtime_move-files
Home: https://github.com/llvm/llvm-project
Commit: 16a5f7eb73f225544d29e613c84011f1e1ec53a4
https://github.com/llvm/llvm-project/commit/16a5f7eb73f225544d29e613c84011f1e1ec53a4
Author: Michael Jones <michaelrj at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M libc/src/time/time_utils.h
Log Message:
-----------
[libc] Fix implict cast to time_t warning (#126947)
On some systems time_t is 32 bit, causing build errors (with -Werror)
in get_epoch which attempts to implicitly convert an int64_t to a
time_t.
Fixes:
error: implicit conversion loses integer precision: 'int64_t' (aka 'long
long') to 'time_t' (aka 'int') [-Werror,-Wshorten-64-to-32]
332 | return mktime_internal(timeptr);
| ~~~~~~ ^~~~~~~~~~~~~~~~~~~~~~~~
Commit: d200caa5216e8e65fe16455e9858f45926fdd79c
https://github.com/llvm/llvm-project/commit/d200caa5216e8e65fe16455e9858f45926fdd79c
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel
Log Message:
-----------
Revert "[bazel] Temporarily disable a broken LookupAddressRangeWithSt… (#126944)
…mtSequenceOffset debug info test"
This reverts commit 247430e9c41c61b66e2ee95c29a05de3e24c19b9.
The breakage has been fixed by 343bbda140d5a15cd7d7fbfc6041a7506da5cdae.
Commit: 67cde37f3c89c22a51d1c20f75965c64c79b1bce
https://github.com/llvm/llvm-project/commit/67cde37f3c89c22a51d1c20f75965c64c79b1bce
Author: Max191 <44243577+Max191 at users.noreply.github.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/DataLayoutPropagation.cpp
M mlir/test/Dialect/Linalg/data-layout-propagation.mlir
Log Message:
-----------
[mlir] Match before rewrite in BubbleUpPackOpThroughGenericOp (#126946)
The BubbleUpPackOpThroughGenericOp pattern had some unsafe rewrites
happening before matching was fully complete, which causes the pattern
rewriter to fail to converge. This PR fixes the bug by moving all
matching logic to before the rewrite logic.
Signed-off-by: Max Dawkins <max.dawkins at gmail.com>
Commit: a6a4252a15669a2d89ad9134e42b87fb0f56c103
https://github.com/llvm/llvm-project/commit/a6a4252a15669a2d89ad9134e42b87fb0f56c103
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll
M llvm/test/CodeGen/X86/vec-strict-fptoint-256.ll
M llvm/test/CodeGen/X86/vec-strict-fptoint-512.ll
Log Message:
-----------
[X86] vec-strict-fptoint - regenerate VPTERNLOG comments
Commit: 689f79d0f86a6965c0a9c4bc73bc0417c7972b7f
https://github.com/llvm/llvm-project/commit/689f79d0f86a6965c0a9c4bc73bc0417c7972b7f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll
Log Message:
-----------
[X86] vec-strict-cmp-512-skx.ll - regenerate checks
Appears to have been manually edited at some point
Commit: f719d8ac1ccd08a9e8def796ecb9b1cd517c86af
https://github.com/llvm/llvm-project/commit/f719d8ac1ccd08a9e8def796ecb9b1cd517c86af
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/vec-strict-cmp-128-fp16.ll
Log Message:
-----------
[X86] vec-strict-cmp-128-fp16.ll - regenerate VMOVSH comments
Commit: 1f51038036b4bc216eddcc620dcb9eca5df2bfef
https://github.com/llvm/llvm-project/commit/1f51038036b4bc216eddcc620dcb9eca5df2bfef
Author: Krishna Pandey <47917477+krishna2803 at users.noreply.github.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/headers/math/stdfix.rst
M libc/include/stdfix.yaml
M libc/src/__support/fixed_point/CMakeLists.txt
M libc/src/__support/fixed_point/fx_bits.h
M libc/src/__support/fixed_point/fx_rep.h
M libc/src/stdfix/CMakeLists.txt
A libc/src/stdfix/countlshk.cpp
A libc/src/stdfix/countlshk.h
A libc/src/stdfix/countlshr.cpp
A libc/src/stdfix/countlshr.h
A libc/src/stdfix/countlsk.cpp
A libc/src/stdfix/countlsk.h
A libc/src/stdfix/countlslk.cpp
A libc/src/stdfix/countlslk.h
A libc/src/stdfix/countlslr.cpp
A libc/src/stdfix/countlslr.h
A libc/src/stdfix/countlsr.cpp
A libc/src/stdfix/countlsr.h
A libc/src/stdfix/countlsuhk.cpp
A libc/src/stdfix/countlsuhk.h
A libc/src/stdfix/countlsuhr.cpp
A libc/src/stdfix/countlsuhr.h
A libc/src/stdfix/countlsuk.cpp
A libc/src/stdfix/countlsuk.h
A libc/src/stdfix/countlsulk.cpp
A libc/src/stdfix/countlsulk.h
A libc/src/stdfix/countlsulr.cpp
A libc/src/stdfix/countlsulr.h
A libc/src/stdfix/countlsur.cpp
A libc/src/stdfix/countlsur.h
M libc/test/src/stdfix/CMakeLists.txt
A libc/test/src/stdfix/CountlsTest.h
A libc/test/src/stdfix/countlshk_test.cpp
A libc/test/src/stdfix/countlshr_test.cpp
A libc/test/src/stdfix/countlsk_test.cpp
A libc/test/src/stdfix/countlslk_test.cpp
A libc/test/src/stdfix/countlslr_test.cpp
A libc/test/src/stdfix/countlsr_test.cpp
A libc/test/src/stdfix/countlsuhk_test.cpp
A libc/test/src/stdfix/countlsuhr_test.cpp
A libc/test/src/stdfix/countlsuk_test.cpp
A libc/test/src/stdfix/countlsulk_test.cpp
A libc/test/src/stdfix/countlsulr_test.cpp
A libc/test/src/stdfix/countlsur_test.cpp
Log Message:
-----------
[libc][stdfix] Implement `countlsfx` functions in libc. (#126597)
fixes #113357
---------
Signed-off-by: krishna2803 <kpandey81930 at gmail.com>
Commit: 562c0c611a3bee6b7766043bfdeb5c6f47d7d2fd
https://github.com/llvm/llvm-project/commit/562c0c611a3bee6b7766043bfdeb5c6f47d7d2fd
Author: Chris B <chris.bieneman at me.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/docs/HLSL/FunctionCalls.rst
Log Message:
-----------
[HLSL][Docs] Update function calls docs (#106860)
Update the function calls documentation to match the newly landed
implementation.
Commit: b0d782080529cf5d422847e1f91f29bd7c62f691
https://github.com/llvm/llvm-project/commit/b0d782080529cf5d422847e1f91f29bd7c62f691
Author: Petr Hosek <phosek at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M libc/include/__llvm-libc-common.h
M libc/include/llvm-libc-macros/features-macros.h
Log Message:
-----------
[libc] Move __LLVM_LIBC__ define to __llvm-libc-common.h (#126877)
Relying on features.h is problematic since codebases are free to have
such a header on their search path, which breaks compilation. libc
should instead provide a more standard way of getting __LLVM_LIBC__.
Since __llvm-libc-common.h is included from all libc headers, defining
__LLVM_LIBC__ there ensures that this define is available whenever any
of the standard header is included.
Commit: 6d7a84d72bf7f7be2a401e80a5339e1ae8f7c0f5
https://github.com/llvm/llvm-project/commit/6d7a84d72bf7f7be2a401e80a5339e1ae8f7c0f5
Author: vporpo <vporpodas at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Scheduler.cpp
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
M llvm/test/Transforms/SandboxVectorizer/bottomup_seed_slice_pow2.ll
M llvm/test/Transforms/SandboxVectorizer/repeated_instrs.ll
M llvm/test/Transforms/SandboxVectorizer/scheduler.ll
Log Message:
-----------
[SandboxVec][Scheduler] Fix top of schedule (#126820)
This patch fixes the way the top-of-schedule variable gets set and
updated. Before this patch it used to get updated whenever we scheduled
a bundle, which is wrong, as the top-of-schedule needs to be maintained
across scheduling attempts.
It should get reset only when we clear the schedule or when we destroy
the current schedule and re-schedule.
Commit: 53c618c07154f8a99762fb5222aa9c05f6c434f7
https://github.com/llvm/llvm-project/commit/53c618c07154f8a99762fb5222aa9c05f6c434f7
Author: Peter Rong <peterrong96 at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/include/clang/AST/Mangle.h
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/lib/CodeGen/CGObjCRuntime.h
M clang/lib/CodeGen/CodeGenFunction.h
Log Message:
-----------
[clang] run clang-format on some CGObjC files (#126644)
These files are relatively old and don't confront our formatting rules.
It's hard to change them without massive clang-format changes.
---------
Signed-off-by: Peter Rong <PeterRong at meta.com>
Commit: 9478822f4f63aa2e5f7bc120406688298911fa24
https://github.com/llvm/llvm-project/commit/9478822f4f63aa2e5f7bc120406688298911fa24
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
Log Message:
-----------
[RISCV] Decompose single source shuffles (without exact VLEN) (#126951)
(This is a re-apply for what was 8374d42. The bug there was fairly
major - despite the comments and review description, the code was
using each register in the source register group, not only the first
register. This was completely wrong.)
This is a continuation of the work started in
https://github.com/llvm/llvm-project/pull/125735 to lower selected VLA
shuffles in linear m1 components instead of generating O(LMUL^2) or
O(LMUL*Log2(LMUL) high LMUL shuffles.
This pattern focuses on shuffles where all the elements being used
across the entire destination register group come from a single register
in the source register group. Such cases come up fairly frequently via
e.g. spread(N), and repeat(N) idioms.
One subtlety to this patch is the handling of the index vector for
vrgatherei16.vv. Because the index and source registers can have
different EEW, the index vector for the Nth chunk of the destination is
not guaranteed to be register aligned. In fact, it is common for e.g. an
EEW=64 shuffle to have EEW=16 indices which are four chunks per source
register. Given this, we have to pay a cost for extracting these chunks
into the low position before performing each shuffle.
I'd initially expressed this as a naive extract sub-vector for each data
parallel piece. However, at high LMUL, this quickly caused register
pressure problems since we could at worst need 4x the temporary
registers for the index. Instead, this patch uses a repeating slidedown
chained from previous iterations. This increases critical path by at
worst 3 slides (SEW=64 is the worst case), but reduces register pressure
to at worst 2x - and only if the original index vector is reused
elsewhere. I view this as arguably a bit of a workaround (since our
scheduling should have done better with the plain extract variant), but
a probably necessary one.
Commit: 7a7f9190d03e12dc5b57d3eb33a84d078de43104
https://github.com/llvm/llvm-project/commit/7a7f9190d03e12dc5b57d3eb33a84d078de43104
Author: vporpo <vporpodas at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/InstrMaps.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/InstrMapsTest.cpp
Log Message:
-----------
[SandboxVec][Legality] Fix mask on diamond reuse with shuffle (#126963)
This patch fixes a bug in the creation of shuffle masks when vectorizing
vectors in case of a diamond reuse with shuffle. The mask needs to
enumerate all elements of a vector, not treat the original vector value
as a single element. That is: if vectorizing two <2 x float> vectors
into a <4 x float> the mask needs to have 4 indices, not just 2.
Commit: 859c871184bdfdebb47b5c7ec5e59348e0534e0b
https://github.com/llvm/llvm-project/commit/859c871184bdfdebb47b5c7ec5e59348e0534e0b
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll
M llvm/test/CodeGen/RISCV/GlobalISel/combine-neg-abs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll
M llvm/test/CodeGen/RISCV/GlobalISel/stacksave-stackrestore.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abds.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
M llvm/test/CodeGen/RISCV/abdu.ll
M llvm/test/CodeGen/RISCV/add-before-shl.ll
M llvm/test/CodeGen/RISCV/add-imm.ll
M llvm/test/CodeGen/RISCV/alloca.ll
M llvm/test/CodeGen/RISCV/alu64.ll
M llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
M llvm/test/CodeGen/RISCV/atomic-rmw.ll
M llvm/test/CodeGen/RISCV/atomic-signext.ll
M llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/RISCV/bf16-promote.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/bfloat-mem.ll
M llvm/test/CodeGen/RISCV/bfloat.ll
M llvm/test/CodeGen/RISCV/bittest.ll
M llvm/test/CodeGen/RISCV/branch-on-zero.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/calling-conv-half.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32e.ll
M llvm/test/CodeGen/RISCV/calls.ll
M llvm/test/CodeGen/RISCV/codemodel-lowering.ll
M llvm/test/CodeGen/RISCV/condbinops.ll
M llvm/test/CodeGen/RISCV/condops.ll
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/double-calling-conv.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/double-imm.ll
M llvm/test/CodeGen/RISCV/double-mem.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
M llvm/test/CodeGen/RISCV/fastcc-bf16.ll
M llvm/test/CodeGen/RISCV/fastcc-float.ll
M llvm/test/CodeGen/RISCV/fastcc-half.ll
M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/float-select-fcmp.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
M llvm/test/CodeGen/RISCV/forced-atomics.ll
M llvm/test/CodeGen/RISCV/fp-fcanonicalize.ll
M llvm/test/CodeGen/RISCV/fp128.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/get-setcc-result-type.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-mem.ll
M llvm/test/CodeGen/RISCV/half-select-fcmp.ll
M llvm/test/CodeGen/RISCV/iabs.ll
M llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
M llvm/test/CodeGen/RISCV/inline-asm-d-modifier-N.ll
M llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
M llvm/test/CodeGen/RISCV/inline-asm-f-modifier-N.ll
M llvm/test/CodeGen/RISCV/inline-asm-zfinx-constraint-r.ll
M llvm/test/CodeGen/RISCV/inline-asm-zhinx-constraint-r.ll
M llvm/test/CodeGen/RISCV/inline-asm.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
M llvm/test/CodeGen/RISCV/legalize-fneg.ll
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
M llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll
M llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
M llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
M llvm/test/CodeGen/RISCV/mem.ll
M llvm/test/CodeGen/RISCV/mem64.ll
M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
M llvm/test/CodeGen/RISCV/memcmp.ll
M llvm/test/CodeGen/RISCV/memmove.ll
M llvm/test/CodeGen/RISCV/memset-pattern.ll
M llvm/test/CodeGen/RISCV/mul.ll
M llvm/test/CodeGen/RISCV/neg-abs.ll
M llvm/test/CodeGen/RISCV/orc-b-patterns.ll
M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
M llvm/test/CodeGen/RISCV/pr51206.ll
M llvm/test/CodeGen/RISCV/pr58511.ll
M llvm/test/CodeGen/RISCV/pr63816.ll
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
M llvm/test/CodeGen/RISCV/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/rv32-inline-asm-pairs.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv32zbs.ll
M llvm/test/CodeGen/RISCV/rv64-double-convert.ll
M llvm/test/CodeGen/RISCV/rv64-half-convert.ll
M llvm/test/CodeGen/RISCV/rv64-inline-asm-pairs.ll
M llvm/test/CodeGen/RISCV/rv64-trampoline.ll
M llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
M llvm/test/CodeGen/RISCV/rv64zbkb.ll
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll
M llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll
M llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
M llvm/test/CodeGen/RISCV/rvv/copyprop.mir
M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/expandload.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpowi.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-addsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store-merge-crash.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll
M llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/localvar.ll
M llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll
M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
M llvm/test/CodeGen/RISCV/rvv/pr125306.ll
M llvm/test/CodeGen/RISCV/rvv/pr63596.ll
M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/shrinkwrap.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.s.x.ll
M llvm/test/CodeGen/RISCV/rvv/vmv0-elimination.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-mask-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub-mask-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/wrong-chain-fixed-load.ll
M llvm/test/CodeGen/RISCV/scmp.ll
M llvm/test/CodeGen/RISCV/select-and.ll
M llvm/test/CodeGen/RISCV/select-bare.ll
M llvm/test/CodeGen/RISCV/select-cc.ll
M llvm/test/CodeGen/RISCV/select-constant-xor.ll
M llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
M llvm/test/CodeGen/RISCV/select-or.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/shift-amount-mod.ll
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/shl-cttz.ll
M llvm/test/CodeGen/RISCV/split-offsets.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/stack-slot-size.ll
M llvm/test/CodeGen/RISCV/stack-store-check.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/RISCV/ucmp.ll
M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
M llvm/test/CodeGen/RISCV/xtheadmempair.ll
M llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
M llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
M llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
Log Message:
-----------
[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)
This change introduces a default schedule model for the RISCV target
which leaves everything unchanged except the MicroOpBufferSize. The
default value of this flag in NoSched is 0. Both configurations
represent in order cores (i.e. no reorder window), the difference
between them comes down to whether heuristics other than latency are
allowed to apply. (Implementation details below)
I left the processor models which explicitly set MicroOpBufferSize=0
unchanged in this patch, but strongly suspect we should change those
too. Honestly, I think the LLVM wide default for this flag should be
changed, but don't have the energy to manage the updates for all
targets.
Implementation wise, the effect of this change is that schedule units
which are ready to run *except that* one of their predecessors may not
have completed yet are added to the Available list, not the Pending one.
The result of this is that it becomes possible to chose to schedule a
node before it's ready cycle if the heuristics prefer. This is
essentially chosing to insert a resource stall instead of e.g.
increasing register pressure.
Note that I was initially concerned there might be a correctness aspect
(as in some kind of exposed pipeline design), but the generic scheduler
doesn't seem to know how to insert noop instructions. Without that, a
program wouldn't be guaranteed to schedule on an exposed pipeline
depending on the program and schedule model in question.
The effect of this is that we sometimes prefer register pressure in
codegen results. This is mostly churn (or small wins) on scalar because
we have many more registers, but is of major importance on vector -
particularly high LMUL - because we effectively have many fewer
registers and the relative cost of spilling is much higher. This is a
significant improvement on high LMUL code quality for default rva23u
configurations - or any non -mcpu vector configuration for that matter.
Fixes #107532
Commit: e75e61728e201f1941c794a12ea22789b6f24c75
https://github.com/llvm/llvm-project/commit/e75e61728e201f1941c794a12ea22789b6f24c75
Author: Vasileios Porpodas <vporpodas at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
Log Message:
-----------
[SandboxVec] Fix warnings introduced by 7a7f9190d03e
Commit: 82605285b8c647f4248bb22f2c9d19945cfcba8c
https://github.com/llvm/llvm-project/commit/82605285b8c647f4248bb22f2c9d19945cfcba8c
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
A llvm/test/Analysis/LoopAccessAnalysis/retry-runtime-checks-after-dependence-analysis.ll
Log Message:
-----------
[LAA] Also clear CheckingGroups in RuntimePointerChecking::reset.
This fixes a crash when trying to print access-info in the newly added
test cases.
Commit: e9e6ba6a5e2a4ca7386861136196903febb9968b
https://github.com/llvm/llvm-project/commit/e9e6ba6a5e2a4ca7386861136196903febb9968b
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-cvt.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt.ll
Log Message:
-----------
[msan] Handle single-parameter Arm NEON vector convert intrinsics (#126136)
This handles the following llvm.aarch64.neon intrinsics, which were suboptimally handled by visitInstruction:
- fcvtas, fcvtau
- fcvtms, fcvtmu
- fcvtns, fcvtnu
- fcvtps, fcvtpu
- fcvtzs, fcvtzu
The old instrumentation checked that the shadow of every element of the input vector was fully initialized, and aborted otherwise. The new instrumentation propagates the shadow: for each element of the output, the shadow is initialized iff the corresponding element of the input is *fully* initialized (since these are floating-point to integer conversions).
Updates the tests from https://github.com/llvm/llvm-project/pull/126095
Commit: 0d95631a3adbc4343e6bfbcecc53ac8f1f0739d1
https://github.com/llvm/llvm-project/commit/0d95631a3adbc4343e6bfbcecc53ac8f1f0739d1
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/scmp.ll
M llvm/test/Instrumentation/MemorySanitizer/ucmp.ll
Log Message:
-----------
[msan] Handle llvm.[us]cmp (starship operator) (#125804)
Apply handleShadowOr to llvm.[us]cmp. Previously, llvm.[su]cmp was correctly handled heuristically when each parameter type is the same as the return type (e.g., `call i8 @llvm.ucmp.i8.i8(i8 %x, i8 %y)`) but handled incorrectly by visitInstruction when the return type is different e.g., (`call i8 @llvm.ucmp.i8.i62(i62 %x, i62 %y)`, `call <4 x i8> @llvm.ucmp.v4i8.v4i32(<4 x i32> %x, <4 x i32> %y)`).
Updates the tests from https://github.com/llvm/llvm-project/pull/125790
Commit: f2650c54c9a6caf021415ed57a0a430fbb032094
https://github.com/llvm/llvm-project/commit/f2650c54c9a6caf021415ed57a0a430fbb032094
Author: S. Bharadwaj Yadavalli <Bharadwaj.Yadavalli at microsoft.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
R clang/test/CodeGenHLSL/disable_opt.hlsl
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.h
A llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-cs.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-lib.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/lib-entry-attr-error.ll
M llvm/test/CodeGen/DirectX/llc-pipeline.ll
Log Message:
-----------
[DirectX] Set Shader Flag DisableOptimizations (#126813)
- Set the shader flag `DisableOptimizations` based on `optnone`
attribute of shader entry functions.
- Add DXIL Metadata Analysis pass as pre-requisite for Shader Flags pass
to obtain entry function information collected therein.
- Named module metadata `dx.disable_optimizations` is intended to
indicate disabling optimizations (`-O0`) via commandline flag. However,
its intent is fulfilled by `optnone` attribute of shader entry functions as
implemented in a recent change, and thus not needed. Delete
generation of named metadata and corresponding test file
`disable_opt.ll`.
- Add tests to verify correctness of setting shader flag.
Closes #112263
Commit: cbb4e99f3613549c2168f52d6f348e3a7ee3cf55
https://github.com/llvm/llvm-project/commit/cbb4e99f3613549c2168f52d6f348e3a7ee3cf55
Author: Jason Molenda <jmolenda at apple.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M lldb/source/Target/ThreadPlanStepOut.cpp
A lldb/test/API/functionalities/thread/finish-from-empty-func/Makefile
A lldb/test/API/functionalities/thread/finish-from-empty-func/TestEmptyFuncThreadStepOut.py
A lldb/test/API/functionalities/thread/finish-from-empty-func/main.c
Log Message:
-----------
[lldb] Update ThreadPlanStepOut to handle new breakpoint behavior (#126838)
I will be changing breakpoint hitting behavior soon, where currently
lldb reports a breakpoint as being hit when a thread is *at* a
BreakpointSite, but possibly has not executed the breakpoint instruction
and trapped yet, to having lldb only report a breakpoint hit when the
breakpoint instruction has actually been executed.
One corner case bug with this change is that when you are stopped at a
breakpoint (that has been hit) on the last instruction of a function,
and you do `finish`, a ThreadPlanStepOut is pushed to the thread's plan
stack to put a breakpoint on the return address and resume execution.
And when the thread is asked to resume, it sees that it is at a
BreakpointSite that has been hit, and pushes a
ThreadPlanStepOverBreakpoint on the thread. The StepOverBreakpoint
plan sees that the thread's state is eStateRunning (not eStateStepping),
so it marks itself as "auto continue" -- so once the breakpoint has
been stepped over, we will execution on the thread.
With current lldb stepping behavior ("a thread *at* a BreakpointSite is
said to have stopped with a breakpoint-hit stop reason, even if the
breakpoint hasn't been executed yet"),
`ThreadPlanStepOverBreakpoint::DoPlanExplainsStop` has a special bit of
code which detects when the thread stops with a eStopReasonBreakpoint.
It first checks if the pc is the same as when we started -- did our
"step instruction" not actually step? -- says the stop reason is
explained. Otherwise it sets auto-continue to false (because we've hit
an *unexpected* breakpoint, and we have advanced past our original pc,
and returns false - the stop reason is not explained.
So we do the "finish", lldb instruction steps, we stop *at* the
return-address breakpoint and lldb sets the thread's stop reason to
breakpoint-hit. ThreadPlanStepOverBreakpoint sees an
eStopReasonBreakpoint, sets its auto-continue to false, and says we
stopped for osme reason other than this plan. (and it will also report
`IsPlanStale()==true` so it will remove itself) Meanwhile the
ThreadPlanStepOut sees that it has stopped in the StackID it wanted to
run to, and return success.
This all changes when stopping at a breakpoint site doesn't report
breakpoint-hit until we actually execute the instruction. Now the
ThraedPlanStepOverBreakpoint looks at the thread's stop reason, it's
eStopReasonTrace (we've instruction stepped), and so it leaves its
auto-continue to `true`. ThreadPlanStepOut sees that it has reached its
goal StackID, removes its breakpoint, and says it is done.
Thread::ShouldStop thinks the auto-continue == yes vote from
ThreadPlanStepOverBreakpoint wins, and we lose control of the process.
This patch changes ThreadPlanStepOut to require that *both* (1) we are
at the StackID of the caller function, where we wanted to end up, and
(2) we have actually hit the breakpoint that we inserted.
This in effect means that now lldb instruction-steps over the breakpoint
in the callee function, stops at the return address of the caller
function. StepOverBreakpoint has completed. StepOut is still running,
and we continue the thread again. We immediatley hit the breakpoint
(that we're sitting at), and now ThreadPlanStepOut marks itself as
completed, and we return control to the user.
Jim suggests that ThreadPlanStepOverBreakpoint is a bit unusual because
it's not something pushed on the stack by a higher-order thread plan
that "owns" it, it is inserted by the Thread as it is about to resume,
if we're at a BreakpointSite. It has no connection to the thread plans
above it, but tries to set the auto-continue mode based on the state of
the thread when it is inserted (and tries to detect an unexpected
breakpoint and unset that auto-continue it previously decided on,
because it now realizes it should not influence execution control any
more). Instead maybe the
ThreadPlanStepOverBreakpoint should be inserted as a child plan of
whatever the lowest plan is on the stack at the point it is added.
I added an API test that will catch this bug in the new thread
breakpoint algorithm.
Commit: fa71238da800f3a818ec0e0649462389dc577890
https://github.com/llvm/llvm-project/commit/fa71238da800f3a818ec0e0649462389dc577890
Author: Jason Molenda <jmolenda at apple.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M lldb/source/Target/ThreadPlanStepOut.cpp
Log Message:
-----------
[lldb] inserted a typeo when checking in a suggested fix
Commit: 65ed4fa57e6293f8e059a368ac52e2a57b1f78e4
https://github.com/llvm/llvm-project/commit/65ed4fa57e6293f8e059a368ac52e2a57b1f78e4
Author: Nikhil Kalra <nkalra at apple.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/include/mlir-c/IR.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/python/ir/module.py
Log Message:
-----------
[mlir] Python: Parse ModuleOp from file path (#126572)
For extremely large models, it may be inefficient to load the model into
memory in Python prior to passing it to the MLIR C APIs for
deserialization. This change adds an API to parse a ModuleOp directly
from a file path.
Re-lands
[4e14b8a](https://github.com/llvm/llvm-project/commit/4e14b8afb44af58ab7073bb8c0b52875599b0ae1).
Commit: 92f916faba13e5cf575f6aef64405b51eaccfe9a
https://github.com/llvm/llvm-project/commit/92f916faba13e5cf575f6aef64405b51eaccfe9a
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
A llvm/include/llvm/CodeGen/DroppedVariableStatsMIR.h
A llvm/include/llvm/IR/DroppedVariableStats.h
A llvm/include/llvm/IR/DroppedVariableStatsIR.h
R llvm/include/llvm/Passes/DroppedVariableStats.h
R llvm/include/llvm/Passes/DroppedVariableStatsIR.h
M llvm/include/llvm/Passes/StandardInstrumentations.h
M llvm/lib/CodeGen/CMakeLists.txt
A llvm/lib/CodeGen/DroppedVariableStatsMIR.cpp
M llvm/lib/CodeGen/MachineFunctionPass.cpp
M llvm/lib/IR/CMakeLists.txt
A llvm/lib/IR/DroppedVariableStats.cpp
A llvm/lib/IR/DroppedVariableStatsIR.cpp
M llvm/lib/Passes/CMakeLists.txt
R llvm/lib/Passes/DroppedVariableStatsIR.cpp
M llvm/unittests/CodeGen/CMakeLists.txt
A llvm/unittests/CodeGen/DroppedVariableStatsMIRTest.cpp
Log Message:
-----------
Add a pass to collect dropped var statistics for MIR (#126686)
This patch attempts to reland
https://github.com/llvm/llvm-project/pull/120780 while addressing the
issues that caused the patch to be reverted.
Namely:
1. The patch had included code from the llvm/Passes directory in the
llvm/CodeGen directory.
2. The patch increased the backend compile time by 2% due to adding a
very expensive include in MachineFunctionPass.h
The patch has been re-structured so that there is no dependency between
the llvm/Passes and llvm/CodeGen directory, by moving the base class,
`class DroppedVariableStats` to the llvm/IR directory.
The expensive include in MachineFunctionPass.h has been changed to
contain forward declarations instead of other header includes which was
pulling a ton of code into MachineFunctionPass.h and should resolve any
issues when it comes to compile time increase.
Commit: c5a4512d853d7d2deef2080b1acb6272fa683bc3
https://github.com/llvm/llvm-project/commit/c5a4512d853d7d2deef2080b1acb6272fa683bc3
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
A llvm/test/CodeGen/AMDGPU/iglp-no-clobber.ll
Log Message:
-----------
[AMDGPU] iglp.opt does not clobber memory operands (#126976)
I think it was an accident that this wasn't included.
Commit: ceb00c07028491506bcf8e334bb12cab7792098f
https://github.com/llvm/llvm-project/commit/ceb00c07028491506bcf8e334bb12cab7792098f
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
Log Message:
-----------
[mlir][acc] Clean up TypedValue builders (#126968)
When MappableType was introduced alongside PointerLikeType, the data
clause operation builders were duplicated to accept a `TypedValue` of
one of the two type options. However, the underlying builder takes a
`Value` and this difference is not relevant for it. The only difference
is that `varType` is set differently depending on the type.
Having two duplicated builders can lead to clunky building since a
`Value` must always be cast to one of the two options. Thus, simply
clean this up - the verifier already checks that it is a type that
implements one of the two interfaces.
Commit: f3a29906aa07d08bbde7ec02b93d02e25d805110
https://github.com/llvm/llvm-project/commit/f3a29906aa07d08bbde7ec02b93d02e25d805110
Author: Nikhil Kalra <nkalra at apple.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/lib/Bytecode/Writer/BytecodeWriter.cpp
M mlir/unittests/Bytecode/BytecodeTest.cpp
Log Message:
-----------
[mlir] BytecodeWriter: invoke `reserveExtraSpace` (#126953)
Update `BytecodeWriter` to invoke `reserveExtraSpace` on the stream
before writing to it. This will give clients implementing custom output
streams the opportunity to allocate an appropriately sized buffer for
the write.
Commit: c6a39697a9334c5e159d75e45094d691a8f9db90
https://github.com/llvm/llvm-project/commit/c6a39697a9334c5e159d75e45094d691a8f9db90
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out.ll
Log Message:
-----------
[hwasan][NFCI] Add more test cases to llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out.ll (#126980)
Add more combinations of parameters to test that the skip conditions are
OR'ed together
Commit: 37952ef75f47440bc629e1a25571190f70bca09d
https://github.com/llvm/llvm-project/commit/37952ef75f47440bc629e1a25571190f70bca09d
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Passes/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
Log Message:
-----------
[gn build] Port 92f916faba13
Commit: 3e02069afe39a3c314476141b9dd90daad5803f2
https://github.com/llvm/llvm-project/commit/3e02069afe39a3c314476141b9dd90daad5803f2
Author: Nick Desaulniers <nick.desaulniers at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M libc/include/llvm-libc-macros/CMakeLists.txt
M libc/include/llvm-libc-macros/pthread-macros.h
M libc/test/integration/src/pthread/pthread_mutex_test.cpp
Log Message:
-----------
[libc][pthread] fix -Wmissing-field-initializers (#126314)
Fixes:
llvm-project/libc/test/integration/src/pthread/pthread_rwlock_test.cpp:59:29:
warning: missing field '__preference' initializer
[-Wmissing-field-initializers]
59 | pthread_rwlock_t rwlock = PTHREAD_RWLOCK_INITIALIZER;
| ^
Also, add a test that demonstrates the same issue for
PTHREAD_MUTEX_INITIALIZER, and fix that, too.
PTHREAD_ONCE_INIT does not have this issue and does have test coverage.
Commit: 31cb807537fa09b3f452ac9f93388ef202f6b4a8
https://github.com/llvm/llvm-project/commit/31cb807537fa09b3f452ac9f93388ef202f6b4a8
Author: vporpo <vporpodas at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
Log Message:
-----------
[SanbdoxVec][BottomUpVec] Fix diamond shuffle with multiple vector inputs (#126965)
When the operand comes from multiple inputs then we need additional
packing code. When the operands are scalar then we can use a single
InsertElementInst. But when the operands are vectors then we need a
chain of ExtractElementInst and InsertElementInst instructions to insert
the vector value into the destination vector. This is what this patch
implements.
Commit: dbfb29fd45a2a655e3e89b108f9a31fd764bd293
https://github.com/llvm/llvm-project/commit/dbfb29fd45a2a655e3e89b108f9a31fd764bd293
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M libcxx/docs/Hardening.rst
Log Message:
-----------
[libc++] Add a link to __builtin_verbose_trap from the hardening docs (#126930)
Commit: 5953e5a3c6e7c0d35f8b6282ba214eedd3228c40
https://github.com/llvm/llvm-project/commit/5953e5a3c6e7c0d35f8b6282ba214eedd3228c40
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M libcxx/utils/ci/run-buildbot
Log Message:
-----------
[libc++] Simplify the apple-system-hardened CI configuration (#126911)
It was basically a copy-paste of the non-hardened version of the same
job, and it's easy to remove the duplication.
Commit: 51c847d8f3d073c6d99a3dd4e6008645a8020b09
https://github.com/llvm/llvm-project/commit/51c847d8f3d073c6d99a3dd4e6008645a8020b09
Author: Amir Bishara <139038766+amirBish at users.noreply.github.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/invalid.mlir
Log Message:
-----------
[mlir][tosa]-Edit the verifier of tosa constShapeOp (#126962)
Add verification for rank 1 for the elements' attribute of the tosa
const_shape operation.
Commit: 1c207f1b6e8bba69dfbbcbd72704b4d720e363d0
https://github.com/llvm/llvm-project/commit/1c207f1b6e8bba69dfbbcbd72704b4d720e363d0
Author: vporpo <vporpodas at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/DependencyGraphTest.cpp
Log Message:
-----------
[SandboxVec][DAG] Fix DAG when old interval is mem free (#126983)
This patch fixes a bug in `DependencyGraph::extend()` when the old
interval contains no memory instructions. When this is the case we
should do a full dependency scan of the new interval.
Commit: 5586541d220ebbe27d8dea039d0165c3b2694b06
https://github.com/llvm/llvm-project/commit/5586541d220ebbe27d8dea039d0165c3b2694b06
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tensor/IR/Tensor.h
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
Log Message:
-----------
[mlir][tensor] Make useful Tensor utilities public (#126802)
1. Extract the main logic from `foldTensorCastPrecondition` into a
dedicated helper hook: `hasFoldableTensorCastOperand`. This allows
for reusing the corresponding checks.
2. Rename `getNewOperands` to `getUpdatedOperandsAfterCastOpFolding` for
better clarity and documentation of its functionality.
3. These updated hooks will be reused in:
* https://github.com/llvm/llvm-project/pull/123902. This PR makes
them public.
**Note:** Moving these hooks to `Tensor/Utils` is not feasible because
`MLIRTensorUtils` depends on `MLIRTensorDialect` (CMake targets). If
these hooks were moved to `Utils`, it would create a dependency of
`MLIRTensorDialect` on `MLIRTensorUtils`, leading to a circular
dependency.
Commit: bcba3117c057158472af83b36a38e0df0f57f4fc
https://github.com/llvm/llvm-project/commit/bcba3117c057158472af83b36a38e0df0f57f4fc
Author: Robert Imschweiler <50044286+ro-i at users.noreply.github.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id-unsupported-calling-convention.ll
Log Message:
-----------
[AMDGPU] SelDAG: fix lowering of undefined workitem intrinsics (#126058)
GlobalISel already handles undefined workitem.id.{x,y,z} intrinsics,
SelDAG failed in AMDGPUISelLowering.cpp due to a failed assertion in
`AMDGPUTargetLowering::loadInputValue`: `Arg && "Attempting to load
missing argument"`. This commit changes the behavior of SelDAG to
instead use a zero constant.
This LLVM defect was identified via the AMD Fuzzing project.
Commit: 105b3a92a72b9acdb01a9ce280a456bc4d5dce78
https://github.com/llvm/llvm-project/commit/105b3a92a72b9acdb01a9ce280a456bc4d5dce78
Author: Matthew Bastien <matthew_bastien at apple.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/package.json
M lldb/tools/lldb-dap/src-ts/debug-adapter-factory.ts
Log Message:
-----------
[lldb-dap] add `debugAdapterExecutable` property to launch configuration (#126803)
The Swift extension for VS Code requires that the `lldb-dap` executable
come from the Swift toolchain which may or may not be configured in
`PATH`. At the moment, this can be configured via LLDB DAP's extension
settings, but experience has shown that modifying other extensions'
settings on behalf of the user (especially those subject to change
whenever a new toolchain is selected) causes issues. Instead, it would
be easier to have this configurable in the launch configuration and let
the Swift extension (or any other extension that wanted to, really)
configure the path to `lldb-dap` that way. This allows the Swift
extension to have its own launch configuration type that delegates to
the LLDB DAP extension in order to provide a more seamless debugging
experience for Swift executables.
This PR adds a new property to the launch configuration object called
`debugAdapterExecutable` which allows overriding the `lldb-dap`
executable path for a specific debug session.
Commit: 6936fadfc32023a029ac7ff757bf8f40092ee2b1
https://github.com/llvm/llvm-project/commit/6936fadfc32023a029ac7ff757bf8f40092ee2b1
Author: Florian Mayer <fmayer at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_allocator_local_cache.h
Log Message:
-----------
[compiler-rt] [sanitizer] avoid UB in allocator (#126977)
Commit: 4078b11daa5b4902f59fa79c1647a20532b16c55
https://github.com/llvm/llvm-project/commit/4078b11daa5b4902f59fa79c1647a20532b16c55
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/test/Dialect/Affine/loop-fusion-4.mlir
Log Message:
-----------
[MLIR][Affine] Fix fusion crash for non-int/fp memref elt types (#126829)
Fix assumption on memref elt types being int or float during private
memref creation in affine fusion.
Fixes: https://github.com/llvm/llvm-project/issues/121020
Commit: 42382386843244cbbac0e23029e07969048e62c7
https://github.com/llvm/llvm-project/commit/42382386843244cbbac0e23029e07969048e62c7
Author: Da-Viper <57949090+Da-Viper at users.noreply.github.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/src-ts/debug-adapter-factory.ts
Log Message:
-----------
[lldb-dap] Fix: Could not find DAP in path (#126903)
Fixes #120839
Commit: 1b582ef3c0a887409b513aae282682b23c7a1a41
https://github.com/llvm/llvm-project/commit/1b582ef3c0a887409b513aae282682b23c7a1a41
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/package.json
Log Message:
-----------
[lldb-dap] Bump the version number for publishing in the Marketplace
Commit: 51d82552037290f9368a43ef7a6e4e642b8c28f4
https://github.com/llvm/llvm-project/commit/51d82552037290f9368a43ef7a6e4e642b8c28f4
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmovn.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/qshrn.ll
Log Message:
-----------
[msan] Handle Arm NEON saturating extract and narrow (#125742)
This handles NEON saturating extract and narrow (Intrinsic::aarch64_neon_{sqxtn, sqxtun, uqxtn}) by (ab)using handleShadowOr() to perform the shadow cast. Previously, these were unknown intrinsics handled suboptimally by visitInstruction.
Updates the tests from https://github.com/llvm/llvm-project/pull/125288 and https://github.com/llvm/llvm-project/pull/125140
Commit: a6f7cb54d3c268ea4748a0ff783b4b030c3195d9
https://github.com/llvm/llvm-project/commit/a6f7cb54d3c268ea4748a0ff783b4b030c3195d9
Author: Tristan Ross <tristan.ross at midstall.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/cmake/config-ix.cmake
M llvm/include/llvm/Config/config.h.cmake
M llvm/lib/Support/Unix/Process.inc
Log Message:
-----------
[Support] Prefer AUX vector for page size (#126863)
Prefers the page size to come from the AUX vector, `getpagesize` is
removed from POSIX.1-2001. Also throws in a couple asserts to ensure the
page size is a valid value.
Commit: 8421ad7f4515653001c3927734fc6204367478a0
https://github.com/llvm/llvm-project/commit/8421ad7f4515653001c3927734fc6204367478a0
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/test/Dialect/Affine/loop-fusion-2.mlir
M mlir/test/Dialect/Affine/loop-fusion-4.mlir
M mlir/test/Dialect/Affine/loop-fusion.mlir
Log Message:
-----------
[MLIR][Affine] Fix sibling fusion - missing check (#126626)
Fix sibling fusion for slice maximality check. Producer-consumer fusion
had this check but not sibling fusion. Sibling fusion shouldn't be
performed if the slice isn't "maximal" (i.e., if it isn't the whole of
the source).
Fixes: https://github.com/llvm/llvm-project/issues/48703
Commit: 3e223e3a202c046b6553aac91d79b6abd089ee8d
https://github.com/llvm/llvm-project/commit/3e223e3a202c046b6553aac91d79b6abd089ee8d
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][vector] Fix out-of-bounds access (#126734)
This PR fixes an out-of-bounds bug that occurs when there are no overlap
dimensions between the `sizes` and source of
`vector.extract_strided_slice`, causing access to `sizes` to go out of
bounds. Fixes #126196.
Commit: 8ed36373a2227c7d39fb1a520ec8dde476dc5603
https://github.com/llvm/llvm-project/commit/8ed36373a2227c7d39fb1a520ec8dde476dc5603
Author: Florian Mayer <fmayer at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M compiler-rt/lib/sanitizer_common/symbolizer/scripts/global_symbols.txt
Log Message:
-----------
[NFC] [sanitizer] allow getauxval in symbolizer
Commit: df07121d54432175ffc211d4165bfe7090c58c5e
https://github.com/llvm/llvm-project/commit/df07121d54432175ffc211d4165bfe7090c58c5e
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
Log Message:
-----------
[hwasan][NFCI] Rename ClRandomSkipRate to ClRandomKeepRate (#126990)
The meaning of ClRandomSkipRate was inverted in
https://github.com/llvm/llvm-project/pull/88070 but the variable name
was not changed. This patch fixes it to avoid confusion.
Additionally, it elaborates the flag description to mention the
interaction between the random keep rate and hotness cutoff.
Commit: 73ab0c076215125a249eee117f51f2ce4f5f9b50
https://github.com/llvm/llvm-project/commit/73ab0c076215125a249eee117f51f2ce4f5f9b50
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/package-lock.json
M lldb/tools/lldb-dap/package.json
Log Message:
-----------
[lldb-dap] Upgrade @types/node to fix TS2386 in node/module.d.ts (#126994)
Upgrade @types/node to work around an issue in TypeScript [1] that
caused our "publish to VSCode Marketplace" github action [2] to fail:
```
node_modules/@types/node/module.d.ts:290:13 - error TS2386: Overload signatures must all be optional or required.
290 resolve?(specified: string, parent?: string | URL): Promise<string>;
```
[1] https://github.com/microsoft/TypeScript/pull/59259#issuecomment-2228833941
[2] https://github.com/llvm/vscode-lldb/actions/runs/13298213337/job/37134713009
Commit: 30a9941624350523535bdec201c895698c171afd
https://github.com/llvm/llvm-project/commit/30a9941624350523535bdec201c895698c171afd
Author: Koakuma <koachan at protonmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/Driver/sparc-ias-Wa.s
Log Message:
-----------
[SPARC][IAS] Add IAS flag handling for ISA levels
Add IAS flag handling for ISA levels we support in LLVM.
Reviewers: MaskRay, rorth, brad0, s-barannikov
Reviewed By: MaskRay
Pull Request: https://github.com/llvm/llvm-project/pull/125151
Commit: 89d636ba91924c945d39f02f261863b709249744
https://github.com/llvm/llvm-project/commit/89d636ba91924c945d39f02f261863b709249744
Author: Brad Smith <brad at comstyle.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/cmake/config-ix.cmake
M llvm/include/llvm/Config/config.h.cmake
M llvm/lib/Support/Unix/Process.inc
Log Message:
-----------
[Support] Fix building on FreeBSD and OpenBSD (#127005)
Fix building after a6f7cb54d3c268ea4748a0ff783b4b030c3195d9.
Check for the function getauxval() instead of just the sys/auxv.h
header.
Commit: cdf45447ef7fe127848dc5e3144006a3391f46a3
https://github.com/llvm/llvm-project/commit/cdf45447ef7fe127848dc5e3144006a3391f46a3
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.cpp
Log Message:
-----------
Orc: Suppress a warning in #126691
Commit: 9bd836adbbb20246a5b0f08a019aa662d1c6dcd7
https://github.com/llvm/llvm-project/commit/9bd836adbbb20246a5b0f08a019aa662d1c6dcd7
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h
M utils/bazel/llvm_configs/config.h.cmake
Log Message:
-----------
[bazel] Introduce HAVE_SYS_AUXV_H for #126863
Commit: 9456e7fcdd8de6af6bcbc82c91e447729eb27af5
https://github.com/llvm/llvm-project/commit/9456e7fcdd8de6af6bcbc82c91e447729eb27af5
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.cpp
Log Message:
-----------
[ORC] Silence unused variable warnings.
Commit: 7b473dfe84c17319930d4019ab3f6ca0cfc03416
https://github.com/llvm/llvm-project/commit/7b473dfe84c17319930d4019ab3f6ca0cfc03416
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M flang/include/flang/Optimizer/OpenACC/FIROpenACCTypeInterfaces.h
M flang/include/flang/Tools/PointerModels.h
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/OpenACC/CMakeLists.txt
M flang/lib/Optimizer/OpenACC/FIROpenACCTypeInterfaces.cpp
M flang/lib/Optimizer/OpenACC/RegisterOpenACCExtensions.cpp
M flang/test/Fir/OpenACC/openacc-mappable.fir
A flang/test/Fir/OpenACC/openacc-type-categories.f90
M flang/test/lib/OpenACC/TestOpenACCInterfaces.cpp
Log Message:
-----------
[flang][acc] Implement type categorization for FIR types (#126964)
The OpenACC type interfaces have been updated to require that a type
self-identify which type category it belongs to. Ensure that FIR types
are able to provide this self identification.
In addition to implementing the new API, the PointerLikeType interface
attachment was moved to FIROpenACCSupport library like MappableType to
ensure all type interfaces and their implementation are now in the same
spot.
Commit: 1032df6f607b6bee55b5340a878dfcfc17d12653
https://github.com/llvm/llvm-project/commit/1032df6f607b6bee55b5340a878dfcfc17d12653
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Passes/PassBuilderPipelines.cpp
A llvm/test/LTO/X86/coro.ll
M llvm/test/Other/new-pm-O0-defaults.ll
M llvm/test/Other/new-pm-lto-defaults.ll
Log Message:
-----------
[LTO][Pipelines][Coro] Handle coroutines in LTO pipeline (#126168)
ThinLTO delays handling of coroutines to ThinLTO backend.
However it's usually possible to use ThinLTO prelink objects for FullLTO.
In this case we have left-over coroutines which crash in codegen.
Issue #104525.
Commit: e76739eeb952940b2979c70ba44a28fecf592695
https://github.com/llvm/llvm-project/commit/e76739eeb952940b2979c70ba44a28fecf592695
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/tools/libclang/CXString.cpp
Log Message:
-----------
[libclang] Always Dup in createRef(StringRef) (#125020)
We can't guaranty that underlying string is
0-terminated and [String.size()] is even in the
same allocation.
https://lab.llvm.org/buildbot/#/builders/94/builds/4152/steps/17/logs/stdio
```
==c-index-test==1846256==WARNING: MemorySanitizer: use-of-uninitialized-value
#0 in clang::cxstring::createRef(llvm::StringRef) llvm-project/clang/tools/libclang/CXString.cpp:96:36
#1 in DumpCXCommentInternal llvm-project/clang/tools/c-index-test/c-index-test.c:521:39
#2 in DumpCXCommentInternal llvm-project/clang/tools/c-index-test/c-index-test.c:674:7
#3 in DumpCXCommentInternal llvm-project/clang/tools/c-index-test/c-index-test.c:674:7
#4 in DumpCXComment llvm-project/clang/tools/c-index-test/c-index-test.c:685:3
#5 in PrintCursorComments llvm-project/clang/tools/c-index-test/c-index-test.c:768:7
Memory was marked as uninitialized
#0 in __msan_allocated_memory llvm-project/compiler-rt/lib/msan/msan_interceptors.cpp:1023:5
#1 in Allocate llvm-project/llvm/include/llvm/Support/Allocator.h:172:7
#2 in Allocate llvm-project/llvm/include/llvm/Support/Allocator.h:216:12
#3 in Allocate llvm-project/llvm/include/llvm/Support/AllocatorBase.h:53:43
#4 in Allocate<char> llvm-project/llvm/include/llvm/Support/AllocatorBase.h:76:29
#5 in convertCodePointToUTF8 llvm-project/clang/lib/AST/CommentLexer.cpp:42:30
#6 in clang::comments::Lexer::resolveHTMLDecimalCharacterReference(llvm::StringRef) const llvm-project/clang/lib/AST/CommentLexer.cpp:76:10
#7 in clang::comments::Lexer::lexHTMLCharacterReference(clang::comments::Token&) llvm-project/clang/lib/AST/CommentLexer.cpp:615:16
#8 in consumeToken llvm-project/clang/include/clang/AST/CommentParser.h:62:9
#9 in clang::comments::Parser::parseParagraphOrBlockCommand() llvm-project/clang/lib/AST/CommentParser.cpp
#10 in clang::comments::Parser::parseFullComment() llvm-project/clang/lib/AST/CommentParser.cpp:925:22
#11 in clang::RawComment::parse(clang::ASTContext const&, clang::Preprocessor const*, clang::Decl const*) const llvm-project/clang/lib/AST/RawCommentList.cpp:221:12
#12 in clang::ASTContext::getCommentForDecl(clang::Decl const*, clang::Preprocessor const*) const llvm-project/clang/lib/AST/ASTContext.cpp:714:35
#13 in clang_Cursor_getParsedComment llvm-project/clang/tools/libclang/CXComment.cpp:36:35
#14 in PrintCursorComments llvm-project/clang/tools/c-index-test/c-index-test.c:756:25
```
Commit: 7050e7d2a305dd2b91774e89fb028794cca63c37
https://github.com/llvm/llvm-project/commit/7050e7d2a305dd2b91774e89fb028794cca63c37
Author: sakria9 <102365810+sakria9 at users.noreply.github.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/JSONNodeDumper.h
M clang/include/clang/AST/TextNodeDumper.h
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/test/AST/ast-dump-templates.cpp
Log Message:
-----------
[clang] [ASTDump] Add support for structural value template arguments in TextNodeDumper (#126341)
It was missed in 5518a9d which introduced this new template argument kind.
Commit: ffd263306194f3d8246e2f25184a44a7f78185be
https://github.com/llvm/llvm-project/commit/ffd263306194f3d8246e2f25184a44a7f78185be
Author: AZero13 <gfunni234 at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/test/Transforms/InstCombine/ashr-lshr.ll
Log Message:
-----------
[InstCombine] Fold mul (shr exact (X, N)), 2^N + 1 -> add (X , shr exact (X, N)) (#112407)
Alive2 Proofs:
https://alive2.llvm.org/ce/z/aJnxyp
https://alive2.llvm.org/ce/z/dyeGEv
Commit: ec056f54589d937ae3f74d795b94de886cbb7ec7
https://github.com/llvm/llvm-project/commit/ec056f54589d937ae3f74d795b94de886cbb7ec7
Author: Christian Sigg <csigg at google.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h
M utils/bazel/llvm_configs/config.h.cmake
Log Message:
-----------
[llvm][bazel] Adjust to HAVE_SYS_AUXV_H > HAVE_GETAUXVAL in https://github.com/llvm/llvm-project/commit/89d636ba91924c945d39f02f261863b709249744
Commit: 9cc8442a2b438962883bbbfd8ff62ad4b1a2b95d
https://github.com/llvm/llvm-project/commit/9cc8442a2b438962883bbbfd8ff62ad4b1a2b95d
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCV.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
A llvm/lib/Target/RISCV/RISCVSchedGeneric.td
Log Message:
-----------
[RISCV][NFC] Move GenericModel to standalone file (#127003)
And fix some typos in comments.
In the future, we may add more scheduling info to GenericModel.
Commit: a472147af4adcf419cd1287f7a4707237ba7f41e
https://github.com/llvm/llvm-project/commit/a472147af4adcf419cd1287f7a4707237ba7f41e
Author: lonely eagle <2020382038 at qq.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Affine/Passes.h
M mlir/include/mlir/Dialect/Affine/Passes.td
M mlir/lib/Dialect/Affine/Transforms/LoopUnroll.cpp
M mlir/test/Dialect/Affine/unroll.mlir
M mlir/test/Dialect/SCF/loop-unroll.mlir
Log Message:
-----------
[mlir][affine]make affine-loop-unroll a FunctionOpInterface pass. (#126475)
[mlir][affine]make affine-loop-unroll a FunctionOpInterface pass
Make `affine-loop-unroll` a `FunctionOpInterface` pass.Now unroll can be
done on gpu.func.
Commit: 75c356c488bf22cb3627fbde58140f239cf6a920
https://github.com/llvm/llvm-project/commit/75c356c488bf22cb3627fbde58140f239cf6a920
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M flang/test/Fir/alloc.fir
M flang/test/Fir/arrexp.fir
M flang/test/Fir/box.fir
M flang/test/Fir/embox.fir
M flang/test/Fir/ignore-missing-type-descriptor.fir
M flang/test/Fir/polymorphic.fir
M flang/test/Fir/rebox.fir
M flang/test/Integration/OpenMP/map-types-and-sizes.f90
M flang/test/Integration/OpenMP/private-global.f90
M flang/test/Lower/OpenMP/parallel-reduction-mixed.f90
M flang/test/Lower/allocatable-polymorphic.f90
M flang/test/Lower/forall/character-1.f90
M flang/test/Lower/real-descriptors.f90
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-array-sectioning-host.mlir
M mlir/test/Target/LLVMIR/omptarget-constant-indexing-device-region.mlir
M mlir/test/Target/LLVMIR/omptarget-fortran-common-block-host.mlir
M mlir/test/Target/LLVMIR/omptarget-record-type-with-ptr-member-host.mlir
M mlir/test/Target/LLVMIR/openmp-private.mlir
Log Message:
-----------
[MLIR][LLVMIR] Always use TargetFolder in IRBuilder (#126929)
This is a followup to https://github.com/llvm/llvm-project/pull/126745,
generalizing it to always use TargetFolder, including inside function
bodies.
This avoids generating non-canonical constant expressions that can be
folded away.
Commit: 672e3858a4e4b9e155adb72426074ea2af0dd922
https://github.com/llvm/llvm-project/commit/672e3858a4e4b9e155adb72426074ea2af0dd922
Author: Takuto Ikuta <tikuta at google.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M libcxx/include/__vector/vector_bool.h
Log Message:
-----------
[libcxx] Add a missing include for __bit_iterator (#127015)
This is to fix compile error with explicit Clang modules like
```
../../third_party/libc++/src/include/__vector/vector_bool.h:85:11: error: default argument of '__bit_iterator' must be imported from module 'std.bit_reference_fwd' before it is required
85 | typedef __bit_iterator<vector, false> pointer;
| ^
../../third_party/libc++/src/include/__fwd/bit_reference.h:23:68: note: default argument declared here is not reachable
23 | template <class _Cp, bool _IsConst, typename _Cp::__storage_type = 0>
| ^
```
Commit: 0761841bc000ce3206e043d25eb45e87d6dab0d4
https://github.com/llvm/llvm-project/commit/0761841bc000ce3206e043d25eb45e87d6dab0d4
Author: Takuto Ikuta <tikuta at google.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M libcxx/include/__filesystem/path.h
Log Message:
-----------
[libcxx] Add a missing include for __enable_if_t (#127016)
This is to fix compile error with explicit Clang modules like
```
../../third_party/libc++/src/include/__filesystem/path.h:80:26: error: declaration of '__enable_if_t' must be imported from module 'std_core.type_traits.enable_if' before it is required
80 | template <class _ECharT, __enable_if_t<__can_convert_char<_ECharT>::value, int> = 0>
| ^
../../third_party/libc++/src/include/__type_traits/enable_if.h:34:1: note: declaration here is not visible
34 | using __enable_if_t _LIBCPP_NODEBUG = typename enable_if<_Bp, _Tp>::type;
| ^
```
Commit: 70b994bcfaafadd649818d2a7f90f8f5989ec6c1
https://github.com/llvm/llvm-project/commit/70b994bcfaafadd649818d2a7f90f8f5989ec6c1
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp
M lldb/test/Shell/SymbolFile/DWARF/x86/simplified-template-names.cpp
Log Message:
-----------
[lldb/DWARF] Resolve type unit references in llvm DWARFDIE compatibility wrappers (#126902)
The llvm versions of these functions do that, so we must to so as well.
Practically this meant that were were unable to correctly un-simplify
the names of some types when using type units, which resulted in type
lookup errors.
Commit: 3bf425764e1837e909263a7e61a13e2308dc7d5f
https://github.com/llvm/llvm-project/commit/3bf425764e1837e909263a7e61a13e2308dc7d5f
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M flang/test/Lower/common-block.f90
M flang/test/Lower/real-descriptors.f90
Log Message:
-----------
[flang] Update f128 tests
Update test that require flang-supports-f128-math after #126929.
Commit: ee655ca27aad466bcc54f6eba03f7e564940ad5a
https://github.com/llvm/llvm-project/commit/ee655ca27aad466bcc54f6eba03f7e564940ad5a
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang/test/CodeGen/allow-ubsan-check.c
M clang/test/CodeGenCXX/RelativeVTablesABI/dynamic-cast.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/type-info.cpp
M clang/test/CodeGenOpenCL/amdgcn-buffer-rsrc-type.cl
M clang/test/CodeGenOpenCL/as_type.cl
M llvm/include/llvm/Analysis/CaptureTracking.h
M llvm/include/llvm/Support/ModRef.h
M llvm/lib/Analysis/CaptureTracking.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/test/Transforms/FunctionAttrs/2009-01-02-LocalStores.ll
M llvm/test/Transforms/FunctionAttrs/arg_returned.ll
M llvm/test/Transforms/FunctionAttrs/nocapture.ll
M llvm/test/Transforms/FunctionAttrs/nonnull.ll
M llvm/test/Transforms/FunctionAttrs/noundef.ll
M llvm/test/Transforms/FunctionAttrs/readattrs.ll
M llvm/test/Transforms/FunctionAttrs/stats.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/block_scaling_decompr_8bit.ll
M llvm/test/Transforms/PhaseOrdering/bitcast-store-branch.ll
M llvm/test/Transforms/PhaseOrdering/dce-after-argument-promotion-loads.ll
M llvm/test/Transforms/PhaseOrdering/enable-loop-header-duplication-oz.ll
M llvm/unittests/Analysis/CaptureTrackingTest.cpp
Log Message:
-----------
[CaptureTracking][FunctionAttrs] Add support for CaptureInfo (#125880)
This extends CaptureTracking to support inferring non-trivial
CaptureInfos. The focus of this patch is to only support FunctionAttrs,
other users of CaptureTracking will be updated in followups.
The key API changes here are:
* DetermineUseCaptureKind() now returns a UseCaptureInfo where the UseCC
component specifies what is captured at that Use and the ResultCC
component specifies what may be captured via the return value of the
User. Usually only one or the other will be used (corresponding to
previous MAY_CAPTURE or PASSTHROUGH results), but both may be set for
call captures.
* The CaptureTracking::captures() extension point is passed this
UseCaptureInfo as well and then can decide what to do with it by
returning an Action, which is one of: Stop: stop traversal.
ContinueIgnoringReturn: continue traversal but don't follow the
instruction return value. Continue: continue traversal and follow the
instruction return value if it has additional CaptureComponents.
For now, this patch retains the (unsound) special logic for comparison
of null with a dereferenceable pointer. I'd like to switch key code to
take advantage of address/address_is_null before dropping it.
This PR mainly intends to introduce necessary API changes and basic
inference support, there are various possible improvements marked with
TODOs.
Commit: df62441336ffaa42c8f9d743194ac15f4bf01ec0
https://github.com/llvm/llvm-project/commit/df62441336ffaa42c8f9d743194ac15f4bf01ec0
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/lib/CodeGen/MachineScheduler.cpp
Log Message:
-----------
[MISched][NFC] Remove unused heuristic NextDefUse from enum (#125879)
Heuristic was removed in 46533e614b78 due to being ineffective.
Commit: 9b2fc66830b2e81d95ef272ddc51c6cff9ba23a1
https://github.com/llvm/llvm-project/commit/9b2fc66830b2e81d95ef272ddc51c6cff9ba23a1
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SDAG] Harden assumption in getMemsetStringVal (#126207)
In 5235973ee03aca4148ecabe5eff64da2af1e034e, an ICE was fixed in
getMemsetStringVal where f128 wasn't handled. It was noted at the time
[1] that the code below this also looks suspect, since it assumes the
element type of VT is either an f32 or f64.
This part of getMemsetStringVal relates to memcpy operations where the
source is a copy from a zero constant. The VT in question is determined
by TargetLowering::findOptimalMemOpLowering, which in turn calls a
further TLI hook getOptimalMemOpType.
For AArch64, getOptimalMemOpType returns either a v16i8, f128, i64, i32
or Other. For Other, TargetLowering::findOptimalMemOpLowering will then
pick an integer VT. So on AArch64 at least, I don't believe the suspect
code can be reached.
For other targets, ARM and x86 are the only ones that return a FP vector
type from getOptimalMemOpType. For both targets, the only such type is
v2f64, but given f64 is already handled it should also be fine.
To defend this, I considered adding an assert as mentioned in [1], but
given getConstantFP handles vector types, I figured using this to fully
handle the FP types makes the code simpler and more robust.
For test coverage I added unreachables to both of the branches handling
FP types in this code, but found neither fired with check-llvm across
all targets.
Test coverage was added to llvm/test/CodeGen/AArch64/memcpy-f128.ll in
5235973ee03aca4148ecabe5eff64da2af1e034e to defend ICE on f128, but at
some point it stopped hitting this code.
AArch64TargetLowering::getOptimalMemOpType was updated in
29200611055f49a0d37243caa5f8bba1df9d57a6, so I suspect this is when it
happened, although I haven't verified this. Although I did find by
updating the test to disable NEON, getOptimalMemOpType returns an f128
and the branch is once again hit.
For the final branch noted as suspect in [1], as far as I can tell this
has never had any test coverage, so I've added a test to the ARM backend
for this.
Fixes: https://github.com/llvm/llvm-project/issues/20521 [1]
Commit: 213917be82e3cd57c74afc836377a746be45dafd
https://github.com/llvm/llvm-project/commit/213917be82e3cd57c74afc836377a746be45dafd
Author: Matthias Springer <me at m-sp.org>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
R mlir/docs/BufferDeallocationInternals.md
M mlir/docs/OwnershipBasedBufferDeallocation.md
R mlir/docs/includes/img/branch_example_post_move.svg
R mlir/docs/includes/img/branch_example_pre_move.svg
R mlir/docs/includes/img/nested_branch_example_post_move.svg
R mlir/docs/includes/img/nested_branch_example_pre_move.svg
R mlir/docs/includes/img/region_branch_example_pre_move.svg
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.h
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.td
R mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocation.cpp
M mlir/lib/Dialect/Bufferization/Transforms/CMakeLists.txt
R mlir/test/Dialect/Bufferization/Transforms/buffer-deallocation.mlir
M mlir/test/Pass/pipeline-invalid.mlir
Log Message:
-----------
[mlir][bufferization] Remove `buffer-deallocation` pass (#126366)
The `-buffer-deallocation` pass is not compatible with One-Shot
Bufferize and has been replaced with the Ownership-based Buffer
Deallocation pass about 1.5 years ago. To clean up the code base, this
commit removes the deprecated `buffer-deallocation` pass. All uses of
this deprecated pass within MLIR have already been migrated.
Note for LLVM integration: If you depend on this pass, migrate to the
Ownership-based Buffer Deallocation pass or copy the pass to your
codebase. For details, see
https://discourse.llvm.org/t/psa-bufferization-new-buffer-deallocation-pipeline/73375.
Commit: cd21e0f08b65512858bd6067681ce2ce254b0188
https://github.com/llvm/llvm-project/commit/cd21e0f08b65512858bd6067681ce2ce254b0188
Author: Christian Sigg <csigg at google.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Port a472147af4ad
Commit: 298caebaadc38eadced7175c80ed6b2866755cb9
https://github.com/llvm/llvm-project/commit/298caebaadc38eadced7175c80ed6b2866755cb9
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M lldb/source/Symbol/Block.cpp
M lldb/test/Shell/ScriptInterpreter/Python/sb_function_ranges.s
Log Message:
-----------
[lldb] Fix Block::GetRangeIndexContainingAddress for discontinuous functions (#124931)
This is a followup to #122440, which changed function-relative
calculations to use the function entry point rather than the lowest
address of the function (but missed this usage). Like in #116777, the
logic is changed to use file addresses instead of section offsets (as
not all parts of the function have to be in the same section).
Commit: 308ce8d5240875911987b63fa6579c87758ab4ac
https://github.com/llvm/llvm-project/commit/308ce8d5240875911987b63fa6579c87758ab4ac
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMCallingConv.cpp
M llvm/lib/Target/ARM/ARMCallingConv.td
M llvm/lib/Target/ARM/ARMISelLowering.cpp
A llvm/test/CodeGen/Thumb2/bf16-pcs.ll
A llvm/test/CodeGen/Thumb2/fp16-pcs.ll
Log Message:
-----------
[ARM] Fix calling convention for __fp16 with big-endian (#126741)
AAPCS32 defines the fp16 and bf16 types as being passed as if they were
extended to 32 bits, with the high 16 bits being unspecified. The
extension is specified as happening as-if it was done in a register,
which means that for big endian targets, the actual value gets passed in
the higher addressed half of the stack slot, instead of the lower
addressed half as for little endian. Previously, for targets with the
fp16 extension, we were passing these types as a 16 bit stack slot,
which worked for little endian because every later stack slot would be
4-byte aligned leaving the 2 byte gap, but was incorrect for big endian.
Commit: b7baf2ee8d302aab7cae787645ee7b7ec107e3ee
https://github.com/llvm/llvm-project/commit/b7baf2ee8d302aab7cae787645ee7b7ec107e3ee
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/IR/Constants.cpp
M llvm/test/Transforms/InstCombine/add2.ll
M llvm/test/Transforms/NewGVN/2009-11-12-MemDepMallocBitCast.ll
Log Message:
-----------
[IR] Mark mul constant expression as undesirable
This is a (very belated) reland of 0a362f12ec60a49a054befec8620a8e69523af54,
which I originally reverted due to flang test failures.
This marks mul constant expressions as undesirable, which means that
we will no longer create them by default, but they can still be
created explicitly.
Part of:
https://discourse.llvm.org/t/rfc-remove-most-constant-expressions/63179
Commit: d44d806faa879dfb7a7ceb58beeb57cf8d5af430
https://github.com/llvm/llvm-project/commit/d44d806faa879dfb7a7ceb58beeb57cf8d5af430
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/MC/AArch64/armv8.1a-lse.s
M llvm/test/MC/AArch64/armv9.6a-lsui.s
Log Message:
-----------
[LLVM][AArch64] Remove aliases of LSUI instructions (#126072)
Removes MnemonicAliases added for instructions available with
the LSUI feature (e.g. CAS -> CAST) which are not equivalent.
The aliases stt[add|clr|set]a & stt[add|clr|set]al are also removed.
Commit: 4ac1c58a77fb6983e55a4f41f4b0ff97f431ffdf
https://github.com/llvm/llvm-project/commit/4ac1c58a77fb6983e55a4f41f4b0ff97f431ffdf
Author: Victor Guerra <vguerra at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M mlir/lib/IR/AsmPrinter.cpp
Log Message:
-----------
[mlir][NFC] Add missing `)` in doc for `--mlir-print-local-scope` (#125721)
Signed-off-by: Victor Guerra <vguerra at gmail.com>
Commit: 9d92bea507be19f4a3dba6107aa5eeb6e95a2765
https://github.com/llvm/llvm-project/commit/9d92bea507be19f4a3dba6107aa5eeb6e95a2765
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
Log Message:
-----------
[MLIR][LLVMIR] Fix use-after-move
Fix an issue introduced in #126929: The LLVM module is moved into
the ModuleTranslator, so query the DataLayout from there.
Commit: 48897774a5accdd33fcb6d7a7b698a61c96006ed
https://github.com/llvm/llvm-project/commit/48897774a5accdd33fcb6d7a7b698a61c96006ed
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
Log Message:
-----------
TableGen: Add missing consts to CodeGenSubRegIndex
Commit: 3ad8657ff60b9967235ad65fdb8b767aae0e799d
https://github.com/llvm/llvm-project/commit/3ad8657ff60b9967235ad65fdb8b767aae0e799d
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M lldb/include/lldb/API/SBTarget.h
M lldb/include/lldb/API/SBType.h
M lldb/include/lldb/API/SBValue.h
M lldb/source/API/SBType.cpp
M lldb/test/API/lang/cpp/class-template-parameter-pack/TestTemplatePackArgs.py
M lldb/test/API/lang/cpp/template-arguments/Makefile
M lldb/test/API/lang/cpp/template-arguments/TestCppTemplateArguments.py
M lldb/test/API/lang/cpp/template-arguments/main.cpp
Log Message:
-----------
[lldb][SBAPI] Add new SBType::GetTemplateParameterValue API (#126901)
This patch adds a new API to `SBType` to retrieve the value of a
template parameter given an index. We re-use the
`TypeSystemClang::GetIntegralTemplateArgument` for this and thus
currently only supports integral non-type template parameters. Types
like float/double are not supported yet.
rdar://144395216
Commit: b88c5d638a00d723f521c907911e42115717937e
https://github.com/llvm/llvm-project/commit/b88c5d638a00d723f521c907911e42115717937e
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang/test/Analysis/live-stmts.cpp
Log Message:
-----------
[analyzer] Disable a flaky test while triaging why its flaky (#127034)
I had previous attempts for fixing this flaky test. Let's admit I failed
so far, and disable this until we have a permanent fix.
See the discussion at:
https://github.com/llvm/llvm-project/pull/126913#issuecomment-2655850766
Commit: 3be48a6f809afccc9bcddc8cf94492812b49e1f7
https://github.com/llvm/llvm-project/commit/3be48a6f809afccc9bcddc8cf94492812b49e1f7
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Frontend/PrintPreprocessedOutput.cpp
M clang/test/Preprocessor/embed_preprocess_to_file.c
Log Message:
-----------
[clang] Fix preprocessor output from #embed (#126742)
When bytes with negative signed char values appear in the data, make
sure to use raw bytes from the data string when preprocessing, not char
values.
Fixes https://github.com/llvm/llvm-project/issues/102798
Commit: 6c5a0086d15e28a39fb8e9ae768a5c3b55c210ae
https://github.com/llvm/llvm-project/commit/6c5a0086d15e28a39fb8e9ae768a5c3b55c210ae
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
Log Message:
-----------
AMDGPU: Add more tests for peephole opt subregister composing
Commit: 499d6da3bb2c967abda298518dc22b7baf084a9e
https://github.com/llvm/llvm-project/commit/499d6da3bb2c967abda298518dc22b7baf084a9e
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
M lldb/source/Symbol/SymbolContext.cpp
M lldb/test/Shell/Commands/command-disassemble.s
Log Message:
-----------
[lldb] Correctly resolve (discontinuous) function offsets when disassembling (#126925)
We need to iterate through the all symbol context ranges returned by
(since #126505) SymbolContext::GetAddressRange. This also includes a fix
to print the function offsets as signed values.
I've also wanted to check that the addresses which are in the middle of
the function do *not* resolve to the function, but that's not entirely
the case right now. This appears to be a separate issue though, so I've
just left a TODO for now.
Commit: 9c89faa62bbf71b1e634a993983cef5507aab249
https://github.com/llvm/llvm-project/commit/9c89faa62bbf71b1e634a993983cef5507aab249
Author: Nicholas Guy <nicholas.guy at arm.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
A llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
Log Message:
-----------
[LoopVectorizer][AArch64] Add support for partial reduce subtraction (#123636)
Commit: 1083ec647f16314bcc9af8c4d6b11f50d288bca6
https://github.com/llvm/llvm-project/commit/1083ec647f16314bcc9af8c4d6b11f50d288bca6
Author: Harald van Dijk <harald.vandijk at codeplay.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
M llvm/include/llvm/IR/DIBuilder.h
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
M llvm/unittests/IR/IRBuilderTest.cpp
M llvm/unittests/Transforms/Utils/CloningTest.cpp
Log Message:
-----------
[reland][DebugInfo] Update DIBuilder insertion to take InsertPosition (#126967)
After #124287 updated several functions to return iterators rather than
Instruction *, it was no longer straightforward to pass their result to
DIBuilder. This commit updates DIBuilder methods to accept an
InsertPosition instead, so that they can be called with an iterator
(preferred), or with a deprecation warning an Instruction *, or a
BasicBlock *. This commit also updates the existing calls to the
DIBuilder methods to pass in iterators.
As a special exception, DIBuilder::insertDeclare() keeps a separate
overload accepting a BasicBlock *InsertAtEnd. This is because despite
the name, this method does not insert at the end of the block, therefore
this cannot be handled implicitly by using InsertPosition.
Commit: 0b0f3da6a82f201619ecde4b8a297a179d7245a7
https://github.com/llvm/llvm-project/commit/0b0f3da6a82f201619ecde4b8a297a179d7245a7
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/dumpcode.ll
Log Message:
-----------
[AMDGPU] Add a regression test for -mattr=dumpcode (#116982)
Commit: eef02053459a0eb3076b0db76555f9836ac90b07
https://github.com/llvm/llvm-project/commit/eef02053459a0eb3076b0db76555f9836ac90b07
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/reg-sequence-like-v-pk-mov-b32.mir
Log Message:
-----------
AMDGPU: Add baseline test for treating v_pk_mov_b32 like reg_sequence (#125656)
Commit: ff585feacf58b384d7525d2b1368298435132fb4
https://github.com/llvm/llvm-project/commit/ff585feacf58b384d7525d2b1368298435132fb4
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/AsmParser/LLToken.h
M llvm/include/llvm/Support/ModRef.h
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/IR/Attributes.cpp
M llvm/lib/Support/ModRef.cpp
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/lib/Transforms/IPO/SCCP.cpp
M llvm/test/Assembler/memory-attribute-errors.ll
M llvm/test/Assembler/memory-attribute.ll
A llvm/test/Bitcode/Inputs/memory-attribute-upgrade.bc
A llvm/test/Bitcode/memory-attribute-upgrade.ll
M llvm/unittests/Support/ModRefTest.cpp
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[IR][ModRef] Introduce `errno` memory location
Model C/C++ `errno` macro by adding a corresponding `errno`
memory location kind to the IR. Preliminary work to separate
`errno` writes from other memory accesses, to the benefit of
alias analyses and optimization correctness.
Previous discussion: https://discourse.llvm.org/t/rfc-modelling-errno-memory-effects/82972.
Commit: b963d3768c0e88d2cac043d4754ce90a19a7e1ec
https://github.com/llvm/llvm-project/commit/b963d3768c0e88d2cac043d4754ce90a19a7e1ec
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/test/SemaCXX/cxx20-ctad-type-alias.cpp
Log Message:
-----------
[clang] CTAD: Remove an incorrect assertion in BuildDeductionGuideForTypeAlias (#126532)
Fixes #125821
The assertion was too strict, as Clang can reach this code path when
recursively generating deduction guides for alias templates. See the
detailed explanation
[here](https://github.com/llvm/llvm-project/issues/125821#issuecomment-2639130893).
No release notes needed, as there is no behavior change in release
builds.
Commit: bfd3e25fddddde2e541dad4616350ce72cd9eeed
https://github.com/llvm/llvm-project/commit/bfd3e25fddddde2e541dad4616350ce72cd9eeed
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
Log Message:
-----------
[flang][debug] Allow variable from non-entry blocks. (#125692)
We currently drop the `DeclareOp` which are not in the entry block of
the function. This was done to side step a problem with the variables in
OpenMP target region. Now that issue has been addressed in #118314 so we
can lift this restriction as well.
Commit: 6a59d60e2b902a750d769d6198efb51e3ce88e70
https://github.com/llvm/llvm-project/commit/6a59d60e2b902a750d769d6198efb51e3ce88e70
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
A llvm/test/Transforms/FunctionAttrs/sendmsg-nocallback.ll
Log Message:
-----------
AMDGPU: Mark sendmsg intrinsics as nocallback (#126782)
These can be nocallback, but no nosync. These return in the current
thread immediately, but may send a signal to the host, which could
trigger
the async execution of code in the module.
Fixes #124802
Commit: 8327c2cfdb9440d9b4cce7eb49693a895a674a9f
https://github.com/llvm/llvm-project/commit/8327c2cfdb9440d9b4cce7eb49693a895a674a9f
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/test/Analysis/LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll
M llvm/test/Analysis/LoopAccessAnalysis/non-constant-distance-backward.ll
Log Message:
-----------
LAA: fix logic for MaxTargetVectorWidth (#125487)
Uses the fixed register width if scalable vectorization is not enabled
(via TargetTransformInfo::enableScalableVectorization) and improves
results if there are scalable vector registers, but they shouldn't be
used.
Commit: 4c5609686b101154a7ef20b775dcc40b901cd116
https://github.com/llvm/llvm-project/commit/4c5609686b101154a7ef20b775dcc40b901cd116
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] Fix shadow variable warning. NFC.
Repeated Ops variable.
Commit: 6fb1d40992ac3aff84dfe7616ea7776e1c26ba99
https://github.com/llvm/llvm-project/commit/6fb1d40992ac3aff84dfe7616ea7776e1c26ba99
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td
Log Message:
-----------
[mlir][spirv] Update example of `spirv.Constant`(NFC) (#127030)
Actually the `spirv.Constant dense<[2, 3]> : vector<2xf32>` will cause a
error:
```
error: unexpected decimal integer literal for a floating point value
%cst = spirv.Constant dense<[2, 3]> : vector<2xf32>
^
```
The value should be an explicit float.
Commit: 1935f84856a9297e725770e6f4b9c50fbcec365c
https://github.com/llvm/llvm-project/commit/1935f84856a9297e725770e6f4b9c50fbcec365c
Author: s-watanabe314 <watanabe.shu-06 at fujitsu.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
A mlir/include/mlir/Conversion/ComplexCommon/DivisionConverter.h
M mlir/include/mlir/Conversion/ComplexToLLVM/ComplexToLLVM.h
M mlir/include/mlir/Conversion/ComplexToStandard/ComplexToStandard.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/Complex/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/Complex/IR/Complex.h
M mlir/include/mlir/Dialect/Complex/IR/ComplexBase.td
M mlir/lib/Conversion/CMakeLists.txt
A mlir/lib/Conversion/ComplexCommon/CMakeLists.txt
A mlir/lib/Conversion/ComplexCommon/DivisionConverter.cpp
M mlir/lib/Conversion/ComplexToLLVM/CMakeLists.txt
M mlir/lib/Conversion/ComplexToLLVM/ComplexToLLVM.cpp
M mlir/lib/Conversion/ComplexToStandard/CMakeLists.txt
M mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp
A mlir/test/Conversion/ComplexToLLVM/complex-range-option.mlir
M mlir/test/Conversion/ComplexToLLVM/convert-to-llvm.mlir
M mlir/test/Conversion/ComplexToLLVM/full-conversion.mlir
A mlir/test/Conversion/ComplexToStandard/complex-range-option.mlir
Log Message:
-----------
[mlir][complex] Add complex-range option and select complex division … (#127010)
…algorithm
This patch adds the `complex-range` option and two calculation methods
for complex number division (algebraic method and Smith's algorithm) to
both the `ComplexToLLVM` and `ComplexToStandard` passes, allowing the
calculation method to be controlled by the option.
See also the discussion in the following discourse post.
https://discourse.llvm.org/t/question-and-proposal-regarding-complex-number-division-algorithm-in-the-complex-dialect/83772
Commit: cf69b4c66898cab9eb0f745f034eaf5b3ffcee0d
https://github.com/llvm/llvm-project/commit/cf69b4c66898cab9eb0f745f034eaf5b3ffcee0d
Author: Zahira Ammarguellat <zahira.ammarguellat at intel.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang/bindings/python/clang/cindex.py
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang-c/Index.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/StmtOpenMP.h
M clang/include/clang/Basic/StmtNodes.td
M clang/include/clang/Sema/SemaOpenMP.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/lib/AST/StmtOpenMP.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/Basic/OpenMPKinds.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/SemaExceptionSpec.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
A clang/test/Index/openmp-stripe.c
A clang/test/OpenMP/stripe_ast_print.cpp
A clang/test/OpenMP/stripe_codegen.cpp
A clang/test/OpenMP/stripe_messages.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CXCursor.cpp
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[Clang] [OpenMP] Add support for '#pragma omp stripe'. (#126927)
This patch was reviewed and approved here:
https://github.com/llvm/llvm-project/pull/119891
However it has been reverted here:
https://github.com/alejandro-alvarez-sonarsource/llvm-project/commit/083df25dc256154cccbc0e127d79fbac4d0583c5
due to a build issue here:
https://lab.llvm.org/buildbot/#/builders/51/builds/10694
This patch is reintroducing the support.
Commit: e657b96cd89d5a861dd5792e6c067eab405d6033
https://github.com/llvm/llvm-project/commit/e657b96cd89d5a861dd5792e6c067eab405d6033
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
Log Message:
-----------
[X86] Fold EXTRACT_SUBVECTOR(VPERMV(V,M),C) -> EXTRACT_SUBVECTOR(VPERMV(V,M'),0)
Similar to what we already do for VPERMV3, we can fold the non-zero-idx EXTRACT_SUBVECTOR into the shuffle mask and use a free EXTRACT_SUBVECTOR(V,0) instead
Commit: 46ffacc2ddf2737b8ec19d3d6584ae7e3d5e04fe
https://github.com/llvm/llvm-project/commit/46ffacc2ddf2737b8ec19d3d6584ae7e3d5e04fe
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M flang/lib/Parser/prescan.cpp
M flang/test/Parser/OpenMP/sentinels.f
Log Message:
-----------
[flang][OpenMP] Skip invalid conditional compilation sentinels (#126282)
In fixed form, an initial line can have an OpenMP conditional
compilation sentinel only if columns 3 through 5 have only
white space or numbers.
Fixes https://github.com/llvm/llvm-project/issues/89560
Commit: 60493ede24a758771a0b34067a30ceb929525b73
https://github.com/llvm/llvm-project/commit/60493ede24a758771a0b34067a30ceb929525b73
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang/tools/c-index-test/c-index-test.c
Log Message:
-----------
[NFC] format c-index-test.c
to separate formatting changes from a functional fix later
also inlcude CXDiagnostic and CXFile
Commit: 873aa29945efa3dcbb57b73737a766cc180e4bf5
https://github.com/llvm/llvm-project/commit/873aa29945efa3dcbb57b73737a766cc180e4bf5
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M .github/workflows/release-asset-audit.py
Log Message:
-----------
[GitHub] Make release audit more strict for LLVM 19 and beyond (#125841)
Before 19, we had releases from release managers, the bot, and community
members. 19 started to restrict this, with only select community members
uploading releases. The lists of users are written out each time to make
modifying this easier.
If we cannot parse the release number, I've made it raise an issue
saying so. Since this may also be a sign of a malicious action.
Commit: e8dba3a4ffd88c9b6881308c98530e6af7a70763
https://github.com/llvm/llvm-project/commit/e8dba3a4ffd88c9b6881308c98530e6af7a70763
Author: Qi Zhao <zhaoqi01 at loongson.cn>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/test/CodeGen/LoongArch/statepoint-call-lowering.ll
Log Message:
-----------
[LoongArch] Add test for stackmaps. NFC
Commit: 6fa671f9e69232bb6a84ec81608131b0b111dbdf
https://github.com/llvm/llvm-project/commit/6fa671f9e69232bb6a84ec81608131b0b111dbdf
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/test/Dialect/Affine/loop-fusion-4.mlir
Log Message:
-----------
[MLIR][Affine] Fix fusion crash from memory space int assumption (#127032)
Fix fusion crash from memory space int assumption from assumption on int
attr-based memory spaces.
Fixes: https://github.com/llvm/llvm-project/issues/118759
Commit: 43780f4f9256117f73bc89cde968b9e757734ddc
https://github.com/llvm/llvm-project/commit/43780f4f9256117f73bc89cde968b9e757734ddc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegAllocGreedy.h
Log Message:
-----------
RegAllocGreedy: Use Register type
Commit: 1e64ea9914d3cc839b52e50d2d497600e03c8b6e
https://github.com/llvm/llvm-project/commit/1e64ea9914d3cc839b52e50d2d497600e03c8b6e
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang/test/CodeGen/allow-ubsan-check.c
M clang/test/CodeGenCXX/RelativeVTablesABI/dynamic-cast.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/type-info.cpp
M clang/test/CodeGenOpenCL/amdgcn-buffer-rsrc-type.cl
M clang/test/CodeGenOpenCL/as_type.cl
M llvm/include/llvm/Analysis/CaptureTracking.h
M llvm/include/llvm/Support/ModRef.h
M llvm/lib/Analysis/CaptureTracking.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/test/Transforms/FunctionAttrs/2009-01-02-LocalStores.ll
M llvm/test/Transforms/FunctionAttrs/arg_returned.ll
M llvm/test/Transforms/FunctionAttrs/nocapture.ll
M llvm/test/Transforms/FunctionAttrs/nonnull.ll
M llvm/test/Transforms/FunctionAttrs/noundef.ll
M llvm/test/Transforms/FunctionAttrs/readattrs.ll
M llvm/test/Transforms/FunctionAttrs/stats.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/block_scaling_decompr_8bit.ll
M llvm/test/Transforms/PhaseOrdering/bitcast-store-branch.ll
M llvm/test/Transforms/PhaseOrdering/dce-after-argument-promotion-loads.ll
M llvm/test/Transforms/PhaseOrdering/enable-loop-header-duplication-oz.ll
M llvm/unittests/Analysis/CaptureTrackingTest.cpp
Log Message:
-----------
Revert "[CaptureTracking][FunctionAttrs] Add support for CaptureInfo (#125880)"
This reverts commit ee655ca27aad466bcc54f6eba03f7e564940ad5a.
A miscompilation has been reported at:
https://github.com/llvm/llvm-project/pull/125880#issuecomment-2656632577
Commit: 27e78e68a6788a08ea591250b6600284b360cff2
https://github.com/llvm/llvm-project/commit/27e78e68a6788a08ea591250b6600284b360cff2
Author: Jan Voung <jvoung at google.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang/include/clang/Analysis/FlowSensitive/CachedConstAccessorsLattice.h
M clang/unittests/Analysis/FlowSensitive/CachedConstAccessorsLatticeTest.cpp
Log Message:
-----------
[clang][dataflow] Remove a deprecated CachedConstAccessorsLattice API (#127001)
We've already migrated known users from the old to the new version of
getOrCreateConstMethodReturnStorageLocation. The conversion is pretty
straightforward as well, if there are out-of-tree users:
Previously: use CallExpr as argument
New: get the direct Callee from CallExpr, null check, and use that as
the argument instead.
Commit: f6e3d33c009cada0437c11d3fd1beace74c5dcfa
https://github.com/llvm/llvm-project/commit/f6e3d33c009cada0437c11d3fd1beace74c5dcfa
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/HIPSPV.cpp
M clang/lib/Driver/ToolChains/SPIRVOpenMP.cpp
M clang/test/Driver/amdgpu-openmp-toolchain.c
Log Message:
-----------
[Clang][NFC] Introduce `--offloadlib` positive flag for `nogpulib` and alias to `--no-offloadlib` (#126567)
Summary:
We support `nogpulib` to disable implicit libraries. In the future we
will want to change the default linking of these libraries based on the
user language. This patch just introduces a positive variant so now we
can do `-nogpulib -gpulib` to disable it.
Later patch will make the default a variable in the ROCmToolChain
depending on the target languages.
Commit: 7763119c6eb0976e4836f81c9876c49a36d46d73
https://github.com/llvm/llvm-project/commit/7763119c6eb0976e4836f81c9876c49a36d46d73
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/PowerPC/PPCRegisterInfo.h
M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
M llvm/test/CodeGen/PowerPC/adde_return_type.ll
M llvm/test/CodeGen/PowerPC/addegluecrash.ll
M llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
M llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
M llvm/test/CodeGen/PowerPC/aix-cc-byval-split.ll
M llvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll
M llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-longlong.ll
M llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large32.ll
M llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/PowerPC/cvt_i64_to_fp.ll
M llvm/test/CodeGen/PowerPC/inc-of-add.ll
M llvm/test/CodeGen/PowerPC/pr35688.ll
M llvm/test/CodeGen/PowerPC/pr36292.ll
M llvm/test/CodeGen/PowerPC/pr40922.ll
M llvm/test/CodeGen/PowerPC/pr45448.ll
M llvm/test/CodeGen/PowerPC/sat-add.ll
M llvm/test/CodeGen/PowerPC/select.ll
M llvm/test/CodeGen/PowerPC/uaddo-32.ll
M llvm/test/CodeGen/PowerPC/uaddo-64.ll
M llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll
Log Message:
-----------
[PowerPC] Deprecate uses of ISD::ADDC/ISD::ADDE/ISD::SUBC/ISD::SUBE (#116984)
ISD::ADDC, ISD::ADDE, ISD::SUBC and ISD::SUBE are being deprecated,
using ISD::UADDO_CARRY,ISD::USUBO_CARRY instead. Lowering the UADDO,
UADDO_CARRY, USUBO, USUBO_CARRY in the patch.
Commit: f63e3b15f90e17a3708adda0a0b3ea180a41501b
https://github.com/llvm/llvm-project/commit/f63e3b15f90e17a3708adda0a0b3ea180a41501b
Author: Jan Leyonberg <jan_sjodin at yahoo.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/test/Lower/Intrinsics/acosh.f90
M flang/test/Lower/Intrinsics/asin.f90
M flang/test/Lower/Intrinsics/asinh.f90
M flang/test/Lower/Intrinsics/atanh.f90
Log Message:
-----------
[Flang] Generate math ops for non-precise calls to acosh, asin, asinh and atanh intrinsic calls (#126932)
This patch changes the codegen for non-precise acosh, asin, asinh and
atanh calls to generate math ops instead. This wasn't done before
because the math dialect did not have the corresponding operations at
the time.
Commit: c4ed95c85bf8ef900cff6444f8f3c97495b1b7bc
https://github.com/llvm/llvm-project/commit/c4ed95c85bf8ef900cff6444f8f3c97495b1b7bc
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M flang/lib/Frontend/CompilerInvocation.cpp
Log Message:
-----------
[Flang] Fix leftover use of 'OPT_nogpulib'
Summary:
This didn't show up as a failure in precommit and I don't build flang so
this slipped by.
Commit: a33a84ee6348659d7e2483d728a841a9872fe2ec
https://github.com/llvm/llvm-project/commit/a33a84ee6348659d7e2483d728a841a9872fe2ec
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
R llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
R llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx940.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/back-off-barrier-subtarget-feature.ll
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
M llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
M llvm/test/CodeGen/AMDGPU/dpp64_combine.ll
M llvm/test/CodeGen/AMDGPU/dpp64_combine.mir
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
M llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir
R llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
A llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
R llvm/test/CodeGen/AMDGPU/gfx940-hazards.mir
A llvm/test/CodeGen/AMDGPU/gfx942-hazards.mir
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/idemponent-atomics.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/lds-dma-hazards.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
M llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
R llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx940.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
R llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx940.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot8.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
R llvm/test/CodeGen/AMDGPU/mai-hazards-gfx940.mir
A llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-global.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-local.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
R llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select-gfx940.ll
A llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select-gfx942.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/neighboring-mfma-padding.mir
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
M llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-IR-lowering.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs-IR-lowering.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-sample.ll
M llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/verifier-sdwa-cvt.mir
M llvm/test/MC/AMDGPU/amdhsa-kd-kernarg-preload.s
M llvm/test/MC/AMDGPU/extrasgprs_mcexpr.s
R llvm/test/MC/AMDGPU/flat-scratch-gfx940.s
A llvm/test/MC/AMDGPU/flat-scratch-gfx942.s
R llvm/test/MC/AMDGPU/gfx940_asm_features.s
R llvm/test/MC/AMDGPU/gfx940_err.s
R llvm/test/MC/AMDGPU/gfx940_err_pos.s
R llvm/test/MC/AMDGPU/gfx940_unsupported.s
A llvm/test/MC/AMDGPU/gfx942_asm_features.s
A llvm/test/MC/AMDGPU/gfx942_err.s
A llvm/test/MC/AMDGPU/gfx942_err_pos.s
A llvm/test/MC/AMDGPU/gfx942_unsupported.s
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_asm_read_tr.s
M llvm/test/MC/AMDGPU/gfx950_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx950_asm_vop3.s
R llvm/test/MC/AMDGPU/mai-err-gfx940.s
A llvm/test/MC/AMDGPU/mai-err-gfx942.s
R llvm/test/MC/AMDGPU/mai-gfx940.s
A llvm/test/MC/AMDGPU/mai-gfx942.s
M llvm/test/MC/AMDGPU/mai-gfx950.s
R llvm/test/MC/AMDGPU/mimg-err-gfx940.s
A llvm/test/MC/AMDGPU/mimg-err-gfx942.s
M llvm/test/MC/AMDGPU/mubuf-gfx950.s
M llvm/test/MC/AMDGPU/writelane_m0.s
M llvm/test/MC/AMDGPU/xdl-insts-gfx908.s
M llvm/test/MC/Disassembler/AMDGPU/gfx908-xdl-insts.txt
R llvm/test/MC/Disassembler/AMDGPU/gfx940_features.txt
R llvm/test/MC/Disassembler/AMDGPU/gfx940_flat.txt
R llvm/test/MC/Disassembler/AMDGPU/gfx940_mai.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx942_features.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx942_flat.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx942_mai.txt
M llvm/test/MachineVerifier/AMDGPU/writelane_m0.mir
M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i64-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i64-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd-flat-specialization.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2bf16-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2bf16-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2f16-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2f16-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-flat-noalias-addrspace.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-fp-vector.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-integer-ops-0-to-add-0.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/load-i1-misaligned.ll
M llvm/test/tools/llvm-mca/AMDGPU/carried-over.s
R llvm/test/tools/llvm-mca/AMDGPU/gfx940-mfma.s
A llvm/test/tools/llvm-mca/AMDGPU/gfx942-mfma.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
Log Message:
-----------
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test
gfx940 and gfx941 are no longer supported. This is one of a series of PRs to remove them from the code base.
This PR uses gfx942 instead of gfx940 and gfx941 in the test RUN-lines (unless there is already a RUN-line for gfx942).
The only notable difference in the test output is that gfx942 does not force the use of sc0 and sc1 on stores while gfx940 and gfx941 do (cf. https://reviews.llvm.org/D149986).
For SWDEV-512631
Commit: 8600d89e55b866186a2dad2e2b4c85bd96150375
https://github.com/llvm/llvm-project/commit/8600d89e55b866186a2dad2e2b4c85bd96150375
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
A llvm/test/Transforms/DeadStoreElimination/captures-ret-only.ll
Log Message:
-----------
[DSE] Add test for interaction with return-only captures (NFC)
Regression test for the miscompile reported at:
https://github.com/llvm/llvm-project/pull/125880#issuecomment-2656632577
Commit: 95bb61bba9dcf0698525cabf8363b91fcb8e57b1
https://github.com/llvm/llvm-project/commit/95bb61bba9dcf0698525cabf8363b91fcb8e57b1
Author: Oleg Shyshkov <shyshkov at google.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Port 1935f84856a9297e725770e6f4b9c50fbcec365c
Commit: 7d1db31aa05cce9e760c473a95f190909c2549b5
https://github.com/llvm/llvm-project/commit/7d1db31aa05cce9e760c473a95f190909c2549b5
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/same-values-sub-node-with-poisons.ll
Log Message:
-----------
[SLP]Check the first instruction instead the first scalar for subvectors
Need to check the first instruction instead of first scalar for
subvectors, when trying to find full matched vectorized node in the
graph.
Fixes #126909.
Commit: 3e54964dcf35dcca02e5d8f18294d6763be35918
https://github.com/llvm/llvm-project/commit/3e54964dcf35dcca02e5d8f18294d6763be35918
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
Log Message:
-----------
[AMDGPU] Simplify OtherPredicates handling in MadFmaMixPats. NFC. (#127044)
This removes some of the complexity added by ad6cd7e8b259 by setting
OtherPredicates outside MadFmaMixPats rather than inside it.
Commit: aecb764cc2e026ecb5c418dd56f2722c6f263e8b
https://github.com/llvm/llvm-project/commit/aecb764cc2e026ecb5c418dd56f2722c6f263e8b
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M mlir/include/mlir/Conversion/Passes.td
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
A mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm-invalid-dialect.mlir
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
A mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-invalid-dialect.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
Log Message:
-----------
[mlir][gpu] GPUToROCDL/NVVM: use generic llvm conversion interface instead of hardcoded conversions. (#124439)
Using `ConvertToLLVMPatternInterface` allows to unhardcode specific
dialect conversions from passes and, more importantly, allows downstream
projects to inject their ops/types translation here by registering
corresponding interface.
Add `allowed-dialects` option so user can control which dialects can be
used to populate conversions.
Commit: db2953d80148870ee22b0ffaed883a02174485c4
https://github.com/llvm/llvm-project/commit/db2953d80148870ee22b0ffaed883a02174485c4
Author: Alex Bradbury <asb at igalia.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang/www/OpenProjects.html
M libc/docs/index.rst
M libcxx/docs/index.rst
M lldb/docs/index.rst
M llvm/docs/GettingInvolved.rst
Log Message:
-----------
[doc] Add Discord invite link alongside channel links (#126352)
By far the most important part of this patch is updating
GettingInvolved.rst to include the invite link, but I've grepped for any
other discord.com links.
I'm no Discord expert, but from my experience (confirmed via @preames
kindly testing as well) the direct channel links provide a confusing
experience if you haven't already found and used an invite link to the
LLVM Discord server. If you're logged into Discord but not a member of
LLVM's sever, the web app opens and then...nothing. No channel opens, no
prompt to join the server or even a hint that you need to find an invite
link (and if you're not used to Discord, you likely don't even know
that's necessary).
This patch addresses the issue by providing the invite link where
Discord is mentioned.
Commit: 277cb60d9ab4335bcc6aef4366278e1500237d2c
https://github.com/llvm/llvm-project/commit/277cb60d9ab4335bcc6aef4366278e1500237d2c
Author: Dave Lee <davelee.com at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M lldb/source/Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.cpp
Log Message:
-----------
[lldb] Use LLDB_LOG_ERROR in ObjectFilePECOFF.cpp (NFC) (#126972)
Commit: 62eddf4792c1dca0d225f06b35887733a557ebb5
https://github.com/llvm/llvm-project/commit/62eddf4792c1dca0d225f06b35887733a557ebb5
Author: Alex Bradbury <asb at igalia.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/docs/HowToAddABuilder.rst
Log Message:
-----------
[docs] Fix typo in HowToAddABuilder
Commit: d2240cd314102ed99d35b84d43006e324f344163
https://github.com/llvm/llvm-project/commit/d2240cd314102ed99d35b84d43006e324f344163
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang/test/Analysis/out-of-bounds.c
Log Message:
-----------
[NFC] [analyzer] Add ArrayBound tests to document casting bug (#127062)
Add a few security.ArrayBound testcases that document the false
positives caused the fact that the analyzer doesn't model a cast from
`signed char` to `unsigned char`.
Commit: 0da8d0f9b712cd9e8110dff2b6bde87205af7932
https://github.com/llvm/llvm-project/commit/0da8d0f9b712cd9e8110dff2b6bde87205af7932
Author: Robert Imschweiler <50044286+ro-i at users.noreply.github.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
Log Message:
-----------
[AMDGPU] Change handling of unsupported non-compute shaders with HSA (#126798)
Previous handling in `SITargetLowering::LowerFormalArguments` only
reported a diagnostic message and continued execution by returning a
non-usable `SDValue`. This results in llvm crashing later with an
unrelated error. This commit changes the detection of an unsupported
non-compute shader to be a fatal error right away.
As an example situation, take the usage of an `amdgpu_ps` function and
the `amdgcn-unknown-amdhsa` target triple.
```
define amdgpu_ps void @foo(ptr %p, i32 %i) {
store i32 %i, ptr %p
ret void
}
```
Compiling this code (with `llc -mtriple=amdgcn-unknown-amdhsa
-mcpu=gfx942`, for example) fails with:
```
error: <unknown>:0:0: in function foo void (ptr, i32): unsupported non-compute shaders with HSA
llc:
[...]/git/trunk21.0/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:11790:
void llvm::SelectionDAGISel::LowerArguments(const llvm::Function&):
Assertion `InVals.size() == Ins.size() && "LowerFormalArguments didn't emit the correct number of values!"' failed.
[...]
```
Commit: 41e49fadd4681bd31f7b9791936cc75912369a56
https://github.com/llvm/llvm-project/commit/41e49fadd4681bd31f7b9791936cc75912369a56
Author: Robert Imschweiler <50044286+ro-i at users.noreply.github.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id-unsupported-calling-convention.ll
Log Message:
-----------
[AMDGPU] Fix llvm.amdgcn.workitem.id-unsupported-calling-convention.ll (#127041)
Follow-up fix for #126058. (@arsenm)
Commit: 2ad816648f2719e6c0da507a1a371f2cad4a3f1c
https://github.com/llvm/llvm-project/commit/2ad816648f2719e6c0da507a1a371f2cad4a3f1c
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/InstructionsState-is-invalid-0.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/horizontal-list.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll
M llvm/test/Transforms/SLPVectorizer/X86/bool-mask.ll
M llvm/test/Transforms/SLPVectorizer/X86/external-used-across-reductions.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract-scalar-from-undef.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelemets-extended-by-poison.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
M llvm/test/Transforms/SLPVectorizer/X86/malformed_phis.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-tracked-reduced-value.ll
M llvm/test/Transforms/SLPVectorizer/X86/phi-node-reshuffled-part.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-val-extracted-and-externally-used.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-value-vectorized-later.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-extracted-value.ll
M llvm/test/Transforms/SLPVectorizer/X86/revectorized_rdx_crash.ll
M llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
M llvm/test/Transforms/SLPVectorizer/partial-register-extract.ll
M llvm/test/Transforms/SLPVectorizer/reduction-modified-values.ll
M llvm/test/Transforms/SLPVectorizer/scalarization-overhead.ll
Log Message:
-----------
[SLP]Improved reduction cost/codegen
SLP vectorizer is able to combine several reductions from the list of
(potentially) reduced values with the different opcodes/values kind.
Currently, these reductions are handled independently of each other. But
instead the compiler can combine them into wide vector operations and
then perform only single reduction.
E.g, if the SLP vectorizer emits currently something like:
```
%r1 = reduce.add(<4 x i32> %v1)
%r2 = reduce.add(<4 x i32> %v2)
%r = add i32 %r1, %r2
```
it can be emitted as:
```
%v = add <4 x i32> %v1, %v2
%r = reduce.add(<4 x i32> %v)
```
It allows to improve the performance in some cases.
AVX512, -O3+LTO
Metric: size..text
Program size..text
results results0 diff
test-suite :: SingleSource/Benchmarks/Shootout-C++/Shootout-C++-matrix.test 4553.00 4615.00 1.4%
test-suite :: SingleSource/Benchmarks/Adobe-C++/loop_unroll.test 412708.00 416820.00 1.0%
test-suite :: SingleSource/UnitTests/Vector/AVX512BWVL/Vector-AVX512BWVL-mask_set_bw.test 12901.00 12981.00 0.6%
test-suite :: MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow.test 22717.00 22813.00 0.4%
test-suite :: MultiSource/Benchmarks/mediabench/gsm/toast/toast.test 39722.00 39850.00 0.3%
test-suite :: MultiSource/Benchmarks/MiBench/telecomm-gsm/telecomm-gsm.test 39725.00 39853.00 0.3%
test-suite :: SingleSource/Regression/C/gcc-c-torture/execute/GCC-C-execute-builtin-bitops-1.test 15918.00 15967.00 0.3%
test-suite :: External/SPEC/CFP2006/433.milc/433.milc.test 155491.00 155587.00 0.1%
test-suite :: MicroBenchmarks/ImageProcessing/Blur/blur.test 227894.00 227942.00 0.0%
test-suite :: MultiSource/Benchmarks/7zip/7zip-benchmark.test 1062188.00 1062364.00 0.0%
test-suite :: External/SPEC/CINT2006/464.h264ref/464.h264ref.test 793672.00 793720.00 0.0%
test-suite :: External/SPEC/CINT2017rate/525.x264_r/525.x264_r.test 657371.00 657403.00 0.0%
test-suite :: External/SPEC/CINT2017speed/625.x264_s/625.x264_s.test 657371.00 657403.00 0.0%
test-suite :: External/SPEC/CINT2017speed/600.perlbench_s/600.perlbench_s.test 2074917.00 2074933.00 0.0%
test-suite :: External/SPEC/CINT2017rate/500.perlbench_r/500.perlbench_r.test 2074917.00 2074933.00 0.0%
test-suite :: MultiSource/Applications/JM/lencod/lencod.test 855219.00 855203.00 -0.0%
Benchmarks/Shootout-C++ - same transformed reduction
Adobe-C++/loop_unroll - same transformed reductions, new vector code
AVX512BWVL/Vector-AVX512BWVL-mask_set_bw - same transformed reductions
FreeBench/fourinarow - same transformed reductions
MiBench/telecomm-gsm - same transformed reductions
execute/GCC-C-execute-builtin-bitops-1 - same transformed reductions
CFP2006/433.milc - better vector code, several x i64 reductions + trunc
to i32 gets trunced to x i32 reductions
ImageProcessing/Blur - same transformed reductions
Benchmarks/7zip - same transformed reductions, extra 4 x vectorization
CINT2006/464.h264ref - same transformed reductions
CINT2017rate/525.x264_r
CINT2017speed/625.x264_s - same transformed reductions
CINT2017speed/600.perlbench_s
CINT2017rate/500.perlbench_r - transformed same reduction
JM/lencod - extra 4 x vectorization
RISC-V, SiFive-p670, -O3+LTO
Metric: size..text
Program size..text
results results0 diff
test-suite :: SingleSource/Regression/C/gcc-c-torture/execute/GCC-C-execute-builtin-bitops-1.test 8990.00 9514.00 5.8%
test-suite :: External/SPEC/CINT2006/464.h264ref/464.h264ref.test 588504.00 588488.00 -0.0%
test-suite :: MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame.test 147464.00 147440.00 -0.0%
test-suite :: MultiSource/Benchmarks/MiBench/automotive-susan/automotive-susan.test 21496.00 21492.00 -0.0%
test-suite :: MicroBenchmarks/ImageProcessing/Blur/blur.test 165420.00 165372.00 -0.0%
test-suite :: MultiSource/Benchmarks/7zip/7zip-benchmark.test 843928.00 843648.00 -0.0%
test-suite :: External/SPEC/CINT2006/458.sjeng/458.sjeng.test 100712.00 100672.00 -0.0%
test-suite :: MultiSource/Benchmarks/MiBench/telecomm-gsm/telecomm-gsm.test 24384.00 24336.00 -0.2%
test-suite :: MultiSource/Benchmarks/mediabench/gsm/toast/toast.test 24380.00 24332.00 -0.2%
test-suite :: SingleSource/UnitTests/Vectorizer/VPlanNativePath/outer-loop-vect.test 10348.00 10316.00 -0.3%
test-suite :: SingleSource/Benchmarks/Adobe-C++/loop_unroll.test 221304.00 220480.00 -0.4%
test-suite :: SingleSource/Benchmarks/Shootout-C++/Shootout-C++-matrix.test 3750.00 3736.00 -0.4%
test-suite :: SingleSource/Regression/C/Regression-C-DuffsDevice.test 678.00 370.00 -45.4%
execute/GCC-C-execute-builtin-bitops-1 - extra 4 x reductions, same
transformed reductions
CINT2006/464.h264ref - extra 4 x reductions, same transformed reductions
MiBench/consumer-lame - 2 4 x i1 merged to 8 x i1 reductions (bitcast + ctpop)
MiBench/automotive-susan - same transformed reductions
ImageProcessing/Blur - same transformed reductions
Benchmarks/7zip - same transformed reductions
CINT2006/458.sjeng - 2 4 x i1 merged to 8 x i1 reductions (bitcast + ctpop)
MiBench/telecomm-gsm - same transformed reductions
Benchmarks/mediabench - same transformed reductions
Vectorizer/VPlanNativePath - same transformed reductions
Adobe-C++/loop_unroll - extra 4 x reductions, same transformed reductions
Benchmarks/Shootout-C++ - extra 4 x reductions, same transformed reductions
Regression/C/Regression-C-DuffsDevice - same transformed reductions
Reviewers: hiraditya, topperc, preames
Pull Request: https://github.com/llvm/llvm-project/pull/118293
Commit: a1345eb240c9456ce1c339106f066217eb5e6984
https://github.com/llvm/llvm-project/commit/a1345eb240c9456ce1c339106f066217eb5e6984
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/tools/libclang/CXString.cpp
Log Message:
-----------
Revert "[libclang] Always Dup in createRef(StringRef)" (#127076)
Reverts llvm/llvm-project#125020
https://lab.llvm.org/buildbot/#/builders/24/builds/5252/steps/12/logs/stdio
```
==c-index-test==2512295==ERROR: AddressSanitizer: heap-use-after-free on address 0xe19338c27992 at pc 0xc66be4784830 bp 0xe0e33660df00 sp 0xe0e33660d6e8
READ of size 23 at 0xe19338c27992 thread T1
#0 0xc66be478482c in printf_common(void*, char const*, std::__va_list) /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm-project/compiler-rt/lib/asan/../sanitizer_common/sanitizer_common_interceptors_format.inc:563:9
#1 0xc66be478643c in vprintf /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm-project/compiler-rt/lib/asan/../sanitizer_common/sanitizer_common_interceptors.inc:1699:1
#2 0xc66be478643c in printf /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm-project/compiler-rt/lib/asan/../sanitizer_common/sanitizer_common_interceptors.inc:1757:1
#3 0xc66be4839384 in FilteredPrintingVisitor /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm-project/clang/tools/c-index-test/c-index-test.c:1359:5
#4 0xe4e3454f12e8 in clang::cxcursor::CursorVisitor::Visit(CXCursor, bool) /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm-project/clang/tools/libclang/CIndex.cpp:227:11
#5 0xe4e3454f48a8 in bool clang::cxcursor::CursorVisitor::visitPreprocessedEntities<clang::PreprocessingRecord::iterator>(clang::PreprocessingRecord::iterator, clang::PreprocessingRecord::iterator, clang::PreprocessingRecord&, clang::FileID) CIndex.cpp
0xe19338c27992 is located 82 bytes inside of 105-byte region [0xe19338c27940,0xe19338c279a9)
freed by thread T1 here:
#0 0xc66be480040c in free /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm-project/compiler-rt/lib/asan/asan_malloc_linux.cpp:51:3
#1 0xc66be4839728 in GetCursorSource c-index-test.c
#2 0xc66be4839368 in FilteredPrintingVisitor /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm-project/clang/tools/c-index-test/c-index-test.c:1360:12
#3 0xe4e3454f12e8 in clang::cxcursor::CursorVisitor::Visit(CXCursor, bool) /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm-project/clang/tools/libclang/CIndex.cpp:227:11
#4 0xe4e3454f48a8 in bool clang::cxcursor::CursorVisitor::visitPreprocessedEntities<clang::PreprocessingRecord::iterator>(clang::PreprocessingRecord::iterator, clang::PreprocessingRecord::iterator, clang::PreprocessingRecord&, clang::FileID) CIndex.cpp
previously allocated by thread T1 here:
#0 0xc66be4800680 in malloc /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm-project/compiler-rt/lib/asan/asan_malloc_linux.cpp:67:3
#1 0xe4e3456379b0 in safe_malloc /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm-project/llvm/include/llvm/Support/MemAlloc.h:26:18
#2 0xe4e3456379b0 in createDup /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm-project/clang/tools/libclang/CXString.cpp:95:40
#3 0xe4e3456379b0 in clang::cxstring::createRef(llvm::StringRef) /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm-project/clang/tools/libclang/CXString.cpp:90:10
```
Commit: de09986596c9bbc89262456dda319715fb49353f
https://github.com/llvm/llvm-project/commit/de09986596c9bbc89262456dda319715fb49353f
Author: Hyunsung Lee <ita9naiwa at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Math/Transforms/ExpandPatterns.cpp
M mlir/test/Dialect/Math/expand-math.mlir
M mlir/test/mlir-runner/test-expand-math-approx.mlir
Log Message:
-----------
[mlir][math] `powf(a, b)` drop support when a < 0 (#126338)
Related: #124402
- change inefficient implementation of `powf(a, b)` to handle `a < 0`
case
- thus drop `a < 0` case support
However, some special cases are being used such as:
- `a < 0` and `b = 0, b = 0.5, b = 1 or b = 2`
- convert those special cases into simpler ops.
Commit: b2165f214efab833a4b1a9e8268b1030fc5ebaeb
https://github.com/llvm/llvm-project/commit/b2165f214efab833a4b1a9e8268b1030fc5ebaeb
Author: David Green <david.green at arm.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/test/Analysis/CostModel/AArch64/fshl.ll
M llvm/test/Analysis/CostModel/AArch64/fshr.ll
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll
Log Message:
-----------
[CostModel] Account for power-2 urem in funnel shift costs (#127037)
As can be seen in https://godbolt.org/z/qvMqY79cK, a urem by a power-2
constant will be code-generated as an And of a mask. The cost model for
funnel shifts tries to account for that by passing OP_PowerOf2 as the
operand info for the second operand. As far as I can tell returning a
lower cost for urem with a OP_PowerOf2 is only implemented on X86
though.
This patch short-cuts that by calling getArithmeticInstrCost(And, ..)
directly when we know the typesize will be a power-of-2. This is an
alternative to the patch in #126912 which is a more general solution for
power-2 udiv/urem costs, this more narrowly just fixes funnel shifts.
Commit: 21811818d6c1a50051032fdb2d350ffe89e1421a
https://github.com/llvm/llvm-project/commit/21811818d6c1a50051032fdb2d350ffe89e1421a
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] port aecb764cc2e026ecb5c418dd56f2722c6f263e8b
Commit: 8da8ff8768bc0115f21d7d8fe8d47872190f8de1
https://github.com/llvm/llvm-project/commit/8da8ff8768bc0115f21d7d8fe8d47872190f8de1
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Flang.cpp
M flang/include/flang/Frontend/TargetOptions.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Frontend/FrontendActions.cpp
A flang/test/Driver/mabi-riscv.f90
A flang/test/Lower/RISCV/riscv-target-abi.f90
Log Message:
-----------
[flang][RISCV] Add target-abi ModuleFlag. (#126188)
This is needed to generate proper ABI flags in the ELF header for LTO
builds. If these flags aren't set correctly, we can't link with objects
that were built with the correct flags.
For non-LTO builds the mcpu/mattr in the TargetMachine will cause the
backend to infer an ABI. For LTO builds the mcpu/mattr aren't set.
I've only added lp64, lp64f, and lp64d ABIs. ilp32* requires riscv32
which is not yet supported in flang. lp64e requires a different
DataLayout string and would need additional plumbing.
Fixes #115679
Commit: 88015d12ca600cf2a74ba3641f319c7ba056223b
https://github.com/llvm/llvm-project/commit/88015d12ca600cf2a74ba3641f319c7ba056223b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M mlir/lib/Conversion/ComplexCommon/DivisionConverter.cpp
Log Message:
-----------
[mlir] Fix a warning
This patch fixes:
mlir/lib/Conversion/ComplexCommon/DivisionConverter.cpp:61:2: error:
extra ';' outside of a function is incompatible with C++98
[-Werror,-Wc++98-compat-extra-semi]
Commit: ba45592377703f99e1955a51f19922522446caec
https://github.com/llvm/llvm-project/commit/ba45592377703f99e1955a51f19922522446caec
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
Log Message:
-----------
[AMDGPU] Try to fix -mattr=dumpcode on big-endian hosts (#127073)
Blind fix for #116982 failing on big-endian buildbots.
Commit: 2f8de7b466efc613111904ee36d13ec95976739a
https://github.com/llvm/llvm-project/commit/2f8de7b466efc613111904ee36d13ec95976739a
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
A llvm/test/CodeGen/SPIRV/validate/triton-tut-softmax-kernel.ll
Log Message:
-----------
[SPIR-V] Type inference must realize that a <1 x Type> vector type is not a legal vector type in LLT (#124560)
In this PR we account for possible <1 x LLVM Type> input to ensure that
we produce legal vector types during type inference.
We modify an LLVM type to conform with future transformations in
IRTranslator, if it's a <1 x Type> vector type, replacing it by the
element type, because <1 x Type> vector type is not a legal vector type
in LLT and IRTranslator will represent it as the scalar eventually.
Commit: 1138a4964adf76cc4af82b3f43dbc8db0b91cd46
https://github.com/llvm/llvm-project/commit/1138a4964adf76cc4af82b3f43dbc8db0b91cd46
Author: Georgiy Samoylov <g.samoylov at syntacore.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M lldb/test/API/tools/lldb-server/main.cpp
Log Message:
-----------
[lldb] Fix build problem in llgs tests for RISC-V (#127091)
During testing of LLDB on RISC-V target, tests from the llgs category
were built with an error: `Error when building test subject.`
```
llvm-project/lldb/test/API/tools/lldb-server/main.cpp:151:40: error: missing ')' after '__builtin_debugtrap'
151 | #elif __has_builtin(__builtin_debugtrap())
| ~~~~~~~~~~~~~~~~~~~^
llvm-project/lldb/test/API/tools/lldb-server/main.cpp:151:20: note: to match this '('
151 | #elif __has_builtin(__builtin_debugtrap())
| ^
```
This patch fixes this error.
Commit: a663e78a6eb6bbd20c0c74b3e6a78e24ee423544
https://github.com/llvm/llvm-project/commit/a663e78a6eb6bbd20c0c74b3e6a78e24ee423544
Author: Piotr Zegar <me at piotrzegar.pl>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang-tools-extra/clang-tidy/utils/ExceptionSpecAnalyzer.cpp
M clang-tools-extra/test/clang-tidy/checkers/performance/noexcept-move-constructor.cpp
Log Message:
-----------
[clang-tidy] Add recursion protection in ExceptionSpecAnalyzer (#66810)
Normally endless recursion should not happen in ExceptionSpecAnalyzer,
but if AST would be malformed (missing include), this could cause crash.
I run into this issue when due to missing include constructor argument
were parsed as FieldDecl.
As checking for recursion cost nothing, why not to do this in check just
in case.
Fixes #111436
Commit: 55f3df875d3a266c566f593357e2290879f49321
https://github.com/llvm/llvm-project/commit/55f3df875d3a266c566f593357e2290879f49321
Author: Abhilash Majumder <30946547+abhilash1910 at users.noreply.github.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/test/CodeGen/NVPTX/prefetch.ll
Log Message:
-----------
[NVPTX] Fix and refine prefetch.* intrinsics (#126899)
This is follow-up PR from #125887 which fixes the intrinsic failures .
---------
Co-authored-by: abmajumder <abmajumder at nvidia.com>
Commit: 79fff6aa324c560f4a32d5d2b0276744a2c49668
https://github.com/llvm/llvm-project/commit/79fff6aa324c560f4a32d5d2b0276744a2c49668
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M lld/ELF/BPSectionOrderer.cpp
M lld/MachO/BPSectionOrderer.cpp
M lld/test/ELF/bp-section-orderer.s
M lld/test/MachO/bp-section-orderer.s
Log Message:
-----------
[lld][BP] Avoid ordering ICF'ed sections (#126327)
ICF runs before BPSectionOrderer. When a section is ICF'ed, it seems
that the original sections are marked as not live, but are still kept
around. Prior to this patch, those ICF'ed sections would be passed to BP
and ordered before being skipped when writing the output. Now, these
sections are no longer passed to BP, saving runtime and possibly
improving BP's output.
In a large binary, I found that the number of sections ordered using BP
decreased, while the number of duplicate sections drastically decreased
as expected.
```
Functions for startup: 50755 -> 50520
Functions for compression: 165734 -> 105328
Duplicate functions: 1827231 -> 55230
```
Commit: e750c7e636f083c48a6cea7fae37ffc3734c7da0
https://github.com/llvm/llvm-project/commit/e750c7e636f083c48a6cea7fae37ffc3734c7da0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
Log Message:
-----------
[RISCV] Set Feature32Bit/Feature64Bit based on triple for -mcpu=help. (#127031)
llvm-mc keeps going after printing help text and creates an assembler.
If we don't set one of the XLen sized feature bits we trip a fatal error
in RISCVFeatures::validate.
llvm-mc should probably be fixed, but I don't know if its the only tool
with this issue.
Commit: f30c891464debb4e0d47d27ea77dc2220d7cdf29
https://github.com/llvm/llvm-project/commit/f30c891464debb4e0d47d27ea77dc2220d7cdf29
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
A lldb/test/API/lang/cpp/enum_promotion/Makefile
A lldb/test/API/lang/cpp/enum_promotion/TestCPPEnumPromotion.py
A lldb/test/API/lang/cpp/enum_promotion/main.cpp
Log Message:
-----------
[lldb] Analyze enum promotion type during parsing (#115005)
The information about an enum's best promotion type is discarded after
compilation and is not present in debug info. This patch repeats the
same analysis of each enum value as in the front-end to determine the
best promotion type during DWARF info parsing.
Fixes #86989
Commit: d096f45322660d59de5267555f121986629bab30
https://github.com/llvm/llvm-project/commit/d096f45322660d59de5267555f121986629bab30
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
Log Message:
-----------
[clang-scan-deps] Avoid repeated map lookups (NFC) (#127023)
Commit: 44b61e056ddb237b7a40d46916abd5d7d6957a3c
https://github.com/llvm/llvm-project/commit/44b61e056ddb237b7a40d46916abd5d7d6957a3c
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Analysis/PhiValues.cpp
Log Message:
-----------
[Analysis] Avoid repeated hash lookups (NFC) (#127024)
Commit: e7bf6a4e042fba2b1492be8fc5f430df3e9a43d2
https://github.com/llvm/llvm-project/commit/e7bf6a4e042fba2b1492be8fc5f430df3e9a43d2
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/LiveStacks.cpp
Log Message:
-----------
[CodeGen] Avoid repeated map lookups (NFC) (#127025)
Commit: fec04f286ef5914f81a5bc188eb2f60cfdbacce8
https://github.com/llvm/llvm-project/commit/fec04f286ef5914f81a5bc188eb2f60cfdbacce8
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/FileCheck/FileCheck.cpp
Log Message:
-----------
[FileCheck] Avoid repeated hash lookups (NFC) (#127026)
Commit: 9a59145d8e3782196378102c42f70f575bc2f99a
https://github.com/llvm/llvm-project/commit/9a59145d8e3782196378102c42f70f575bc2f99a
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Analysis/MemoryProfileInfo.cpp
Log Message:
-----------
[memprof] Avoid repeated map lookups (NFC) (#127027)
Commit: 4bda95304ff892d31c3ff7a89f75df25c0fa3bb9
https://github.com/llvm/llvm-project/commit/4bda95304ff892d31c3ff7a89f75df25c0fa3bb9
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/tools/llvm-profgen/MissingFrameInferrer.cpp
Log Message:
-----------
[llvm-profgen] Avoid repeated hash lookups (NFC) (#127028)
Commit: 4a97ce5f7560bf8be6d0291ae9ea054248fbcf24
https://github.com/llvm/llvm-project/commit/4a97ce5f7560bf8be6d0291ae9ea054248fbcf24
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
Log Message:
-----------
[X86] X86FixupVectorConstantsPass - pull out getPrimitiveSizeInBits call. NFC.
Commit: 07405ca03600fd27fa27fb63f09cd0807f92e31a
https://github.com/llvm/llvm-project/commit/07405ca03600fd27fa27fb63f09cd0807f92e31a
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIProgramInfo.h
Log Message:
-----------
[AMDGPU] clang-format SIProgramInfo.h. NFC. (#127033)
Commit: 9a63a2c4babcaabaeb1a106345f3b037485efa4c
https://github.com/llvm/llvm-project/commit/9a63a2c4babcaabaeb1a106345f3b037485efa4c
Author: Martin Erhart <martin.erhart at sifive.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
A mlir/include/mlir-c/Dialect/Index.h
M mlir/lib/CAPI/Dialect/CMakeLists.txt
A mlir/lib/CAPI/Dialect/Index.cpp
Log Message:
-----------
[mlir][index] Add CAPI (#127039)
Commit: 660cdace559a8dbe44ebf2222b854bf3f39a5f62
https://github.com/llvm/llvm-project/commit/660cdace559a8dbe44ebf2222b854bf3f39a5f62
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M flang/runtime/pointer.cpp
M flang/unittests/Runtime/Pointer.cpp
Log Message:
-----------
[flang] Fixed write past allocated descriptor in PointerAssociateRemapping. (#127000)
The pointer descriptor might be smaller than the target descriptor,
so `operator=` would write beyound the pointer descriptor.
Commit: b12d925bc268421d203724778b41aaf23bf34d4b
https://github.com/llvm/llvm-project/commit/b12d925bc268421d203724778b41aaf23bf34d4b
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M .github/workflows/release-asset-audit.py
M clang-tools-extra/clang-tidy/utils/ExceptionSpecAnalyzer.cpp
M clang-tools-extra/test/clang-tidy/checkers/performance/noexcept-move-constructor.cpp
M clang/bindings/python/clang/cindex.py
M clang/docs/HLSL/FunctionCalls.rst
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang-c/Index.h
M clang/include/clang/AST/JSONNodeDumper.h
M clang/include/clang/AST/Mangle.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/StmtOpenMP.h
M clang/include/clang/AST/TextNodeDumper.h
M clang/include/clang/Analysis/FlowSensitive/CachedConstAccessorsLattice.h
M clang/include/clang/Basic/StmtNodes.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Sema/SemaOpenMP.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/StmtOpenMP.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Basic/OpenMPKinds.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/lib/CodeGen/CGObjCRuntime.h
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/HIPSPV.cpp
M clang/lib/Driver/ToolChains/SPIRVOpenMP.cpp
M clang/lib/Frontend/PrintPreprocessedOutput.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/SemaExceptionSpec.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/test/AST/ast-dump-templates.cpp
M clang/test/Analysis/live-stmts.cpp
M clang/test/Analysis/out-of-bounds.c
R clang/test/CodeGenHLSL/disable_opt.hlsl
M clang/test/Driver/amdgpu-openmp-toolchain.c
A clang/test/Driver/sparc-ias-Wa.s
A clang/test/Index/openmp-stripe.c
A clang/test/OpenMP/stripe_ast_print.cpp
A clang/test/OpenMP/stripe_codegen.cpp
A clang/test/OpenMP/stripe_messages.cpp
M clang/test/Preprocessor/embed_preprocess_to_file.c
M clang/test/SemaCXX/cxx20-ctad-type-alias.cpp
M clang/tools/c-index-test/c-index-test.c
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CXCursor.cpp
M clang/unittests/Analysis/FlowSensitive/CachedConstAccessorsLatticeTest.cpp
M clang/www/OpenProjects.html
M compiler-rt/lib/sanitizer_common/sanitizer_allocator_local_cache.h
M compiler-rt/lib/sanitizer_common/symbolizer/scripts/global_symbols.txt
M flang-rt/lib/runtime/pointer.cpp
M flang-rt/unittests/Runtime/Pointer.cpp
M flang/include/flang/Frontend/TargetOptions.h
M flang/include/flang/Optimizer/OpenACC/FIROpenACCTypeInterfaces.h
M flang/include/flang/Tools/PointerModels.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/OpenACC/CMakeLists.txt
M flang/lib/Optimizer/OpenACC/FIROpenACCTypeInterfaces.cpp
M flang/lib/Optimizer/OpenACC/RegisterOpenACCExtensions.cpp
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/lib/Parser/prescan.cpp
A flang/test/Driver/mabi-riscv.f90
M flang/test/Fir/OpenACC/openacc-mappable.fir
A flang/test/Fir/OpenACC/openacc-type-categories.f90
M flang/test/Fir/alloc.fir
M flang/test/Fir/arrexp.fir
M flang/test/Fir/box.fir
M flang/test/Fir/embox.fir
M flang/test/Fir/ignore-missing-type-descriptor.fir
M flang/test/Fir/polymorphic.fir
M flang/test/Fir/rebox.fir
M flang/test/Integration/OpenMP/map-types-and-sizes.f90
M flang/test/Integration/OpenMP/private-global.f90
M flang/test/Lower/Intrinsics/acosh.f90
M flang/test/Lower/Intrinsics/asin.f90
M flang/test/Lower/Intrinsics/asinh.f90
M flang/test/Lower/Intrinsics/atanh.f90
M flang/test/Lower/OpenMP/parallel-reduction-mixed.f90
A flang/test/Lower/RISCV/riscv-target-abi.f90
M flang/test/Lower/allocatable-polymorphic.f90
M flang/test/Lower/common-block.f90
M flang/test/Lower/forall/character-1.f90
M flang/test/Lower/real-descriptors.f90
M flang/test/Parser/OpenMP/sentinels.f
M flang/test/lib/OpenACC/TestOpenACCInterfaces.cpp
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/headers/math/stdfix.rst
M libc/docs/index.rst
M libc/include/__llvm-libc-common.h
M libc/include/llvm-libc-macros/CMakeLists.txt
M libc/include/llvm-libc-macros/features-macros.h
M libc/include/llvm-libc-macros/pthread-macros.h
M libc/include/stdfix.yaml
M libc/src/__support/fixed_point/CMakeLists.txt
M libc/src/__support/fixed_point/fx_bits.h
M libc/src/__support/fixed_point/fx_rep.h
M libc/src/stdfix/CMakeLists.txt
A libc/src/stdfix/countlshk.cpp
A libc/src/stdfix/countlshk.h
A libc/src/stdfix/countlshr.cpp
A libc/src/stdfix/countlshr.h
A libc/src/stdfix/countlsk.cpp
A libc/src/stdfix/countlsk.h
A libc/src/stdfix/countlslk.cpp
A libc/src/stdfix/countlslk.h
A libc/src/stdfix/countlslr.cpp
A libc/src/stdfix/countlslr.h
A libc/src/stdfix/countlsr.cpp
A libc/src/stdfix/countlsr.h
A libc/src/stdfix/countlsuhk.cpp
A libc/src/stdfix/countlsuhk.h
A libc/src/stdfix/countlsuhr.cpp
A libc/src/stdfix/countlsuhr.h
A libc/src/stdfix/countlsuk.cpp
A libc/src/stdfix/countlsuk.h
A libc/src/stdfix/countlsulk.cpp
A libc/src/stdfix/countlsulk.h
A libc/src/stdfix/countlsulr.cpp
A libc/src/stdfix/countlsulr.h
A libc/src/stdfix/countlsur.cpp
A libc/src/stdfix/countlsur.h
M libc/src/time/time_utils.h
M libc/test/integration/src/pthread/pthread_mutex_test.cpp
M libc/test/src/stdfix/CMakeLists.txt
A libc/test/src/stdfix/CountlsTest.h
A libc/test/src/stdfix/countlshk_test.cpp
A libc/test/src/stdfix/countlshr_test.cpp
A libc/test/src/stdfix/countlsk_test.cpp
A libc/test/src/stdfix/countlslk_test.cpp
A libc/test/src/stdfix/countlslr_test.cpp
A libc/test/src/stdfix/countlsr_test.cpp
A libc/test/src/stdfix/countlsuhk_test.cpp
A libc/test/src/stdfix/countlsuhr_test.cpp
A libc/test/src/stdfix/countlsuk_test.cpp
A libc/test/src/stdfix/countlsulk_test.cpp
A libc/test/src/stdfix/countlsulr_test.cpp
A libc/test/src/stdfix/countlsur_test.cpp
M libcxx/docs/Hardening.rst
M libcxx/docs/index.rst
M libcxx/include/__filesystem/path.h
M libcxx/include/__vector/vector_bool.h
M libcxx/utils/ci/run-buildbot
M lld/ELF/BPSectionOrderer.cpp
M lld/MachO/BPSectionOrderer.cpp
M lld/test/ELF/bp-section-orderer.s
M lld/test/MachO/bp-section-orderer.s
M lldb/docs/index.rst
M lldb/include/lldb/API/SBTarget.h
M lldb/include/lldb/API/SBType.h
M lldb/include/lldb/API/SBValue.h
M lldb/source/API/SBType.cpp
M lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
M lldb/source/Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Symbol/Block.cpp
M lldb/source/Symbol/SymbolContext.cpp
M lldb/source/Target/ThreadPlanStepOut.cpp
A lldb/test/API/functionalities/thread/finish-from-empty-func/Makefile
A lldb/test/API/functionalities/thread/finish-from-empty-func/TestEmptyFuncThreadStepOut.py
A lldb/test/API/functionalities/thread/finish-from-empty-func/main.c
M lldb/test/API/lang/cpp/class-template-parameter-pack/TestTemplatePackArgs.py
A lldb/test/API/lang/cpp/enum_promotion/Makefile
A lldb/test/API/lang/cpp/enum_promotion/TestCPPEnumPromotion.py
A lldb/test/API/lang/cpp/enum_promotion/main.cpp
M lldb/test/API/lang/cpp/template-arguments/Makefile
M lldb/test/API/lang/cpp/template-arguments/TestCppTemplateArguments.py
M lldb/test/API/lang/cpp/template-arguments/main.cpp
M lldb/test/API/tools/lldb-server/main.cpp
M lldb/test/Shell/Commands/command-disassemble.s
M lldb/test/Shell/ScriptInterpreter/Python/sb_function_ranges.s
M lldb/test/Shell/SymbolFile/DWARF/x86/simplified-template-names.cpp
M lldb/tools/lldb-dap/package-lock.json
M lldb/tools/lldb-dap/package.json
M lldb/tools/lldb-dap/src-ts/debug-adapter-factory.ts
M llvm/cmake/config-ix.cmake
M llvm/docs/GettingInvolved.rst
M llvm/docs/HowToAddABuilder.rst
M llvm/docs/LangRef.rst
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/include/llvm/AsmParser/LLToken.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
A llvm/include/llvm/CodeGen/DroppedVariableStatsMIR.h
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/include/llvm/Config/config.h.cmake
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/IR/DIBuilder.h
A llvm/include/llvm/IR/DroppedVariableStats.h
A llvm/include/llvm/IR/DroppedVariableStatsIR.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
R llvm/include/llvm/Passes/DroppedVariableStats.h
R llvm/include/llvm/Passes/DroppedVariableStatsIR.h
M llvm/include/llvm/Passes/StandardInstrumentations.h
M llvm/include/llvm/Support/ModRef.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/InstrMaps.h
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/MemoryProfileInfo.cpp
M llvm/lib/Analysis/PhiValues.cpp
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/CMakeLists.txt
A llvm/lib/CodeGen/DroppedVariableStatsMIR.cpp
M llvm/lib/CodeGen/LiveStacks.cpp
M llvm/lib/CodeGen/MachineFunctionPass.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegAllocGreedy.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.cpp
M llvm/lib/FileCheck/FileCheck.cpp
M llvm/lib/IR/Attributes.cpp
M llvm/lib/IR/CMakeLists.txt
M llvm/lib/IR/Constants.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
A llvm/lib/IR/DroppedVariableStats.cpp
A llvm/lib/IR/DroppedVariableStatsIR.cpp
M llvm/lib/Passes/CMakeLists.txt
R llvm/lib/Passes/DroppedVariableStatsIR.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Support/ModRef.cpp
M llvm/lib/Support/Unix/Process.inc
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/ARM/ARMCallingConv.cpp
M llvm/lib/Target/ARM/ARMCallingConv.td
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/PowerPC/PPCRegisterInfo.h
M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
M llvm/lib/Target/RISCV/RISCV.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVProcessors.td
A llvm/lib/Target/RISCV/RISCVSchedGeneric.td
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/lib/Transforms/IPO/SCCP.cpp
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Scheduler.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Analysis/CostModel/AArch64/fshl.ll
M llvm/test/Analysis/CostModel/AArch64/fshr.ll
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll
M llvm/test/Analysis/LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll
M llvm/test/Analysis/LoopAccessAnalysis/non-constant-distance-backward.ll
A llvm/test/Analysis/LoopAccessAnalysis/retry-runtime-checks-after-dependence-analysis.ll
M llvm/test/Assembler/memory-attribute-errors.ll
M llvm/test/Assembler/memory-attribute.ll
A llvm/test/Bitcode/Inputs/memory-attribute-upgrade.bc
A llvm/test/Bitcode/memory-attribute-upgrade.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
R llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
R llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx940.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/back-off-barrier-subtarget-feature.ll
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
M llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
M llvm/test/CodeGen/AMDGPU/dpp64_combine.ll
M llvm/test/CodeGen/AMDGPU/dpp64_combine.mir
A llvm/test/CodeGen/AMDGPU/dumpcode.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir
M llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-clear-kill-flags.mir
R llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
A llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
R llvm/test/CodeGen/AMDGPU/gfx940-hazards.mir
A llvm/test/CodeGen/AMDGPU/gfx942-hazards.mir
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/idemponent-atomics.ll
A llvm/test/CodeGen/AMDGPU/iglp-no-clobber.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/lds-dma-hazards.mir
M llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
M llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
R llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx940.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
R llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx940.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot8.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id-unsupported-calling-convention.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
R llvm/test/CodeGen/AMDGPU/mai-hazards-gfx940.mir
A llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-global.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-local.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
R llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select-gfx940.ll
A llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select-gfx942.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/neighboring-mfma-padding.mir
M llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
M llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-IR-lowering.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs-IR-lowering.ll
M llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
A llvm/test/CodeGen/AMDGPU/reg-sequence-like-v-pk-mov-b32.mir
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2bf16.v8bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f16.v8f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i16.v8i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v2f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v3f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v4f32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v3i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v4i16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v2i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v3i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v4i32.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v3i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v4i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v2p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v3p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v2p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v3p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v4p3.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v3bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v4bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v3f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v4f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v2f32.ll
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M llvm/test/CodeGen/AMDGPU/uniform-select.ll
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M llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/verifier-sdwa-cvt.mir
A llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-cs.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-lib.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/lib-entry-attr-error.ll
M llvm/test/CodeGen/DirectX/llc-pipeline.ll
M llvm/test/CodeGen/LoongArch/statepoint-call-lowering.ll
M llvm/test/CodeGen/NVPTX/prefetch.ll
M llvm/test/CodeGen/PowerPC/adde_return_type.ll
M llvm/test/CodeGen/PowerPC/addegluecrash.ll
M llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
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M llvm/test/CodeGen/PowerPC/aix-cc-byval-split.ll
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M llvm/test/CodeGen/PowerPC/pr35688.ll
M llvm/test/CodeGen/PowerPC/pr36292.ll
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M llvm/test/CodeGen/PowerPC/sat-add.ll
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M llvm/test/CodeGen/PowerPC/uaddo-32.ll
M llvm/test/CodeGen/PowerPC/uaddo-64.ll
M llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll
M llvm/test/CodeGen/RISCV/GlobalISel/combine-neg-abs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll
M llvm/test/CodeGen/RISCV/GlobalISel/stacksave-stackrestore.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abds.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
M llvm/test/CodeGen/RISCV/abdu.ll
M llvm/test/CodeGen/RISCV/add-before-shl.ll
M llvm/test/CodeGen/RISCV/add-imm.ll
M llvm/test/CodeGen/RISCV/alloca.ll
M llvm/test/CodeGen/RISCV/alu64.ll
M llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
M llvm/test/CodeGen/RISCV/atomic-rmw.ll
M llvm/test/CodeGen/RISCV/atomic-signext.ll
M llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/RISCV/bf16-promote.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/bfloat-mem.ll
M llvm/test/CodeGen/RISCV/bfloat.ll
M llvm/test/CodeGen/RISCV/bittest.ll
M llvm/test/CodeGen/RISCV/branch-on-zero.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/calling-conv-half.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32e.ll
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M llvm/test/CodeGen/RISCV/codemodel-lowering.ll
M llvm/test/CodeGen/RISCV/condbinops.ll
M llvm/test/CodeGen/RISCV/condops.ll
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
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M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
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M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
M llvm/test/CodeGen/RISCV/fastcc-bf16.ll
M llvm/test/CodeGen/RISCV/fastcc-float.ll
M llvm/test/CodeGen/RISCV/fastcc-half.ll
M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
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M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/float-select-fcmp.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
M llvm/test/CodeGen/RISCV/forced-atomics.ll
M llvm/test/CodeGen/RISCV/fp-fcanonicalize.ll
M llvm/test/CodeGen/RISCV/fp128.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/get-setcc-result-type.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-mem.ll
M llvm/test/CodeGen/RISCV/half-select-fcmp.ll
M llvm/test/CodeGen/RISCV/iabs.ll
M llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
M llvm/test/CodeGen/RISCV/inline-asm-d-modifier-N.ll
M llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
M llvm/test/CodeGen/RISCV/inline-asm-f-modifier-N.ll
M llvm/test/CodeGen/RISCV/inline-asm-zfinx-constraint-r.ll
M llvm/test/CodeGen/RISCV/inline-asm-zhinx-constraint-r.ll
M llvm/test/CodeGen/RISCV/inline-asm.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
M llvm/test/CodeGen/RISCV/legalize-fneg.ll
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M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
M llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll
M llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
M llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
M llvm/test/CodeGen/RISCV/mem.ll
M llvm/test/CodeGen/RISCV/mem64.ll
M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
M llvm/test/CodeGen/RISCV/memcmp.ll
M llvm/test/CodeGen/RISCV/memmove.ll
M llvm/test/CodeGen/RISCV/memset-pattern.ll
M llvm/test/CodeGen/RISCV/mul.ll
M llvm/test/CodeGen/RISCV/neg-abs.ll
M llvm/test/CodeGen/RISCV/orc-b-patterns.ll
M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
M llvm/test/CodeGen/RISCV/pr51206.ll
M llvm/test/CodeGen/RISCV/pr58511.ll
M llvm/test/CodeGen/RISCV/pr63816.ll
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
M llvm/test/CodeGen/RISCV/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/rv32-inline-asm-pairs.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv32zbs.ll
M llvm/test/CodeGen/RISCV/rv64-double-convert.ll
M llvm/test/CodeGen/RISCV/rv64-half-convert.ll
M llvm/test/CodeGen/RISCV/rv64-inline-asm-pairs.ll
M llvm/test/CodeGen/RISCV/rv64-trampoline.ll
M llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
M llvm/test/CodeGen/RISCV/rv64zbkb.ll
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll
M llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll
M llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
M llvm/test/CodeGen/RISCV/rvv/copyprop.mir
M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/expandload.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-addsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store-merge-crash.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll
M llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
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M llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll
M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
M llvm/test/CodeGen/RISCV/rvv/pr125306.ll
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M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
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M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/shrinkwrap.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.s.x.ll
M llvm/test/CodeGen/RISCV/rvv/vmv0-elimination.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-mask-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub-mask-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/wrong-chain-fixed-load.ll
M llvm/test/CodeGen/RISCV/scmp.ll
M llvm/test/CodeGen/RISCV/select-and.ll
M llvm/test/CodeGen/RISCV/select-bare.ll
M llvm/test/CodeGen/RISCV/select-cc.ll
M llvm/test/CodeGen/RISCV/select-constant-xor.ll
M llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
M llvm/test/CodeGen/RISCV/select-or.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/shift-amount-mod.ll
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/shl-cttz.ll
M llvm/test/CodeGen/RISCV/split-offsets.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/stack-slot-size.ll
M llvm/test/CodeGen/RISCV/stack-store-check.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/RISCV/ucmp.ll
M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
M llvm/test/CodeGen/RISCV/xtheadmempair.ll
M llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
M llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
M llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
A llvm/test/CodeGen/SPIRV/validate/triton-tut-softmax-kernel.ll
A llvm/test/CodeGen/Thumb2/bf16-pcs.ll
A llvm/test/CodeGen/Thumb2/fp16-pcs.ll
M llvm/test/CodeGen/X86/vec-strict-cmp-128-fp16.ll
M llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll
M llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll
M llvm/test/CodeGen/X86/vec-strict-fptoint-256.ll
M llvm/test/CodeGen/X86/vec-strict-fptoint-512.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
M llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-cvt.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmovn.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/qshrn.ll
M llvm/test/Instrumentation/MemorySanitizer/scmp.ll
M llvm/test/Instrumentation/MemorySanitizer/ucmp.ll
A llvm/test/LTO/X86/coro.ll
M llvm/test/MC/AArch64/armv8.1a-lse.s
M llvm/test/MC/AArch64/armv9.6a-lsui.s
M llvm/test/MC/AMDGPU/amdhsa-kd-kernarg-preload.s
M llvm/test/MC/AMDGPU/extrasgprs_mcexpr.s
R llvm/test/MC/AMDGPU/flat-scratch-gfx940.s
A llvm/test/MC/AMDGPU/flat-scratch-gfx942.s
R llvm/test/MC/AMDGPU/gfx940_asm_features.s
R llvm/test/MC/AMDGPU/gfx940_err.s
R llvm/test/MC/AMDGPU/gfx940_err_pos.s
R llvm/test/MC/AMDGPU/gfx940_unsupported.s
A llvm/test/MC/AMDGPU/gfx942_asm_features.s
A llvm/test/MC/AMDGPU/gfx942_err.s
A llvm/test/MC/AMDGPU/gfx942_err_pos.s
A llvm/test/MC/AMDGPU/gfx942_unsupported.s
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_asm_read_tr.s
M llvm/test/MC/AMDGPU/gfx950_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx950_asm_vop3.s
R llvm/test/MC/AMDGPU/mai-err-gfx940.s
A llvm/test/MC/AMDGPU/mai-err-gfx942.s
R llvm/test/MC/AMDGPU/mai-gfx940.s
A llvm/test/MC/AMDGPU/mai-gfx942.s
M llvm/test/MC/AMDGPU/mai-gfx950.s
R llvm/test/MC/AMDGPU/mimg-err-gfx940.s
A llvm/test/MC/AMDGPU/mimg-err-gfx942.s
M llvm/test/MC/AMDGPU/mubuf-gfx950.s
M llvm/test/MC/AMDGPU/writelane_m0.s
M llvm/test/MC/AMDGPU/xdl-insts-gfx908.s
M llvm/test/MC/Disassembler/AMDGPU/gfx908-xdl-insts.txt
R llvm/test/MC/Disassembler/AMDGPU/gfx940_features.txt
R llvm/test/MC/Disassembler/AMDGPU/gfx940_flat.txt
R llvm/test/MC/Disassembler/AMDGPU/gfx940_mai.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx942_features.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx942_flat.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx942_mai.txt
M llvm/test/MachineVerifier/AMDGPU/writelane_m0.mir
M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
M llvm/test/Other/new-pm-O0-defaults.ll
M llvm/test/Other/new-pm-lto-defaults.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i64-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i64-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd-flat-specialization.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2bf16-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2bf16-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2f16-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2f16-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-flat-noalias-addrspace.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-fp-vector.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-integer-ops-0-to-add-0.ll
A llvm/test/Transforms/DeadStoreElimination/captures-ret-only.ll
A llvm/test/Transforms/FunctionAttrs/sendmsg-nocallback.ll
M llvm/test/Transforms/InstCombine/add2.ll
M llvm/test/Transforms/InstCombine/ashr-lshr.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/load-i1-misaligned.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
A llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/NewGVN/2009-11-12-MemDepMallocBitCast.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/InstructionsState-is-invalid-0.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/horizontal-list.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll
M llvm/test/Transforms/SLPVectorizer/X86/bool-mask.ll
M llvm/test/Transforms/SLPVectorizer/X86/external-used-across-reductions.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract-scalar-from-undef.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractelemets-extended-by-poison.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
M llvm/test/Transforms/SLPVectorizer/X86/malformed_phis.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-tracked-reduced-value.ll
M llvm/test/Transforms/SLPVectorizer/X86/phi-node-reshuffled-part.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-val-extracted-and-externally-used.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduced-value-vectorized-later.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-extracted-value.ll
M llvm/test/Transforms/SLPVectorizer/X86/revectorized_rdx_crash.ll
A llvm/test/Transforms/SLPVectorizer/X86/same-values-sub-node-with-poisons.ll
M llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
M llvm/test/Transforms/SLPVectorizer/partial-register-extract.ll
M llvm/test/Transforms/SLPVectorizer/reduction-modified-values.ll
M llvm/test/Transforms/SLPVectorizer/scalarization-overhead.ll
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
M llvm/test/Transforms/SandboxVectorizer/bottomup_seed_slice_pow2.ll
M llvm/test/Transforms/SandboxVectorizer/repeated_instrs.ll
M llvm/test/Transforms/SandboxVectorizer/scheduler.ll
M llvm/test/tools/llvm-mca/AMDGPU/carried-over.s
R llvm/test/tools/llvm-mca/AMDGPU/gfx940-mfma.s
A llvm/test/tools/llvm-mca/AMDGPU/gfx942-mfma.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
M llvm/tools/llvm-profgen/MissingFrameInferrer.cpp
M llvm/unittests/CodeGen/CMakeLists.txt
A llvm/unittests/CodeGen/DroppedVariableStatsMIRTest.cpp
M llvm/unittests/IR/IRBuilderTest.cpp
M llvm/unittests/Support/ModRefTest.cpp
M llvm/unittests/Transforms/Utils/CloningTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/DependencyGraphTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/InstrMapsTest.cpp
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Passes/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
R mlir/docs/BufferDeallocationInternals.md
M mlir/docs/OwnershipBasedBufferDeallocation.md
R mlir/docs/includes/img/branch_example_post_move.svg
R mlir/docs/includes/img/branch_example_pre_move.svg
R mlir/docs/includes/img/nested_branch_example_post_move.svg
R mlir/docs/includes/img/nested_branch_example_pre_move.svg
R mlir/docs/includes/img/region_branch_example_pre_move.svg
A mlir/include/mlir-c/Dialect/Index.h
M mlir/include/mlir-c/IR.h
A mlir/include/mlir/Conversion/ComplexCommon/DivisionConverter.h
M mlir/include/mlir/Conversion/ComplexToLLVM/ComplexToLLVM.h
M mlir/include/mlir/Conversion/ComplexToStandard/ComplexToStandard.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/Affine/Passes.h
M mlir/include/mlir/Dialect/Affine/Passes.td
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.h
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.td
M mlir/include/mlir/Dialect/Complex/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/Complex/IR/Complex.h
M mlir/include/mlir/Dialect/Complex/IR/ComplexBase.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td
M mlir/include/mlir/Dialect/Tensor/IR/Tensor.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Bytecode/Writer/BytecodeWriter.cpp
M mlir/lib/CAPI/Dialect/CMakeLists.txt
A mlir/lib/CAPI/Dialect/Index.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/lib/Conversion/CMakeLists.txt
A mlir/lib/Conversion/ComplexCommon/CMakeLists.txt
A mlir/lib/Conversion/ComplexCommon/DivisionConverter.cpp
M mlir/lib/Conversion/ComplexToLLVM/CMakeLists.txt
M mlir/lib/Conversion/ComplexToLLVM/ComplexToLLVM.cpp
M mlir/lib/Conversion/ComplexToStandard/CMakeLists.txt
M mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopUnroll.cpp
R mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocation.cpp
M mlir/lib/Dialect/Bufferization/Transforms/CMakeLists.txt
M mlir/lib/Dialect/Linalg/Transforms/DataLayoutPropagation.cpp
M mlir/lib/Dialect/Math/Transforms/ExpandPatterns.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
A mlir/test/Conversion/ComplexToLLVM/complex-range-option.mlir
M mlir/test/Conversion/ComplexToLLVM/convert-to-llvm.mlir
M mlir/test/Conversion/ComplexToLLVM/full-conversion.mlir
A mlir/test/Conversion/ComplexToStandard/complex-range-option.mlir
A mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm-invalid-dialect.mlir
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
A mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-invalid-dialect.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
M mlir/test/Dialect/Affine/loop-fusion-2.mlir
M mlir/test/Dialect/Affine/loop-fusion-4.mlir
M mlir/test/Dialect/Affine/loop-fusion.mlir
M mlir/test/Dialect/Affine/unroll.mlir
R mlir/test/Dialect/Bufferization/Transforms/buffer-deallocation.mlir
M mlir/test/Dialect/Linalg/data-layout-propagation.mlir
M mlir/test/Dialect/Math/expand-math.mlir
M mlir/test/Dialect/SCF/loop-unroll.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/Pass/pipeline-invalid.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/omptarget-array-sectioning-host.mlir
M mlir/test/Target/LLVMIR/omptarget-constant-indexing-device-region.mlir
M mlir/test/Target/LLVMIR/omptarget-fortran-common-block-host.mlir
M mlir/test/Target/LLVMIR/omptarget-record-type-with-ptr-member-host.mlir
M mlir/test/Target/LLVMIR/openmp-private.mlir
M mlir/test/mlir-runner/test-expand-math-approx.mlir
M mlir/test/python/ir/module.py
M mlir/unittests/Bytecode/BytecodeTest.cpp
M utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h
M utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm_configs/config.h.cmake
Log Message:
-----------
Merge commit '660cdace559a8dbe44ebf2222b854bf3f39a5f62' into users/meinersbur/flang_runtime_move-files
Compare: https://github.com/llvm/llvm-project/compare/9a88083071e2...b12d925bc268
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