[all-commits] [llvm/llvm-project] 022fe3: RISCV: Implement isLoadFromStackSlot/isStoreToStac...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/riscv-is-load-store-stackslot-rvv
  Home:   https://github.com/llvm/llvm-project
  Commit: 022fe3bb690f32430665baef21f69f573867d661
      https://github.com/llvm/llvm-project/commit/022fe3bb690f32430665baef21f69f573867d661
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-02-13 (Thu, 13 Feb 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll

  Log Message:
  -----------
  RISCV: Implement isLoadFromStackSlot/isStoreToStackSlot for rvv

This partially helps avoid regressions in a future regalloc patch.
It isn't sufficient, and I think there are more missing implementations
of the copy and spill hooks.


  Commit: 4e4e7210b3275945616ba7471a8c06a8728e148b
      https://github.com/llvm/llvm-project/commit/4e4e7210b3275945616ba7471a8c06a8728e148b
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-02-13 (Thu, 13 Feb 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

  Log Message:
  -----------
  Add a few more opcodes found by asserting on frame indexes with mayLoad/mayStore.

One test looks like a regression, which is probably rematerialization not
being handled for something.


Compare: https://github.com/llvm/llvm-project/compare/6b9fb88955e0...4e4e7210b327

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