[all-commits] [llvm/llvm-project] 27c034: [Hexagon] Fix typos discovered by codespell (NFC) ...
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Wed Feb 12 22:01:29 PST 2025
Branch: refs/heads/users/vitalybuka/spr/libclang-always-dup-in-createref
Home: https://github.com/llvm/llvm-project
Commit: 27c034a9c69a659a2c1fa645f5cf1b50ecf61834
https://github.com/llvm/llvm-project/commit/27c034a9c69a659a2c1fa645f5cf1b50ecf61834
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
M llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
M llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
M llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
M llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
M llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
M llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Hexagon/HexagonLoopAlign.cpp
M llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
M llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
M llvm/lib/Target/Hexagon/HexagonPeephole.cpp
M llvm/lib/Target/Hexagon/HexagonPseudo.td
M llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
M llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp
M llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
M llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h
M llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
M llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp
M llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.h
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
Log Message:
-----------
[Hexagon] Fix typos discovered by codespell (NFC) (#126233)
Found using https://github.com/codespell-project/codespell
```
codespell Hexagon --write-changes \
--ignore-words-list=CarryIn,CreateOr,ORE,COPYs,ArchVer,predicable,UE,MIs,isNT,Vor,CountR,DUM,GEs,AddD,ToI, \
CopyIn,TheI,TotalIn,vor,MOne,contigious,Contigious
```
Commit: 170b9caf335eb99cdecba0fb6cdf45728bcac11d
https://github.com/llvm/llvm-project/commit/170b9caf335eb99cdecba0fb6cdf45728bcac11d
Author: Ben Shi <2283975856 at qq.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaAVR.cpp
M clang/lib/Sema/SemaMIPS.cpp
M clang/lib/Sema/SemaMSP430.cpp
M clang/lib/Sema/SemaRISCV.cpp
A clang/test/Sema/avr-interript-signal-attr.c
R clang/test/Sema/avr-interrupt-attr.c
R clang/test/Sema/avr-signal-attr.c
Log Message:
-----------
[clang][Sema] Emit warnings about incorrect AVR interrupt/signal handlers (#125997)
1. interrupt/signal handlers can not have parameters
2. interrupt/signal handlers must be 'void' type
Commit: 569e94f8f1c3e6998860e2b2ff577870433bdac9
https://github.com/llvm/llvm-project/commit/569e94f8f1c3e6998860e2b2ff577870433bdac9
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/lib/Serialization/ASTReaderDecl.cpp
A clang/test/Modules/pr126373.cppm
Log Message:
-----------
[C++20] [Modules] Don't diagnose duplicated declarations in different modules which is not in file scope
Close https://github.com/llvm/llvm-project/issues/126373
Although the root problems should be we shouldn't place the friend
declaration to the incorrect module, let's avoid bleeding the edge by
stoping diagnosing declarations not in file scope.
Commit: 1d6b31f7705541a9fb7d79bebe2cdbc3de7d9fb6
https://github.com/llvm/llvm-project/commit/1d6b31f7705541a9fb7d79bebe2cdbc3de7d9fb6
Author: Amir Bishara <139038766+amirBish at users.noreply.github.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer.mlir
Log Message:
-----------
[mlir]linalg][NFC]-Add lit test for tile and fuse transformation (#126216)
Add coverage for the fuse consumer transform for
`linalg.generic` operation with projected permutation indexing maps.
Commit: 0d8d354b0c2e9b11605290af3323ac63652e1abd
https://github.com/llvm/llvm-project/commit/0d8d354b0c2e9b11605290af3323ac63652e1abd
Author: YunQiang Su <syq at debian.org>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
R llvm/test/CodeGen/Mips/readcyclecounter.ll
Log Message:
-----------
Revert "[Mips] Support llvm.readcyclecounter intrinsic (#114953)"
This reverts commit 9cc7ee16e3bb849fb3c0155a843bfe349a2d2175.
Commit: be354cf3818222a114a098ed3637a67f8004b21f
https://github.com/llvm/llvm-project/commit/be354cf3818222a114a098ed3637a67f8004b21f
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M mlir/lib/Transforms/RemoveDeadValues.cpp
M mlir/test/Transforms/remove-dead-values.mlir
Log Message:
-----------
[mlir][transforms] Process RegionBranchOp with empty region (#123895)
This PR adds process for RegionBranchOp with empty region, such as
'else' region of `scf.if`. Fixes #123246.
Commit: 90192e8872cc90b4d292b180a49babf72d17e579
https://github.com/llvm/llvm-project/commit/90192e8872cc90b4d292b180a49babf72d17e579
Author: higher-performance <higher.performance.github at gmail.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/lib/Sema/SemaInit.cpp
M clang/test/SemaCXX/uninitialized.cpp
Log Message:
-----------
Fix false positive of [[clang::require_explicit_initialization]] on copy/move constructors (#126553)
Fixes #126490
Commit: 2cd8207b26ea4269630feba661f68554d7ae3c15
https://github.com/llvm/llvm-project/commit/2cd8207b26ea4269630feba661f68554d7ae3c15
Author: Piyou Chen <piyou.chen at sifive.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M compiler-rt/lib/builtins/cpu_model/riscv.c
Log Message:
-----------
[RISCV][compiler-rt] drop __riscv_vendor_feature_bits (#126460)
Address https://github.com/riscv-non-isa/riscv-c-api-doc/pull/101
Commit: dfbd764a551bf1a0c72bd3e76ac86297221448c0
https://github.com/llvm/llvm-project/commit/dfbd764a551bf1a0c72bd3e76ac86297221448c0
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
[clang][bytecode][NFC] Add failing memmove testcase (#126682)
Reduced from
libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char32_t/move.pass.cpp
Commit: 7af4ab4f072ee6de9d347f9955683d4a49645f1c
https://github.com/llvm/llvm-project/commit/7af4ab4f072ee6de9d347f9955683d4a49645f1c
Author: Petr Hosek <phosek at google.com>
Date: 2025-02-10 (Mon, 10 Feb 2025)
Changed paths:
M libc/src/complex/generic/CMakeLists.txt
M libc/src/math/generic/CMakeLists.txt
M libc/src/stdfix/CMakeLists.txt
Log Message:
-----------
[libc] Don't manually override the optimization level for math (#126322)
This was originally done for testing purposes, but after #126315 we now
do testing through GitHub Actions and should be instead using the
optimization setting chosen by the user.
Commit: a0587414cbb1520cfd7e886de1d18c408539ac9f
https://github.com/llvm/llvm-project/commit/a0587414cbb1520cfd7e886de1d18c408539ac9f
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M compiler-rt/lib/sanitizer_common/tests/sanitizer_libc_test.cpp
Log Message:
-----------
[sanitizer_common][test] Remove second SanitizerCommon.ReportFile tem… (#126509)
…p file
The `SanitizerCommon.ReportFile` test leaves a temp file behind on every
run. While this is not a problem for manual builds, on buildbots those
files accumulate over time, interfering with other bots on the same
system.
The files in question are named like
`sanitizer_common.reportfile.tmp.XXXXXX.<pid>`. The issue can be seen in
Solaris `truss` output:
```
22633: fstatat64(AT_FDCWD, "/tmp/sanitizer_common.reportfile.tmp.rzVEja", 0xFEFFBAD0, AT_SYMLINK_NOFOLLOW) Err#2 ENOENT
22633: openat64(AT_FDCWD, "/tmp/sanitizer_common.reportfile.tmp.rzVEja", O_RDWR|O_CREAT|O_EXCL, 0600) = 3
22633: openat64(AT_FDCWD, "/tmp/sanitizer_common.reportfile.tmp.rzVEja.22633", O_WRONLY|O_CREAT|O_TRUNC, 0660) = 4
22633: unlinkat(AT_FDCWD, "/tmp/sanitizer_common.reportfile.tmp.rzVEja", 0) = 0
```
The first temp file, created by `temp_file_name`, is removed at the end
of the test, the second one, created in `ReportFile::GetReportPath`
using `OpenFile`, is not.
This patch fixes this, simply removing the file.
Tested on `amd64-pc-solaris2.11` and `x86_64-pc-linux-gnu`.
Commit: d78b5ceb1661c5953563bf860f93b65f85fc4be0
https://github.com/llvm/llvm-project/commit/d78b5ceb1661c5953563bf860f93b65f85fc4be0
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/lib/Sema/HeuristicResolver.cpp
Log Message:
-----------
[clang][HeuristicResolver] Additional hardening against an infinite loop in simplifyType() (#126690)
Commit: 99e1308c41b24e2422324d68be28e5370196e5d6
https://github.com/llvm/llvm-project/commit/99e1308c41b24e2422324d68be28e5370196e5d6
Author: jeanPerier <jperier at nvidia.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/include/llvm/IR/InstrTypes.h
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
A mlir/test/Target/LLVMIR/Import/call-argument-attributes.ll
A mlir/test/Target/LLVMIR/Import/invoke-argument-attributes.ll
A mlir/test/Target/LLVMIR/call-argument-attributes.mlir
A mlir/test/Target/LLVMIR/invoke-argument-attributes.mlir
Log Message:
-----------
[mlir][LLVM] handle argument and result attributes in llvm.call and llvm.invoke (#123177)
Update llvm.call/llvm.invoke pretty printer/parser and the llvm ir import/export
to deal with the argument and result attributes.
This patch is made on top of PR 123176 that modified the
CallOpInterface and added the argument and result attributes to
llvm.call and llvm.invoke without doing anything with them.
RFC: https://discourse.llvm.org/t/mlir-rfc-adding-argument-and-result-attributes-to-llvm-call/84107
Commit: 6a961dc03d802fb1f34b2b0cd8d09f427382dbdb
https://github.com/llvm/llvm-project/commit/6a961dc03d802fb1f34b2b0cd8d09f427382dbdb
Author: Abhilash Majumder <30946547+abhilash1910 at users.noreply.github.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/prefetch.ll
Log Message:
-----------
[NVPTX] Add intrinsics for prefetch.* (#125887)
\[NVPTX\] Add Prefetch intrinsics
This PR adds prefetch intrinsics with the relevant eviction priorities.
* Lit tests are added as part of prefetch.ll
* The generated PTX is verified with a 12.3 ptxas executable.
* Added docs for these intrinsics in NVPTXUsage.rst.
For more information, refer PTX ISA
`<https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-prefetch-prefetchu>`_.
---------
Co-authored-by: abmajumder <abmajumder at nvidia.com>
Commit: 701223ac20a45d23b9b01c8a514294eb16219d79
https://github.com/llvm/llvm-project/commit/701223ac20a45d23b9b01c8a514294eb16219d79
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/llvm.sincospi.ll
A llvm/test/CodeGen/AArch64/veclib-llvm.sincospi.ll
Log Message:
-----------
[IR] Add llvm.sincospi intrinsic (#125873)
This adds the `llvm.sincospi` intrinsic, legalization, and lowering
(mostly reusing the lowering for sincos and frexp).
The `llvm.sincospi` intrinsic takes a floating-point value and returns
both the sine and cosine of the value multiplied by pi. It computes the
result more accurately than the naive approach of doing the
multiplication ahead of time, especially for large input values.
```
declare { float, float } @llvm.sincospi.f32(float %Val)
declare { double, double } @llvm.sincospi.f64(double %Val)
declare { x86_fp80, x86_fp80 } @llvm.sincospi.f80(x86_fp80 %Val)
declare { fp128, fp128 } @llvm.sincospi.f128(fp128 %Val)
declare { ppc_fp128, ppc_fp128 } @llvm.sincospi.ppcf128(ppc_fp128 %Val)
declare { <4 x float>, <4 x float> } @llvm.sincospi.v4f32(<4 x float> %Val)
```
Currently, the default lowering of this intrinsic relies on the
`sincospi[f|l]` functions being available in the target's runtime (e.g.
libc).
Commit: 67f59a642f96cdb0b73b991b96b5ca05b988e50d
https://github.com/llvm/llvm-project/commit/67f59a642f96cdb0b73b991b96b5ca05b988e50d
Author: Adam Siemieniuk <adam.siemieniuk at intel.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/test/Dialect/XeGPU/XeGPUOps.mlir
M mlir/test/Dialect/XeGPU/invalid.mlir
Log Message:
-----------
[mlir][xegpu] Improve scatter attribute definition (#126540)
Refactors XeGPU scatter attribute introducing following:
- improved docs formatting
- default initialized parameters
- invariant checks in attribute verifier
- removal of additional parsing error
The attribute's getters now provide default values simplifying their
usage and scattered tensor descriptor handling.
Related descriptor verifier is updated to avoid check duplication.
Commit: dd369c771e215ebf7bf2d09e874643788e49d334
https://github.com/llvm/llvm-project/commit/dd369c771e215ebf7bf2d09e874643788e49d334
Author: Victor Campos <victor.campos at arm.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M compiler-rt/test/builtins/Unit/arm/aeabi_idivmod_test.c
M compiler-rt/test/builtins/Unit/arm/aeabi_uidivmod_test.c
M compiler-rt/test/builtins/Unit/arm/aeabi_uldivmod_test.c
Log Message:
-----------
[compiler-rt] Fix tests of __aeabi_(idivmod|uidivmod|uldivmod) to support big endian (#126277)
This patch makes these functions' tests work in big endian mode:
- `__aeabi_idivmod`.
- `__aeabi_uidivmod`.
- `__aeabi_uldivmod`.
The three functions return a struct containing two fields, quotient and
remainder, via *value in regs* calling convention. They differ in the
integer type of each field.
In the tests of the first two, a 64-bit integer is used as the return
type of the call. And as consequence of the ABI rules for structs
(Composite Types), the quotient resides in `r0` and the remainder in
`r1` regardless of endianness. So, in order to access each component
from the 64-bit integer in the caller code, care must be taken to access
the correct bits as they do depend on endianness in this case.
In the test of the third one, the caller code has inline assembly to
access the components. This assembly code assumed little endian, so it
had to be made flexible for big endian as well.
`_YUGA_BIG_ENDIAN` is defined in `int_endianness.h`. It's a macro
internal to compiler-rt that's in theory compatible with more toolchains
than gcc and clang.
Commit: 19fc8e384680eca405b0f1cda9da5f5b2d1f91ab
https://github.com/llvm/llvm-project/commit/19fc8e384680eca405b0f1cda9da5f5b2d1f91ab
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/utils/git/github-automation.py
Log Message:
-----------
[GitHub] Correct word in commit access request greeting
Commit: 9fdb0633051121af24dfa00e8a762df10138ecc3
https://github.com/llvm/llvm-project/commit/9fdb0633051121af24dfa00e8a762df10138ecc3
Author: Ben Shi <2283975856 at qq.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/CallDescription.h
Log Message:
-----------
[clang][analyzer][NFC] Fix typos in comments (#126676)
Commit: 06f4fe331727d66187db9672629545755caa24db
https://github.com/llvm/llvm-project/commit/06f4fe331727d66187db9672629545755caa24db
Author: jeanPerier <jperier at nvidia.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M flang/test/Evaluate/rewrite-out_of_range.F90
Log Message:
-----------
[flang][NFC] fix rewrite-out_of_range.F90 tests (#126699)
There was a typo in the target, and REAL(16) parts needed to be
protected too.
Commit: 1a8d2a40167ea752366fa718a98cafdccce002a5
https://github.com/llvm/llvm-project/commit/1a8d2a40167ea752366fa718a98cafdccce002a5
Author: Tai Ly <tai.ly at arm.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/ops.mlir
Log Message:
-----------
[mlir][tosa] Use generic QuantizedType in Conv verifiers (#126275)
Replace UniformQuantizedType by the more generic QuantizedType in Conv verifiers.
Change-Id: Ie1961af931864f801914a62976bc988881ee075e
Signed-off-by: Tai Ly <tai.ly at arm.com>
Co-authored-by: Thibaut Goetghebuer-Planchon <thibaut.goetghebuer-planchon at arm.com>
Commit: 64735ad63975c1126f84dbf7921ce4341dfa2419
https://github.com/llvm/llvm-project/commit/64735ad63975c1126f84dbf7921ce4341dfa2419
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M libclc/CMakeLists.txt
A libclc/clc/include/clc/common/clc_sign.h
M libclc/clc/include/clc/math/gentype.inc
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/common/clc_sign.cl
A libclc/clc/lib/generic/common/clc_sign.inc
M libclc/generic/include/clc/float/definitions.h
M libclc/generic/lib/common/sign.cl
Log Message:
-----------
[libclc] Move sign to the CLC builtins library (#115699)
This commit moves the sign builtin's implementation to the CLC library.
It simultaneously optimizes it (for vector types) by removing
control-flow from the implementation.
The __CLC_INTERNAL preprocessor definition has been repurposed (without
the leading underscores) to be passed when building the internal CLC
library. It was only used in one other place to guard an extra maths
preprocessor definition, which we can do unconditionally.
Commit: a09beae271f209b2038bd503a1347bbf2e802568
https://github.com/llvm/llvm-project/commit/a09beae271f209b2038bd503a1347bbf2e802568
Author: Marcos Maronas <marcos.maronas at intel.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bit_instructions/cl_khr_extended_bit_ops.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bit_instructions/cl_khr_extended_bit_ops_ocl_only.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bit_instructions/cl_khr_extended_bit_ops_spv-friendly_only.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bit_instructions/spirv-friendly_extended_bit_ops.ll
Log Message:
-----------
[SPIRV] Add support for `cl_khr_extended_bit_ops` (#120571)
This PR adds support for `cl_khr_extended_bit_ops` in SPIRV Backend.
Note that `cl_khr_extended_bit_ops` only supports types in
```
char, charn, uchar, ucharn, short, shortn, ushort, ushortn, int, intn, uint, uintn, long, longn, ulong, and ulongn
```
where `n is 2, 3, 4, 8, or 16`.
Subsequent PRs will introduce support for non-standard bit width
required by `SPV_KHR_bit_instructions`.
Commit: 19556eccf650e2e273ebe7770cc32bd3a1786fa4
https://github.com/llvm/llvm-project/commit/19556eccf650e2e273ebe7770cc32bd3a1786fa4
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
Log Message:
-----------
[RTLIB] Rename getFSINCOS() to getSINCOS (NFC) (#126705)
This makes the name more consistent with the other helpers.
Commit: 8cf4c5576d4b9252301c834239791f70f42d94b8
https://github.com/llvm/llvm-project/commit/8cf4c5576d4b9252301c834239791f70f42d94b8
Author: Maya Amrami <62667278+amrami at users.noreply.github.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/test/Dialect/Bufferization/canonicalize.mlir
Log Message:
-----------
[mlir][bufferization] Canonicalize to_memref(to_tensor(x)) to a CopyO… (#126692)
…p if memory spaces differ
Commit: 2a5050aa5ef56b01cf4a8f73e0d0eddd6d9ce2a9
https://github.com/llvm/llvm-project/commit/2a5050aa5ef56b01cf4a8f73e0d0eddd6d9ce2a9
Author: Zichen Lu <mikaovo2000 at gmail.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M mlir/lib/Target/LLVM/NVVM/Target.cpp
M mlir/test/Dialect/GPU/module-to-binary-nvvm.mlir
M mlir/test/python/dialects/gpu/module-to-binary-nvvm.py
Log Message:
-----------
[mlir][target][nvvm] Perf by stage and store into properties (#126178)
Implement the feature about perf by stage(llvm-ir -> isa, isa->binary).
The results will be stored into the properties, then users can use them
after using GpuModuleToBinary Pass.
Commit: e258bca9505f35e0a22cb213a305eea9b76d11ea
https://github.com/llvm/llvm-project/commit/e258bca9505f35e0a22cb213a305eea9b76d11ea
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
A llvm/test/Transforms/LoopVectorize/X86/scev-checks-unprofitable.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
Log Message:
-----------
[VPlan] Only skip expansion for SCEVUnknown if it isn't an instruction. (#125235)
Update getOrCreateVPValueForSCEVExpr to only skip expansion of
SCEVUnknown if the underlying value isn't an instruction. Instructions
may be defined in a loop and using them without expansion may break
LCSSA form. SCEVExpander will take care of preserving LCSSA if needed.
We could also try to pass LoopInfo, but there are some users of the
function where it won't be available and main benefit from skipping
expansion is slightly more concise VPlans.
Note that SCEVExpander is now used to expand SCEVUnknown with floats.
Adjust the check in expandCodeFor to only check the types and casts if
the type of the value is different to the requested type. Otherwise we
crash when trying to expand a float and requesting a float type.
Fixes https://github.com/llvm/llvm-project/issues/121518.
PR: https://github.com/llvm/llvm-project/pull/125235
Commit: 560149b5e3c891c64899e9912e29467a69dc3a4c
https://github.com/llvm/llvm-project/commit/560149b5e3c891c64899e9912e29467a69dc3a4c
Author: Michael Flanders <flanders.michaelk at gmail.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StackAddrEscapeChecker.cpp
M clang/test/Analysis/copy-elision.cpp
M clang/test/Analysis/stack-addr-ps.cpp
M clang/test/Analysis/stackaddrleak.c
M clang/test/Analysis/stackaddrleak.cpp
Log Message:
-----------
[analyzer] Reapply recent stack addr escape checker changes + buildbot fix (#126620)
Reapplying changes from https://github.com/llvm/llvm-project/pull/125638
after buildbot failures.
Buildbot failures fixed in 029e7e98dc9956086adc6c1dfb0c655a273fbee6,
latest commit on this PR. It was a problem with a declared class member
with same name as its type. Sorry!
Commit: 73913275c414741b6c9789931fbab4470a181b00
https://github.com/llvm/llvm-project/commit/73913275c414741b6c9789931fbab4470a181b00
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
R clang/test/Analysis/no-outofbounds.c
M clang/test/Analysis/out-of-bounds-diagnostics.c
M clang/test/Analysis/out-of-bounds.c
Log Message:
-----------
[NFC][analyzer] OOB test consolidation I: no-outofbounds.c (#126539)
Before commit 6e17ed9b04e5523cc910bf171c3122dcc64b86db the test file
`no-outofbounds.c` tested the behavior of the old alpha checker
`alpha.security.ArrayBound` (V1); then that commit converted it into a
test for the checker `security.ArrayBound` which was previously called
`alpha.security.ArrayBoundV2`.
This commit removes this small separate test file and adds some tests to
the "native" test files of `security.ArrayBound` to ensure that the same
functionality is still tested.
This is intended as the first commit in a series that reorganizes the
tests of `security.ArrayBound` to system that's easier to understand and
maintain.
Commit: 82bd148a3f25439d7f52a32422dc1bcd2da03803
https://github.com/llvm/llvm-project/commit/82bd148a3f25439d7f52a32422dc1bcd2da03803
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M flang/CMakeLists.txt
M flang/include/flang/Optimizer/Dialect/CMakeLists.txt
M mlir/cmake/modules/MLIRConfig.cmake.in
Log Message:
-----------
[mlir][cmake] Do not export MLIR_MAIN_SRC_DIR and MLIR_INCLUDE_DIR (#125842)
MLIR_MAIN_SRC_DIR and MLIR_INCLUDE_DIR point to the source directory,
which is not installed. As such, the installed MLIRConfig.cmake also
should not reference it.
The comment indicates that these are needed for mlir_tablegen(), but I
don't see any related uses.
The motivation for this is the use in flang, where we end up inheriting
a meaningless MLIR_MAIN_SRC_DIR from a previous MLIR build, whose source
directory doesn't exist anymore, and that cannot be overridden with the
correct path, because it's not a cached variable.
Instead do what all the other projects do for LLVM_MAIN_SRC_DIR and
initialize MLIR_MAIN_SRC_DIR to CMAKE_CURRENT_SOURCE_DIR/../mlir.
For MLIR_INCLUDE_DIR there already is an exported MLIR_INCLUDE_DIRS,
which can be used instead.
Commit: 8d902f2cb0bc8825bcde911897e99aadbd5d28e9
https://github.com/llvm/llvm-project/commit/8d902f2cb0bc8825bcde911897e99aadbd5d28e9
Author: Yutong Zhu <115899167+YutongZhuu at users.noreply.github.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/JumpDiagnostics.cpp
A clang/test/CXX/stmt.stmt/stmt.select/stmt.switch/p4.cpp
Log Message:
-----------
[clang] Force AttributedStmtClass to not be scope parents (#125370)
Example from the issue:
```c++
void Func(int x) {
switch (x) {
[[likely]] case 0:
case 1:
int i = 3;
case 2:
break;
}
}
```
Clang checks if ``case 2`` can be reachable by checking its scope. The
variable declaration should create a scope containing ``case 2``, but
due to the structure of the AST, ``case 2`` gets the scope of the
``likely`` statement, but not ``int i = 3;``. Therefore, I changed this
code to force attribute statement not to be scope parents.
Fixes #84072
Commit: dd59198647b7be2e7a404d7bf9ecb247fb36ebad
https://github.com/llvm/llvm-project/commit/dd59198647b7be2e7a404d7bf9ecb247fb36ebad
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/amdgpu-branch-weight-metadata.ll
R llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
Log Message:
-----------
[NFC][AMDGPU] Rename test (#126725)
The demonte-scc transformation is no longer needed and the old test name
doesn't make sense anymore.
The test checks the generated assembly for different branch cases
* without metadata,
* with the same branch_weights on each edge and
* with a branch_weights that corresponds to the [[likely]] attribute
Commit: bf2d4eb7030b809004dd1e6d0cc15a94a9e18c88
https://github.com/llvm/llvm-project/commit/bf2d4eb7030b809004dd1e6d0cc15a94a9e18c88
Author: Michał Górny <mgorny at gentoo.org>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M lldb/source/Core/CMakeLists.txt
M lldb/source/Core/Telemetry.cpp
Log Message:
-----------
[lldb] Use preprocessor guard for `LLVM_BUILD_TELEMETRY` (#126715)
Use a preprocessor `#ifdef LLVM_BUILD_TELEMETRY` guard rather than
`PARTIAL_SOURCES_INTENDED` for the `Telemetry.cpp` file, to fix building
with telemetry disabled. `PARTIAL_SOURCES_INTENDED` does not currently
work in `lldb_add_library()`, and while it could be fixed, it seems to
be used contrary to its purpose — in other parts of LLVM project, the
option is used to indicate that the sources found in the directory are
split between different targets (e.g. a library and a tool), not to
include sources conditionally.
Commit: d89c23b487dfb96718f9f72f2841a83906cc3d0b
https://github.com/llvm/llvm-project/commit/d89c23b487dfb96718f9f72f2841a83906cc3d0b
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Core/BUILD.gn
Log Message:
-----------
[gn build] Port bf2d4eb7030b
Commit: dbe1dafdbde247d9c133626cc38a8c587a49344f
https://github.com/llvm/llvm-project/commit/dbe1dafdbde247d9c133626cc38a8c587a49344f
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenSchedule.h
M llvm/utils/TableGen/InstrInfoEmitter.cpp
Log Message:
-----------
[NFC][TableGen] Code cleanup in InstrInfoEmitter.cpp (#126578)
- Use range for loops and `enumerate` in a few places.
- Use `StringRef` for `TargetName` in `InstrInfoEmitter::run`.
- Use `\n` character for new line instead of string.
- Use StringRef in `InstrNames` (instead of std::string) and
avoid string copies.
Commit: efc72347fd26e30a3f751348bee6a404cf18237a
https://github.com/llvm/llvm-project/commit/efc72347fd26e30a3f751348bee6a404cf18237a
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/fully-unrolled-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
Log Message:
-----------
[AArch64] Improve getPartialReductionCost for fixed-width VFs (#126538)
NEON does not have a version of udot/sdot that accumulates into
64-bit integer values, so we should return Invalid from
getPartialReductionCost for 64-bit types and fixed-width VFs.
In theory, if the 64-bit versions of SVE udot/sdot are available
we could use those, but we don't currently have lowering support
for that.
Commit: 04589d1795ed4698766f5a26b6d7f32207968792
https://github.com/llvm/llvm-project/commit/04589d1795ed4698766f5a26b6d7f32207968792
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/test/CMakeLists.txt
M llvm/test/CodeGen/SPIRV/lit.local.cfg
M llvm/tools/spirv-tools/CMakeLists.txt
Log Message:
-----------
[SPIR-V] Add SPIR-V Linker (#126319)
I want to use `spirv-link` from `SPIR-V-Tools` in a test, so let's build
it if `LLVM_INCLUDE_SPIRV_TOOLS_TESTS` is set, as we do with the other
tools.
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: 94f9d5d1a8257710f0483ce025e19a6326ca6e4b
https://github.com/llvm/llvm-project/commit/94f9d5d1a8257710f0483ce025e19a6326ca6e4b
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/linker-wrapper.c
M clang/test/Driver/sycl-offload-jit.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
Log Message:
-----------
[Offload] Treat an empty packager architecture as 'generic' (#126655)
Summary:
The `clang-offload-packager` records the architecture of the job.
Currently there are cases where this will be empty. SYCL, CPU, and when
the user manually overrides it to be empty. In these cases we should
alwas consider it 'generic'. Adding this string both makes it clear how
it behaves and triggers the special handling for this architecture,
allowing it to bind to different architectures.
Commit: c837f572865eb2980b82a8415da45dc1157627bf
https://github.com/llvm/llvm-project/commit/c837f572865eb2980b82a8415da45dc1157627bf
Author: Vigneshwar Jayakumar <vigneshwar.jayakumar at amd.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx940.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-mfma-scale.gfx950.mir
Log Message:
-----------
AMDGPU: Handle gfx950 XDL-write-VGPR-Overlap-Src-AB wait state (#126732)
gfx950 needs more additional waitstates from gfx940
Commit: 9387fd96314c59fc9aff1a82e478f9b89a97c20a
https://github.com/llvm/llvm-project/commit/9387fd96314c59fc9aff1a82e478f9b89a97c20a
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/cxx26.cpp
Log Message:
-----------
[clang][bytecode] Fix diagnosing replaceable global allocator functions (#126717)
Don't return true here in InvalidNewDeleteExpr just because we are in
C++26 mode. This invalid there as well.
Testcase reduced from
libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.create/make_unique_for_overwrite.pass.cpp
Commit: ab93bd6959d6d2df1b44c1654938452dc30898b0
https://github.com/llvm/llvm-project/commit/ab93bd6959d6d2df1b44c1654938452dc30898b0
Author: Hsiangkai Wang <hsiangkai.wang at arm.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/tosa-reduce-transposes.mlir
Log Message:
-----------
[mlir][tosa] Change ClampOp's min/max attributes (#125197)
This changes Tosa ClampOp attributes to min_val and max_val which are
either integer attributes or float attributes, and adds verify checks
that these attribute element types must match element types of input and
output
Co-authored-by: Tai Ly <tai.ly at arm.com>
Commit: 5bf42d3e2e83344db14fc0e33623840c53cebfc4
https://github.com/llvm/llvm-project/commit/5bf42d3e2e83344db14fc0e33623840c53cebfc4
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M lldb/source/API/SBDebugger.cpp
Log Message:
-----------
[lldb] Fix ubsan violation with plugin loading (#126652)
This typedef doesn't match the signature below, specifically the
signature takes a `lldb:SBDebugger` vs this was defined as
`lldb:SBDebugger&`.
```
lldb/source/API/SBDebugger.cpp:199:13: runtime error: call to function lldb::PluginInitialize(lldb::SBDebugger) through pointer to incorrect function type 'bool (*)(lldb::SBDebugger &)'
.../CustomPlugin.cpp:134: note: lldb::PluginInitialize(lldb::SBDebugger) defined here
```
Commit: b7188f6313fef2d5a248e71ba6028460b2ac0558
https://github.com/llvm/llvm-project/commit/b7188f6313fef2d5a248e71ba6028460b2ac0558
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
Log Message:
-----------
[AMDGPU][NFC] Remove an unneeded return value. (#126739)
And rename the function to disassociate it from the one where generating
loading of the input value may actually fail.
Commit: 2ad9d5f5f01cd4f29788a0cf7b21790df13fca71
https://github.com/llvm/llvm-project/commit/2ad9d5f5f01cd4f29788a0cf7b21790df13fca71
Author: Michał Górny <mgorny at gentoo.org>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/cmake/modules/LLVMConfig.cmake.in
Log Message:
-----------
[llvm] [cmake] Expose `LLVM_BUILD_TELEMETRY` in `LLVMConfig.cmake` (#126710)
Add `LLVM_BUILD_TELEMETRY` to the list of flags exposed in
`LLVMConfig.cmake`. This fixes telemetry library being misdetected as
`OFF` when building LLDB standalone.
Fixes bac62ee5b473e70981a6bd9759ec316315fca07d.
------
I guess this also needs a backport to 20.x.
Commit: 76392421553f3b25552970812868f70721971451
https://github.com/llvm/llvm-project/commit/76392421553f3b25552970812868f70721971451
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
M llvm/test/MC/AMDGPU/hsa-gfx12-v4.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx11.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx12.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx11.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx12.s
Log Message:
-----------
[AMDGPU] Create new directive .amdhsa_inst_pref_size (#126622)
The field INST_PREF_SIZE is available since gfx11.
Commit: 2f54223247e8f9f0fc006b944de8351f376814af
https://github.com/llvm/llvm-project/commit/2f54223247e8f9f0fc006b944de8351f376814af
Author: sitrin <michael.s.adams at gmail.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/docs/TypeSanitizer.rst
Log Message:
-----------
[Docs] Fix typo in TypeSanitizer.rst "tale" -> "table" (NFC) (#126721)
The word `table` is now in place of the word `tale`.
Fixes #126719.
Co-authored-by: sitrin <sitrin at users.noreply.github.com>
Commit: b3510a88b3c19645fbde09cb58af6dead68ebd36
https://github.com/llvm/llvm-project/commit/b3510a88b3c19645fbde09cb58af6dead68ebd36
Author: Florian Mayer <fmayer at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
Log Message:
-----------
[NFC] [clang] simplify isDesignatorAtObjectEnd (#126658)
IsLastOrInvalidFieldDecl would always return true if `Invalid=true`, so
we know that !IsLastOrInvalidFieldDecl(...) means !Invalid.
Commit: 8e4e1449318de0e73192edf0b3c6a0d5b6ec7a31
https://github.com/llvm/llvm-project/commit/8e4e1449318de0e73192edf0b3c6a0d5b6ec7a31
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
Log Message:
-----------
[CodeGen] Avoid repeated hash lookups (NFC) (#126672)
Commit: c50f924aeae2d2eded772a7a80b20d46e1c9b41e
https://github.com/llvm/llvm-project/commit/c50f924aeae2d2eded772a7a80b20d46e1c9b41e
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/lib/Sema/SemaOpenMP.cpp
Log Message:
-----------
[Sema] Avoid repeated hash lookups (NFC) (#126674)
Commit: 43c82a8e07819ad0553ef0dffedff3c8b8cecf5e
https://github.com/llvm/llvm-project/commit/43c82a8e07819ad0553ef0dffedff3c8b8cecf5e
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/tools/clang-installapi/Options.cpp
Log Message:
-----------
[clang-installapi] Avoid repeated hash lookups (NFC) (#126677)
Commit: 497506f6f454272e7c4921b3143768c6927738e4
https://github.com/llvm/llvm-project/commit/497506f6f454272e7c4921b3143768c6927738e4
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Analysis/DDG.cpp
Log Message:
-----------
[Analysis] Avoid repeated hash lookups (NFC) (#126678)
Commit: c9686d6904f24de8c63294dd708c9e0d0b4f7a47
https://github.com/llvm/llvm-project/commit/c9686d6904f24de8c63294dd708c9e0d0b4f7a47
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
Log Message:
-----------
[SystemZ] Avoid repeated hash lookups (NFC) (#126679)
Commit: 042e860a8a3a2e1be384a5de04b90607ce32e294
https://github.com/llvm/llvm-project/commit/042e860a8a3a2e1be384a5de04b90607ce32e294
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[Vectorize] Avoid repeated hash lookups (NFC) (#126681)
Commit: cf87eb9d9b006ff28296e399dcc73d68bb187e91
https://github.com/llvm/llvm-project/commit/cf87eb9d9b006ff28296e399dcc73d68bb187e91
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/InstCombine/known-bits.ll
Log Message:
-----------
[ValueTracking] Handle trunc to i1 as condition in dominating condition. (#126414)
proof: https://alive2.llvm.org/ce/z/gALGmv
Commit: f574d8235371c4f28cad8e800d99bcb7ad579b7d
https://github.com/llvm/llvm-project/commit/f574d8235371c4f28cad8e800d99bcb7ad579b7d
Author: Sharjeel Khan <sharjeelkhan at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/test/Driver/dep-file-flag-with-multiple-offload-archs.hip
Log Message:
-----------
[Clang][Driver][HIP] Fix test for HIP as it was failing (#126585)
This PR #125646 added this test and it was failing in Android's compiler
and on my machine locally. I removed the "Build config" check and it
passes now.
Commit: c3d8c625af8ebbf8a9af035c18ec4e1cb1d8d2f3
https://github.com/llvm/llvm-project/commit/c3d8c625af8ebbf8a9af035c18ec4e1cb1d8d2f3
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-private-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-private.f90
Log Message:
-----------
[flang][acc] Fill-in name for privatized loop iv (#126601)
When the loop induction variable implicit private clause was being
generated, the name was left empty. The intent is that the data clause
operation holds the source language variable name. Thus, add the missing
name now.
Commit: 75cb5633844deb4e0c6a5c7bdf84013b563818d3
https://github.com/llvm/llvm-project/commit/75cb5633844deb4e0c6a5c7bdf84013b563818d3
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/include/clang/AST/ASTContext.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/Sema/SemaDecl.cpp
Log Message:
-----------
[clang][Sema] Move computing enum bits into a separate function (#126096)
Move the code that computes `NumNegativeBits` and `NumPositiveBits` for
an enum to a separate function in `ASTContext.h`.
This function needs to be called from LLDB as well (#115005)
Commit: 42538ca3a0db6513a1a01fca88dccd34bd0d9641
https://github.com/llvm/llvm-project/commit/42538ca3a0db6513a1a01fca88dccd34bd0d9641
Author: Aaron Siddhartha Mondal <aaron at tracemachina.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
[GitHub] Add aaronmondal to Bazel codeowners (#126760)
Commit: b92bab3c010a8b8d7c2273ebdacfa34aaaaa757d
https://github.com/llvm/llvm-project/commit/b92bab3c010a8b8d7c2273ebdacfa34aaaaa757d
Author: S. Bharadwaj Yadavalli <Bharadwaj.Yadavalli at microsoft.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/test/CodeGenHLSL/inline-functions.hlsl
Log Message:
-----------
[HLSL] Appropriately set function attribute optnone (#125937)
When optimization is disabled, set `optnone` attribute all module entry
functions.
Updated test in accordance with the change.
Closes #124796
Commit: b8ba266820ca51216c98216369a4947a942ec21c
https://github.com/llvm/llvm-project/commit/b8ba266820ca51216c98216369a4947a942ec21c
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M libc/test/src/stdbit/stdc_bit_ceil_uc_test.cpp
M libc/test/src/stdbit/stdc_bit_ceil_us_test.cpp
M libc/test/src/stdbit/stdc_first_leading_one_uc_test.cpp
M libc/test/src/stdbit/stdc_first_leading_one_us_test.cpp
M libc/test/src/stdbit/stdc_first_leading_zero_uc_test.cpp
M libc/test/src/stdbit/stdc_first_leading_zero_us_test.cpp
M libc/test/src/stdbit/stdc_first_trailing_one_uc_test.cpp
M libc/test/src/stdbit/stdc_first_trailing_one_us_test.cpp
M libc/test/src/stdbit/stdc_first_trailing_zero_uc_test.cpp
M libc/test/src/stdbit/stdc_first_trailing_zero_us_test.cpp
M libc/test/src/stdbit/stdc_has_single_bit_uc_test.cpp
M libc/test/src/stdbit/stdc_has_single_bit_us_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_uc_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_us_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_uc_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_us_test.cpp
M libc/test/src/stdbit/stdc_trailing_ones_uc_test.cpp
M libc/test/src/stdbit/stdc_trailing_ones_us_test.cpp
M libc/test/src/stdbit/stdc_trailing_zeros_uc_test.cpp
M libc/test/src/stdbit/stdc_trailing_zeros_us_test.cpp
Log Message:
-----------
[libc][test][stdbit] fix -Wimplicit-int-conversion (#126616)
When cross compiling the libc-stdbit-tests, the existing tests trigger numerous
instances of -Wimplicit-int-conversion. The truncation of these implicit
promotions is intentional.
Commit: 6d58dd4dd9fa24d66bdab64f0f905926081a9944
https://github.com/llvm/llvm-project/commit/6d58dd4dd9fa24d66bdab64f0f905926081a9944
Author: Wael Yehia <wyehia at ca.ibm.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[Release Notes] Mention -fprofile-continuous in release notes
Commit: 1337b0fe3c153ee8b7c8e19d694b9840a64ccf3a
https://github.com/llvm/llvm-project/commit/1337b0fe3c153ee8b7c8e19d694b9840a64ccf3a
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/docs/analyzer/developer-docs/PerformanceInvestigation.rst
A clang/docs/analyzer/images/flamegraph.png
A clang/docs/analyzer/images/uftrace_detailed.png
Log Message:
-----------
[analyzer][docs] Document how to use perf and uftrace to debug performance issues (#126724)
Commit: 55ae118db7c36fb88994e072e424cb66d1f34e74
https://github.com/llvm/llvm-project/commit/55ae118db7c36fb88994e072e424cb66d1f34e74
Author: Aaron Siddhartha Mondal <aaron at tracemachina.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/utils/git/code-format-helper.py
Log Message:
-----------
[GitHub] Skip undefcheck if no relevant files changed (#126749)
If the list of filtered files was empty the check would process every
file in the diff.
Commit: 918848d03bb9d0e06dea2ef588bda17ff961923c
https://github.com/llvm/llvm-project/commit/918848d03bb9d0e06dea2ef588bda17ff961923c
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M lldb/include/lldb/Core/UserSettingsController.h
M lldb/source/Core/UserSettingsController.cpp
Log Message:
-----------
[lldb] Devirtualize GetValueProperties (NFC) (#126583)
Nobody is overriding GetValueProperties, so in practice we're always
using `m_collection_sp`, which means we don't need to check the pointer.
The temlated helpers were already operating on `m_collection_sp`
directly so this makes the rest of the class consistent.
Commit: 71478ecdb48075051e6e746c4c51b9caeb4c21b6
https://github.com/llvm/llvm-project/commit/71478ecdb48075051e6e746c4c51b9caeb4c21b6
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-obj-arg.mm
Log Message:
-----------
[WebKit Checkers] Treat const Objective-C ivar as a safe origin (#126353)
Like const C++ member variables, treat const Ref, RefPtr, CheckedRef,
CheckedPtr Objective-C ivars as a safe pointer origin in WebKit
checkers.
Commit: a2263eba4d3be0daa96bd154de3b8f2a67aa67fb
https://github.com/llvm/llvm-project/commit/a2263eba4d3be0daa96bd154de3b8f2a67aa67fb
Author: Vigneshwar Jayakumar <vigneshwar.jayakumar at amd.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx940.mir
Log Message:
-----------
AMDGPU: Handle gfx950 XDL-write-VGPR-VALU-Mem-Exp wait state change (#126727)
Commit: 1188b1ff7b956cb65d8ddda5f1e56c432f1a57c7
https://github.com/llvm/llvm-project/commit/1188b1ff7b956cb65d8ddda5f1e56c432f1a57c7
Author: Vigneshwar Jayakumar <vigneshwar.jayakumar at amd.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx940.mir
Log Message:
-----------
AMDGPU: Handle gfx950 XDL Write-VGPR-VALU-WAW wait state change (#126132)
There are additional wait states for XDL write VALU WAW hazard in gfx950
compared to gfx940.
Commit: 71e623d878ecbf66324e15b3a3b2e983e2d7942a
https://github.com/llvm/llvm-project/commit/71e623d878ecbf66324e15b3a3b2e983e2d7942a
Author: Elvin Wang <elvin.wang at intel.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/IR/DebugInfo.cpp
A llvm/test/Transforms/Util/strip-nonlinetable-debuginfo-pr125116.ll
Log Message:
-----------
[llvm] Avoid out-of-order evaluation in DebugInfo (#125116)
This is an upstream proposal from
https://github.com/intel/intel-graphics-compiler/commit/e60884cb98c4332a0eecff8396eb353c5b86cd35
We observed malfunctioning StripNonLineTableDebugInfo during debugging
and it's caused by out-of-order evaluation, this is a C++ level semantic
ambiguity issue, refer
https://en.cppreference.com/w/cpp/language/eval_order
Solution is simply separating one line into two.
Commit: 9d7177a2d7e63f90effea848e897cbf96690d154
https://github.com/llvm/llvm-project/commit/9d7177a2d7e63f90effea848e897cbf96690d154
Author: Renaud Kauffmann <rkauffmann at nvidia.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/test/Analysis/AliasAnalysis/alias-analysis-2.fir
A flang/test/Analysis/AliasAnalysis/alias-analysis-target.fir
Log Message:
-----------
[flang][NFCI] Stop tracking memory source after a load in a more explicit manner. (#126156)
Typically, we do not track memory sources after a load because of the
dynamic nature of the load and the fact that the alias analysis is a
simple static analysis.
However, the code is written in a way that makes it seem like we are
continuing to track memory but in reality we are only doing so when we
know that the tracked memory is a leaf and therefore when there will
only be one more iteration through the switch statement. In other words,
we are iterating one more time, to gather data about a box, anticipating
that this will be the last time. This is a hack that helped avoid
cut-and-paste from other case statements but gives the wrong impression
about the intention of the code and makes it confusing.
To make it clear that there is no more tracking, we gather all the
necessary data from the memref of the load, in the case statement for
the load, and exit the loop. I am also limiting this data gathering for
the case when we load a box reference while we were actually following
data, as tests have shows, is the only case when we need it for. Other
cases will be handled conservatively, but this can change in the future,
on a case-by-case basis.
---------
Co-authored-by: Joel E. Denny <jdenny.ornl at gmail.com>
Commit: 070f84ebc89b11df616a83a56df9ac56efbab783
https://github.com/llvm/llvm-project/commit/070f84ebc89b11df616a83a56df9ac56efbab783
Author: Zahira Ammarguellat <zahira.ammarguellat at intel.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/bindings/python/clang/cindex.py
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang-c/Index.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/StmtOpenMP.h
M clang/include/clang/Basic/StmtNodes.td
M clang/include/clang/Sema/SemaOpenMP.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/lib/AST/StmtOpenMP.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/Basic/OpenMPKinds.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/SemaExceptionSpec.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
A clang/test/Index/openmp-stripe.c
A clang/test/OpenMP/stripe_ast_print.cpp
A clang/test/OpenMP/stripe_codegen.cpp
A clang/test/OpenMP/stripe_messages.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CXCursor.cpp
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[Clang] [OpenMP] Add support for '#pragma omp stripe'. (#119891)
Implement basic parsing and semantic support for `#pragma omp stripe`
constuct introduced in
https://www.openmp.org/wp-content/uploads/[OpenMP-API-Specification-6-0.pdf](https://www.openmp.org/wp-content/uploads/OpenMP-API-Specification-6-0.pdf),
section 11.7.
Commit: 20ae283d087224f6b82b7308054bd34a6764d926
https://github.com/llvm/llvm-project/commit/20ae283d087224f6b82b7308054bd34a6764d926
Author: Tai Ly <tai.ly at arm.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaReduceTransposes.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/constant-op-fold.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/tosa-reduce-transposes.mlir
Log Message:
-----------
[mlir][tosa] Change the shift of mul to be required (#125297)
Change the shift operand for the mul operator to be a required operand.
Also defined shift to be Tosa_ScalarInt8Tensor which requires that it is
a rank-1 tensor
whose shape is [1] (ie, tensor containing a single element)
Signed-off-by: Tai Ly <tai.ly at arm.com>
Commit: 8c67f14f628420a5e06fe631ec6b323f096f2a43
https://github.com/llvm/llvm-project/commit/8c67f14f628420a5e06fe631ec6b323f096f2a43
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-counted-const-member.cpp
M clang/test/Analysis/Checkers/WebKit/mock-types.h
Log Message:
-----------
[WebKit Checkers] Allow operator T&() in a const member function (#126470)
Allow operator T&() in a member function which returns a const member
variable.
In particular, this will allow UniqueRef::operator T&() and
Ref::operator T&() to be treated as a safe pointer origin when they're
called on a const member.
Commit: c4fe4561c7893596a5e519d7275df5ea5f0886be
https://github.com/llvm/llvm-project/commit/c4fe4561c7893596a5e519d7275df5ea5f0886be
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++] Fixes building with Python 3.8.
This addresses the post-commit issues reported in #101880.
Commit: 1bf1f13be94fa5f4994d10310ec349cc3450d70f
https://github.com/llvm/llvm-project/commit/1bf1f13be94fa5f4994d10310ec349cc3450d70f
Author: quic-areg <aregmi at quicinc.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
Log Message:
-----------
[Hexagon][Disassembler] Set CommentStream of Disassembler (#126766)
Sets CommentStream after assert added in #125962.
Commit: 401f4b828c374a01de6acd7fd8f4a3a4245f7595
https://github.com/llvm/llvm-project/commit/401f4b828c374a01de6acd7fd8f4a3a4245f7595
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M flang/runtime/CMakeLists.txt
Log Message:
-----------
[flang][rt] Add decimal files to device runtime (#126778)
The library FortranDecimal is not used anymore with the runtime but its
files are now integrated. Add the files for the device build as well.
Commit: c2fea0d837c481c2c1f00077778f84de54c0196f
https://github.com/llvm/llvm-project/commit/c2fea0d837c481c2c1f00077778f84de54c0196f
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/test/CMakeLists.txt
M clang/test/Tooling/clang-linker-wrapper-spirv-elf.cpp
M clang/test/Tooling/lit.local.cfg
Log Message:
-----------
[clang-linker-wrapper][lit] Fix SPIR-V ELF test when spirv-tools feature is available (#126756)
My last change made the test not run when the `spirv-tools` feature is
not available, which is always the case in CI for clang tests, but it
fails if `spirv-tools` is available for the following reasons:
1) We didn't build `spirv-link` as part of the internal `SPIRV-Tools`
build, which is required by the `clang` call in `clang-linker-wrapper`,
I already fixed that
[here](https://github.com/llvm/llvm-project/pull/126319).
2) We didn't depend on the `SPIRV-Tools` CMake targets in clang tests,
so depending on what CMake targets were built before running
`check-clang`, `SPIRV-Tools` might not have been built.
3) We didn't check for `llvm-spirv` being available, which is not part
of `SPIRV-Tools` but is currently required for SPIR-V compilation.
Manually confirmed this works. This test is the bane of my existence.
---------
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: 2cf6663d3c86b065edeb693815e6a4b325045cc2
https://github.com/llvm/llvm-project/commit/2cf6663d3c86b065edeb693815e6a4b325045cc2
Author: Kevin Gleason <gleasonk at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M mlir/test/mlir-tblgen/gen-dialect-doc.td
A mlir/test/mlir-tblgen/gen-pass-doc.td
M mlir/tools/mlir-tblgen/OpDocGen.cpp
M mlir/tools/mlir-tblgen/OpInterfacesGen.cpp
M mlir/tools/mlir-tblgen/PassDocGen.cpp
M utils/bazel/llvm-project-overlay/mlir/test/mlir-tblgen/BUILD.bazel
Log Message:
-----------
[MLIR] Make generated markdown doc more consistent (#119926)
A few changes to doc generation:
- All summaries are in italics.
- In general each optional block starts and ends with a newline.
- All table elements are enclosed in `|`'s
- Overall reduce the number of >2newlines in a row
Rationale for this change is that our markdown to docs generator
requires a newline before all headers, otherwise it gets inlined into
the line before it, see `### sdy-op-priority-propagate` in the image
below.
<img width="883" alt="image"
src="https://github.com/user-attachments/assets/b795c424-cecb-48df-abbe-aee2030f4491"
/>
That said overall I feel this formatting is more consistent now, here's
a before and after:
- Dialect documentation diff: https://www.diffchecker.com/OVMHoXeL/
- Pass documentation diff: https://www.diffchecker.com/XEJRmW3k/
Commit: 67e1e98811ccb438e951ae59dd3041a2baf84437
https://github.com/llvm/llvm-project/commit/67e1e98811ccb438e951ae59dd3041a2baf84437
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/bindings/python/clang/cindex.py
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang-c/Index.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/StmtOpenMP.h
M clang/include/clang/Basic/StmtNodes.td
M clang/include/clang/Sema/SemaOpenMP.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/lib/AST/StmtOpenMP.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/Basic/OpenMPKinds.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/SemaExceptionSpec.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
R clang/test/Index/openmp-stripe.c
R clang/test/OpenMP/stripe_ast_print.cpp
R clang/test/OpenMP/stripe_codegen.cpp
R clang/test/OpenMP/stripe_messages.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CXCursor.cpp
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
Revert "[Clang] [OpenMP] Add support for '#pragma omp stripe'. (#119891)"
This reverts commit 070f84ebc89b11df616a83a56df9ac56efbab783.
Buildbot failure:
https://lab.llvm.org/buildbot/#/builders/51/builds/10694
Commit: e4016bf5c32558e773264d1ce875d71cf67bd192
https://github.com/llvm/llvm-project/commit/e4016bf5c32558e773264d1ce875d71cf67bd192
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[DAG] Use ArrayRef to simplify ShuffleVectorSDNode::isSplatMask
Commit: baf7a3c1e561ff7e3f7da2261ce1012c4f2ba1c0
https://github.com/llvm/llvm-project/commit/baf7a3c1e561ff7e3f7da2261ce1012c4f2ba1c0
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M offload/plugins-nextgen/common/include/RPC.h
M offload/plugins-nextgen/common/src/RPC.cpp
Log Message:
-----------
[Offload] Properly guard modifications to the RPC device array (#126790)
Summary:
If the user deallocates an RPC device this can sometimes fail if the RPC
server is still running. This will happen if the modification happens
while the server is still checking it. This patch adds a mutex to guard
modifications to it.
Commit: 3ef5348a0486def3e53ce37b9ed8b8ca020a3a12
https://github.com/llvm/llvm-project/commit/3ef5348a0486def3e53ce37b9ed8b8ca020a3a12
Author: David Green <david.green at arm.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
A llvm/test/Transforms/PhaseOrdering/AArch64/udotabd.ll
Log Message:
-----------
[AArch64] Add a phase-order test for dot patterns. NFC
Commit: 5c7071e996b8b26080219038c2eb262567c18769
https://github.com/llvm/llvm-project/commit/5c7071e996b8b26080219038c2eb262567c18769
Author: Florian Mayer <fmayer at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
Log Message:
-----------
[NFC] [clang] fix unused variable warning (#126796)
Commit: 3c74430320619495d4d547b05427654c9a7c8586
https://github.com/llvm/llvm-project/commit/3c74430320619495d4d547b05427654c9a7c8586
Author: Alireza Torabian <torabian.alireza at gmail.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/include/llvm/Analysis/DDG.h
M llvm/include/llvm/Analysis/DependenceAnalysis.h
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/Analysis/DependenceGraphBuilder.cpp
M llvm/lib/Analysis/LoopCacheAnalysis.cpp
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Utils/CodeMoverUtils.cpp
M llvm/lib/Transforms/Utils/LoopUnrollAndJam.cpp
Log Message:
-----------
[DependenceAnalysis][NFC] Removing PossiblyLoopIndependent parameter (#124615)
Parameter PossiblyLoopIndependent has lost its intended purpose. This
flag is always set to true in all cases when depends() is called, hence
we want to reconsider the utility of this variable and remove it from
the function signature entirely. This is an NFC patch.
Commit: 188915535a2c42f347076e49ad95271c11e9a05d
https://github.com/llvm/llvm-project/commit/188915535a2c42f347076e49ad95271c11e9a05d
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
Log Message:
-----------
[RISCV] Add coverage for vmerge.vim shuffle lowering
Commit: b88b6a2b633a942d454205f336703cdc62074686
https://github.com/llvm/llvm-project/commit/b88b6a2b633a942d454205f336703cdc62074686
Author: Florian Mayer <fmayer at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/include/clang/Basic/FPOptions.def
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Basic/LangOptions.h
Log Message:
-----------
[clang] Assert the enum FPOpts and LangOpts fit into the storage (#126166)
Fix existing failure
Commit: fcbf04e40e66014f455a38b59993be865bc6cdfd
https://github.com/llvm/llvm-project/commit/fcbf04e40e66014f455a38b59993be865bc6cdfd
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
Log Message:
-----------
[mlir][vector][nfc] Add clarification on "dim-1" bcast (#125425)
Adds a small note to VectorOps.td on what "dim-1" broadcast is. Also
updates comments to consistently use quotes, i.e.
* "dim-1" broadcasting instead of dim-1 broadcasting.
This way it is clear that we are referring to "stretching" one of the
trailing dims rather than e.g. broadcasting a dim at idx 1.
Commit: 10844fb9b0b78695243391e091e17ec29295872a
https://github.com/llvm/llvm-project/commit/10844fb9b0b78695243391e091e17ec29295872a
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/SystemZ/reuse-non-power-of-2-reorder.ll
Log Message:
-----------
[SLP]Fix attempt to build the reorder mask for non-adjusted reuse mask
When building the reorder for non-single use reuse mask, need to check
if the size of the mask is multiple of the number of unique scalars.
Otherwise, the compiler may crash when trying to reorder nodes.
Fixes #126304
Commit: ad905f133c5b22896900f3f335de990d0daf1ff4
https://github.com/llvm/llvm-project/commit/ad905f133c5b22896900f3f335de990d0daf1ff4
Author: Florian Mayer <fmayer at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
Log Message:
-----------
[NFC] [clang] Use isa instead of dyn_cast
Commit: 07600f80c7790b31826392ee5edfbd3ccd9f55bc
https://github.com/llvm/llvm-project/commit/07600f80c7790b31826392ee5edfbd3ccd9f55bc
Author: vporpo <vporpodas at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Scheduler.h
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/SchedulerTest.cpp
Log Message:
-----------
[SandboxVec][Scheduler] Update ready list comparator (#126160)
This patch implements a hierarchical comparator for the ready list. PHIs
have higher priority than non-phis and terminators are always last.
Commit: f6556afce0aa5a72ef42103875101d975e810474
https://github.com/llvm/llvm-project/commit/f6556afce0aa5a72ef42103875101d975e810474
Author: Shoaib Meenai <smeenai at fb.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M mlir/include/mlir/IR/OperationSupport.h
Log Message:
-----------
[mlir] Silence -Wdangling-assignment-gsl in OperationSupport.h (#126140)
This warning is causing lots of build spam when I use a recent Clang as
my host compiler. It's a potential false positive, so silence it until
https://github.com/llvm/llvm-project/issues/126600 is resolved.
Fix variable casing while I'm here.
Commit: 0419db6b95e246fe9dc90b5795beb77c393eb2ce
https://github.com/llvm/llvm-project/commit/0419db6b95e246fe9dc90b5795beb77c393eb2ce
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M libc/utils/docgen/docgen.py
M libc/utils/docgen/sys/time.yaml
Log Message:
-----------
[libc][docgen] make note of sys/time.h interfaces removed in POSIX.1-2024 (#126612)
One of these days, we'll be able to specify time to a computer...
Also, POSIX can remove stuff all they want. Folks probably will continue to
depend on broken interfaces forever.
Link: #124654
Link: https://austingroupbugs.net/view.php?id=1330
Commit: c7eb5204a631986f0a8d6c204c5bc5135e3efc1c
https://github.com/llvm/llvm-project/commit/c7eb5204a631986f0a8d6c204c5bc5135e3efc1c
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/lib/Sema/HeuristicResolver.cpp
M clang/unittests/Sema/HeuristicResolverTest.cpp
Log Message:
-----------
[clang][HeuristicResolver] Track the expression whose type is being simplified after each step in simplifyType() (#126689)
Fixes https://github.com/llvm/llvm-project/issues/126536
Commit: fd41393e2e6a32a7fcacdd0779f70964689d01ec
https://github.com/llvm/llvm-project/commit/fd41393e2e6a32a7fcacdd0779f70964689d01ec
Author: lntue <lntue at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M libc/src/__support/FPUtil/double_double.h
M libc/src/__support/macros/optimization.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/atan2f.cpp
A libc/src/math/generic/atan2f_float.h
M libc/src/math/generic/pow.cpp
M libc/src/math/generic/range_reduction_double_fma.h
M libc/src/math/generic/range_reduction_double_nofma.h
Log Message:
-----------
[libc][math] Add float-only option for atan2f. (#122979)
For targets that have single precision FPU but not double precision FPU
such as Cortex M4, only using float-float in the intermediate
computations might reduce the code size compared to using double. In
this case, when the exact pass is skipped, the float-only option for
atan2f implemented in this PR reduces the code size of this function by
~1 KB compared to the double precision version.
Commit: ad6cd7e8b2590dcbb8aed92ac416ca889986471d
https://github.com/llvm/llvm-project/commit/ad6cd7e8b2590dcbb8aed92ac416ca889986471d
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
Log Message:
-----------
[AMDGPU][True16][CodeGen] true16 codegen for MadFmaMixPat (#124892)
true16 codegen for MadFmaMixPat. GISEL test not enabled and will be
added later when GISEL is supported
Commit: a760e7faacb79e7ff0ae23d3ae370d1aa6e52666
https://github.com/llvm/llvm-project/commit/a760e7faacb79e7ff0ae23d3ae370d1aa6e52666
Author: Michael Jones <michaelrj at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M libc/include/llvm-libc-types/struct_tm.h
M libc/src/time/CMakeLists.txt
M libc/src/time/mktime.cpp
M libc/src/time/time_constants.h
M libc/src/time/time_utils.cpp
M libc/src/time/time_utils.h
Log Message:
-----------
[libc] create TimeReader to look at a struct tm (#126138)
In the process of adding strftime (#122556) I wrote this utility class
to simplify reading from a struct tm. It provides helper functions that
return basically everything needed by strftime. It's not tested
directly, but it is thoroughly exercised by the strftime tests.
Commit: 8374d421861cd3d47e21ae7889ba0b4c498e8d85
https://github.com/llvm/llvm-project/commit/8374d421861cd3d47e21ae7889ba0b4c498e8d85
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
Log Message:
-----------
[RISCV] Decompose single source shuffles (without exact VLEN) (#126108)
This is a continuation of the work started in #125735 to lower selected
VLA shuffles in linear m1 components instead of generating O(LMUL^2) or
O(LMUL*Log2(LMUL) high LMUL shuffles.
This pattern focuses on shuffles where all the elements being used
across the entire destination register group come from a single register
in the source register group. Such cases come up fairly frequently via
e.g. spread(N), and repeat(N) idioms.
One subtlety to this patch is the handling of the index vector for
vrgatherei16.vv. Because the index and source registers can have
different EEW, the index vector for the Nth chunk of the destination is
not guaranteed to be register aligned. In fact, it is common for e.g. an
EEW=64 shuffle to have EEW=16 indices which are four chunks per source
register. Given this, we have to pay a cost for extracting these chunks
into the low position before performing each shuffle.
I'd initially expressed this as a naive extract sub-vector for each data
parallel piece. However, at high LMUL, this quickly caused register
pressure problems since we could at worst need 4x the temporary
registers for the index. Instead, this patch uses a repeating slidedown
chained from previous iterations. This increases critical path by at
worst 3 slides (SEW=64 is the worst case), but reduces register pressure
to at worst 2x - and only if the original index vector is reused
elsewhere. I view this as arguably a bit of a workaround (since our
scheduling should have done better with the plain extract variant), but
a probably neccessary one.
Commit: 84fe1f63b02414085bf7a8434caaf4a358be86da
https://github.com/llvm/llvm-project/commit/84fe1f63b02414085bf7a8434caaf4a358be86da
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
M llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.h
M llvm/include/llvm/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.h
M llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.cpp
M llvm/lib/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink-executor/llvm-jitlink-executor.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
Log Message:
-----------
[ORC] Switch to singleton pattern for UnwindInfoManager. (#126691)
The find-dynamic-unwind-info callback registration APIs in libunwind
limit the number of callbacks that can be registered. If we use multiple
UnwindInfoManager instances, each with their own own callback function
(as was the case prior to this patch) we can quickly exceed this limit
(see https://github.com/llvm/llvm-project/issues/126611).
This patch updates the UnwindInfoManager class to use a singleton
pattern, with the single instance shared between all LLVM JITs in the
process.
This change does _not_ apply to compact unwind info registered through
the ORC runtime (which currently installs its own callbacks).
As a bonus this change eliminates the need to load an IR "bouncer"
module to supply the unique callback for each instance, so support for
compact-unwind can be extended to the llvm-jitlink tools (which does not
support adding IR).
Commit: 376f65d865282d32c12f47a3247968e16025d1ef
https://github.com/llvm/llvm-project/commit/376f65d865282d32c12f47a3247968e16025d1ef
Author: Shoaib Meenai <smeenai at fb.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M mlir/include/mlir/IR/OperationSupport.h
Log Message:
-----------
Revert "[mlir] Silence -Wdangling-assignment-gsl in OperationSupport.h (#126140)"
This reverts commit f6556afce0aa5a72ef42103875101d975e810474.
Buildbots are broken.
Commit: 3a22cf9bd85f77b5274304eda6f90d758f0a6664
https://github.com/llvm/llvm-project/commit/3a22cf9bd85f77b5274304eda6f90d758f0a6664
Author: Daniel Hoekwater <hoekwater at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetFrameLowering.h
M llvm/lib/CodeGen/CFIFixup.cpp
M llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.h
M llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir
Log Message:
-----------
[CFIFixup] Fixup CFI for split functions with synchronous uwtables (#125299)
- **Precommit tests for synchronous uwtable CFI fixup**
- **[CFIFixup] Fixup CFI for split functions with synchronous uwtables**
Commit
https://github.com/llvm/llvm-project/commit/6e54fccede402c9ed0e8038aa258a99c5a2773e5
disables CFI fixup for
functions with synchronous tables, breaking CFI for split functions.
Instead, we can disable *block-level* CFI fixup for functions with
synchronous tables.
Unwind tables can be:
- N/A (not present)
- Asynchronous
- Synchronous
Functions without unwind tables don't need CFI fixup (since they don't
care about CFI).
Functions with asynchronous unwind tables must be accurate for each
basic block, so full CFI fixup is necessary.
Functions with synchronous unwind tables only need to be accurate for
each function (specifically, the portion of a function in a given
section). Disabling CFI fixup entirely for functions with synchronous
uwtables may break CFI for a function split between two sections. The
portion in the first section may have valid CFI, while the portion in
the second section is missing a call frame.
Ex:
```
(.text.hot)
Foo (BB1):
<Call frame information>
...
BB2:
...
(.text.split)
BB3:
...
BB4:
<epilogue>
```
Even if `Foo` has a synchronous unwind table, we still need to insert
call frame information into `BB3` so that unwinding the call stack from
`BB3` or `BB4` works properly.
Commit: 17721b7b1474331f67cf89ff95056b27eb1f5029
https://github.com/llvm/llvm-project/commit/17721b7b1474331f67cf89ff95056b27eb1f5029
Author: lntue <lntue at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M libc/src/__support/FPUtil/double_double.h
M libc/src/math/generic/range_reduction_double_common.h
Log Message:
-----------
[libc][NFC] Remove DEFAULT_DOUBLE_SPLIT macro. (#126822)
Commit: 9f61a60c777465c8a1bb67f80560a9e3b4d0f05b
https://github.com/llvm/llvm-project/commit/9f61a60c777465c8a1bb67f80560a9e3b4d0f05b
Author: Florian Mayer <fmayer at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.cpp
Log Message:
-----------
[NFC] [clang] fixed unused variable warning
Commit: ab0006ddba3e977c44e1e761909e09603816b32c
https://github.com/llvm/llvm-project/commit/ab0006ddba3e977c44e1e761909e09603816b32c
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
Log Message:
-----------
[RISCV] Allow undef prefix for local repeating VLA shuffle lowering (#126097)
Implement the first TODO from #125735, and minorly cleanup code using
same style as the recently landed strict prefix case.
Commit: 022c9c9d3ac39c1f5a3efe143972dff4b62090b6
https://github.com/llvm/llvm-project/commit/022c9c9d3ac39c1f5a3efe143972dff4b62090b6
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/test/CodeGen/NVPTX/addrspacecast.ll
Log Message:
-----------
[NVPTX] Lower invalid `ISD::ADDRSPACECAST` (#125607)
Avoid [crashing](https://godbolt.org/z/8T58vcM68) when lowering
`addrspacecast ptr addrspace(<non-zero>) %ptr to ptr
addrspace(<non-zero>)`.
Commit: a6a5507e368c8a69f5ed1796f3eeb3a5e9acd119
https://github.com/llvm/llvm-project/commit/a6a5507e368c8a69f5ed1796f3eeb3a5e9acd119
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
Log Message:
-----------
Revert "[RISCV] Allow undef prefix for local repeating VLA shuffle lowering (#126097)"
This reverts commit ab0006ddba3e977c44e1e761909e09603816b32c. It appears to have rebased badly during web merge.
Commit: 36d8e7056ef08d0f51e5b1e928274a8ca7dadeb5
https://github.com/llvm/llvm-project/commit/36d8e7056ef08d0f51e5b1e928274a8ca7dadeb5
Author: Arda Unal <3157490+ardaunal at users.noreply.github.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
M mlir/include/mlir/Interfaces/LoopLikeInterface.td
M mlir/include/mlir/Interfaces/SideEffectInterfaces.h
M mlir/include/mlir/Transforms/LoopInvariantCodeMotionUtils.h
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Interfaces/SideEffectInterfaces.cpp
M mlir/lib/Transforms/Utils/LoopInvariantCodeMotionUtils.cpp
M mlir/test/Transforms/loop-invariant-code-motion.mlir
M mlir/test/lib/Dialect/Test/TestOps.td
Log Message:
-----------
[mlir] Enable LICM for ops with only read side effects in scf.for (#120302)
Enable ops with only read side effects in scf.for to be hoisted with a
scf.if guard that checks against the trip count
This patch takes a step towards a less conservative LICM in MLIR as
discussed in the following discourse thread:
[Speculative LICM?](https://discourse.llvm.org/t/speculative-licm/80977)
This patch in particular does the following:
1. Relaxes the original constraint for hoisting that only hoists ops
without any side effects. This patch also allows the ops with only read
side effects to be hoisted into an scf.if guard only if every op in the
loop or its nested regions is side-effect free or has only read side
effects. This scf.if guard wraps the original scf.for and checks for
**trip_count > 0**.
2. To support this, two new interface methods are added to
**LoopLikeInterface**: _wrapInTripCountCheck_ and
_unwrapTripCountCheck_. Implementation starts with wrapping the scf.for
loop into scf.if guard using _wrapInTripCountCheck_ and if there is no
op hoisted into the this guard after we are done processing the
worklist, it unwraps the guard by calling _unwrapTripCountCheck_.
Commit: b72079e75dbbe94752c3c187d79828845a65327d
https://github.com/llvm/llvm-project/commit/b72079e75dbbe94752c3c187d79828845a65327d
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.cpp
Log Message:
-----------
[ExecutionEngine] Fix a warning
This patch fixes:
llvm/lib/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.cpp:53:20:
error: unused variable 'AddFnName' [-Werror,-Wunused-variable]
Commit: 31c4d17fbce07a77b34973a7e275c1e2182039b5
https://github.com/llvm/llvm-project/commit/31c4d17fbce07a77b34973a7e275c1e2182039b5
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.cpp
Log Message:
-----------
[ExecutionEngine] Fix formatting (NFC)
Commit: 574ccc6d1b85e9e93b674152ab60df3b0deed86f
https://github.com/llvm/llvm-project/commit/574ccc6d1b85e9e93b674152ab60df3b0deed86f
Author: Michael Jones <michaelrj at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M libc/src/time/time_utils.h
Log Message:
-----------
[libc] fix get_epoch constexpr error (#126818)
get_epoch calls mktime_internal which isn't constexpr. For now, just
remove the constexpr from get_epoch.
Commit: 934c97dd16ae8048ae009d97be7d80db4e1dee66
https://github.com/llvm/llvm-project/commit/934c97dd16ae8048ae009d97be7d80db4e1dee66
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-pointer-ops.ll
Log Message:
-----------
[LowerBufferFatPointers] Fix support for GEP T, p7, <N x T> idxs (#126126)
The lowering for GEP didn't properly support the case where the pointer
argument was being implicitly broadcast by a vector of indices. Fix
that.
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: 9db0f91ceb6c5065fa7b119888e0fe15702300d3
https://github.com/llvm/llvm-project/commit/9db0f91ceb6c5065fa7b119888e0fe15702300d3
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M compiler-rt/lib/scudo/standalone/chunk.h
M compiler-rt/lib/scudo/standalone/report.cpp
M compiler-rt/lib/scudo/standalone/report.h
M compiler-rt/lib/scudo/standalone/tests/report_test.cpp
Log Message:
-----------
[scudo] Modify header corrupption error message (#126812)
Update the error message to be explicit that this is likely due to
memory corruption.
In addition, check if the chunk header is all zero, which could mean
corruption or an attempt to free a pointer after the memory has been
released to the kernel. This case results in a slightly different error
message to also indicate this could still be a double free.
Commit: f15a6c99fa552f82dad46e6bf3c8ff958c8b6e7f
https://github.com/llvm/llvm-project/commit/f15a6c99fa552f82dad46e6bf3c8ff958c8b6e7f
Author: donald chen <chenxunyu1993 at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/lib/Analysis/DataFlow/IntegerRangeAnalysis.cpp
M mlir/test/Interfaces/InferIntRangeInterface/infer-int-range-test-ops.mlir
Log Message:
-----------
[mlir] [DataFlow] Fix bug in int-range-analysis (#126708)
When querying the lower bound and upper bound of loop to update the
value range of a loop iteration variable, the program point to depend on
should be the block corresponding to the iteration variable rather than
the loop operation.
Commit: 82cbb02cbc79bfcadc77385535caf3813d82cac0
https://github.com/llvm/llvm-project/commit/82cbb02cbc79bfcadc77385535caf3813d82cac0
Author: lonely eagle <2020382038 at qq.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm-interface.mlir
Log Message:
-----------
[mlir][vector][NFC] Fix typos in tests (#126662)
[mlir][vector] Fix typos in tests (nfc)
Fix typos in `{insert|extract}_scalar_from_vec_2d_f32_dynamic_idxs_compile_time_constant` - the intention was to use `f32` rather than `i32`.
Commit: 6de4de893188b1b548417c8073fa929d4befb16d
https://github.com/llvm/llvm-project/commit/6de4de893188b1b548417c8073fa929d4befb16d
Author: c8ef <c8ef at outlook.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M libc/include/llvm-libc-macros/CMakeLists.txt
M libc/include/llvm-libc-macros/endian-macros.h
Log Message:
-----------
[libc] implement endian related macros (#126368)
Follow up of #125168.
This patch adds endian-related macros to `endian.h`. We utilize compiler
built-ins for byte swap functions, which are already included in our
minimal supported compiler version.
Commit: bfbe5319a8d0e96d90687be009b77a21820b91f8
https://github.com/llvm/llvm-project/commit/bfbe5319a8d0e96d90687be009b77a21820b91f8
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vadd.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll
Log Message:
-----------
[msan] Add handlePairwiseShadowOrIntrinsic and use it to handle Arm NEON pairwise add (#126008)
This patch adds a function, handlePairwiseShadowOrIntrinsic that ORs
pairs of adjacent shadow values; this is suitable for propagating shadow
for 1- or 2-vector intrinsics that combine adjacent fields. It then
applies handlePairwiseShadowOrIntrinsic to Arm NEON pairwise add:
llvm.aarch64.neon.{addhn, raddhn} (currently incorrectly handled) and
llvm.aarch64.neon.{saddlp, uaddlp} (currently suboptimally handled).
Updates the tests from https://github.com/llvm/llvm-project/pull/125820.
Commit: a0fbc19ad6bcc77ee7c9e5161d5ac23f90da0aa0
https://github.com/llvm/llvm-project/commit/a0fbc19ad6bcc77ee7c9e5161d5ac23f90da0aa0
Author: Jie Fu <jiefu at tencent.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
Log Message:
-----------
[MemorySanitizer] Silence an unused-variable warning (NFC)
/llvm-project/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp:2622:22:
error: unused variable 'ReturnType' [-Werror,-Wunused-variable]
FixedVectorType *ReturnType = cast<FixedVectorType>(I.getType());
^
1 error generated.
Commit: acd34d90d3acd9dd260fdb93c54f70c222e26875
https://github.com/llvm/llvm-project/commit/acd34d90d3acd9dd260fdb93c54f70c222e26875
Author: Miguel A. Arroyo <miguel.arroyo at rockstargames.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/cmake/modules/AddClang.cmake
Log Message:
-----------
[Clang][CMake][MSVC] Install PDBs alongside executables (#126675)
* Follows up on https://github.com/llvm/llvm-project/pull/120683
enabling PDBs for `clang`.
Commit: cc7e83601d759349b0ded7d75b5550f3c625dfcf
https://github.com/llvm/llvm-project/commit/cc7e83601d759349b0ded7d75b5550f3c625dfcf
Author: Luke Lau <luke at igalia.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/CMakeLists.txt
M llvm/lib/Target/RISCV/RISCV.h
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
A llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select.mir
M llvm/test/CodeGen/RISCV/O0-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/rvv/copyprop.mir
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll
M llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops-mir.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload-vpstore-output.ll
M llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll
A llvm/test/CodeGen/RISCV/rvv/vmv0-elimination.ll
Log Message:
-----------
[RISCV] Select mask operands as virtual registers and eliminate uses of vmv0 (#125026)
This is another attempt at #88496 to keep mask operands in SSA after
instruction selection.
Previously we selected the mask operands into vmv0, a singleton register
class with exactly one register, V0.
But the register allocator doesn't really support singleton register
classes and we ran into errors like "ran out of registers during
register allocation in function".
This avoids this by introducing a pass just before register allocation
that converts any use of vmv0 to a copy to $v0, i.e. what isel currently
does today.
That way the register allocator doesn't need to deal with the singleton
register class, but we get the benefits of having the mask registers in
SSA throughout the backend:
- This allows RISCVVLOptimizer to reduce the VLs of instructions that
define mask registers
- It enables CSE and code sinking in more places
- It removes the need to peek through mask copies in RISCVISelDAGToDAG
and keep track of V0 defs in RISCVVectorPeephole
This patch initially eliminates uses of vmv0s after RISCVVectorPeephole
to keep the diff to a minimum, and a follow up patch will move it past
the other MachineInstr SSA passes.
Note that it doesn't try to remove any defs of vmv0 as we shouldn't have
any instructions that have any vmv0 outputs.
As a further follow up, we can move the elimination pass to after phi
elimination and outside of SSA, which would unblock the pre-RA scheduler
around masked pseudos. This might also help the issue that
RISCVVectorMaskDAGMutation tries to solve.
Commit: 4a63ff4330342aeb4a4f62cca32cfcd07ba91cab
https://github.com/llvm/llvm-project/commit/4a63ff4330342aeb4a4f62cca32cfcd07ba91cab
Author: Hongtao Yu <hoy at meta.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
M mlir/include/mlir/Interfaces/LoopLikeInterface.td
M mlir/include/mlir/Interfaces/SideEffectInterfaces.h
M mlir/include/mlir/Transforms/LoopInvariantCodeMotionUtils.h
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Interfaces/SideEffectInterfaces.cpp
M mlir/lib/Transforms/Utils/LoopInvariantCodeMotionUtils.cpp
M mlir/test/Transforms/loop-invariant-code-motion.mlir
M mlir/test/lib/Dialect/Test/TestOps.td
Log Message:
-----------
Revert "[mlir] Enable LICM for ops with only read side effects in scf.for" (#126840)
Reverts llvm/llvm-project#120302
Commit: caa9fae2e7bd61aa73bdd4b77933b067078e822f
https://github.com/llvm/llvm-project/commit/caa9fae2e7bd61aa73bdd4b77933b067078e822f
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
Log Message:
-----------
[gn build] Port cc7e83601d75
Commit: 31bfae35d26ac07636f944cdbe140ccd9ee8eca6
https://github.com/llvm/llvm-project/commit/31bfae35d26ac07636f944cdbe140ccd9ee8eca6
Author: Jim Lin <jim at andestech.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/align-down.ll
M llvm/test/CodeGen/X86/align-down.ll
M llvm/test/CodeGen/X86/not-of-dec.ll
Log Message:
-----------
[DAGCombiner] Add hasOneUse checks for folding (not (add X, -1)) to (neg X) (#126667)
To get more better codegen for AArch with bic, x86 with andn and riscv
with andn.
Commit: df2dca7a73db58289cd95ac9058c9338dc0bd2fd
https://github.com/llvm/llvm-project/commit/df2dca7a73db58289cd95ac9058c9338dc0bd2fd
Author: Abhishek Kaushik <abhishek.kaushik at intel.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/include/llvm/MC/MCELFStreamer.h
Log Message:
-----------
[MC] Use `std::move` to avoid copy (#126700)
Commit: 84e3c6ff9591d4e93b5a30dbcffc985d41d87bda
https://github.com/llvm/llvm-project/commit/84e3c6ff9591d4e93b5a30dbcffc985d41d87bda
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp
Log Message:
-----------
[RISCV] Fix a warning
THis patch fixes:
llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp:91:29: error: unused
variable 'TRI' [-Werror,-Wunused-variable]
Commit: 9e5c136d5a1a8acee9e7acfbe14cc6d4490dee2e
https://github.com/llvm/llvm-project/commit/9e5c136d5a1a8acee9e7acfbe14cc6d4490dee2e
Author: Ethan Luis McDonough <ethanluismcdonough at gmail.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M compiler-rt/lib/profile/InstrProfiling.h
M compiler-rt/lib/profile/InstrProfilingFile.c
M offload/include/Shared/Environment.h
M offload/plugins-nextgen/common/include/GlobalHandler.h
M offload/plugins-nextgen/common/src/GlobalHandler.cpp
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/test/lit.cfg
M offload/test/lit.site.cfg.in
M offload/test/offloading/pgo1.c
M openmp/docs/design/Runtimes.rst
Log Message:
-----------
[PGO][Offload] Profile profraw generation for GPU instrumentation #76587 (#93365)
This pull request is the second part of an ongoing effort to extends PGO
instrumentation to GPU device code and depends on #76587. This PR makes
the following changes:
- Introduces `__llvm_write_custom_profile` to PGO compiler-rt library.
This is an external function that can be used to write profiles with
custom data to target-specific files.
- Adds `__llvm_write_custom_profile` as weak symbol to libomptarget so
that it can write the collected data to a profraw file.
- Adds `PGODump` debug flag and only displays dump when the
aforementioned flag is set
Commit: 9c725ef368fb3e6f797833a2354533d1f1c4ad45
https://github.com/llvm/llvm-project/commit/9c725ef368fb3e6f797833a2354533d1f1c4ad45
Author: Vikram Hegde <115221833+vikramRH at users.noreply.github.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
A llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
Log Message:
-----------
[AMDGPU][NewPM] Port "GCNRewritePartialRegUses" pass to NPM (#126024)
Commit: d222488007b294e897fb5c29971d87c3148ae33b
https://github.com/llvm/llvm-project/commit/d222488007b294e897fb5c29971d87c3148ae33b
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
Log Message:
-----------
[AsmParser] Remove OperandMatchResultTy (#126650)
This has been deprecated since a479be0f39a3301e9ca634d37cf6454b6d3865c6
from September 2023, before LLVM 18. Surely now enough release cycles
have happened that it can be removed upstream.
Commit: ec28e9b7579347f0ba00882850fdc99218da7c20
https://github.com/llvm/llvm-project/commit/ec28e9b7579347f0ba00882850fdc99218da7c20
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/include/llvm/MC/MCContext.h
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/MC/MCContext.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/MC/MCParser/WasmAsmParser.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
Log Message:
-----------
[MC] Replace MCContext::GenericSectionID with MCSection::NonUniqueID (#126202)
They have same semantics. NonUniqueID is more friendly for isUnique
implementation in MCSectionELF.
History: 97837b7 added support for unique IDs in sections and added
GenericSectionID. Later, 1dc16c7 added NonUniqueID.
Commit: 52ee06d2730ebcc6e97d63eea222901a3f3d71d8
https://github.com/llvm/llvm-project/commit/52ee06d2730ebcc6e97d63eea222901a3f3d71d8
Author: Ethan Luis McDonough <ethanluismcdonough at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M offload/test/offloading/pgo1.c
Log Message:
-----------
[PGO][Offload] Fix pgo1.c (#126864)
pgo1.c had outdated test checks
Commit: de968c8e1c711728b62c441fbaa518c958882882
https://github.com/llvm/llvm-project/commit/de968c8e1c711728b62c441fbaa518c958882882
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
Log Message:
-----------
AMDGPU: Use range to implement getSubRegs (#126861)
Fixes #126781
Commit: be9842837486c674c9001732356a43b27d7cdba5
https://github.com/llvm/llvm-project/commit/be9842837486c674c9001732356a43b27d7cdba5
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M llvm/lib/Passes/PassBuilderPipelines.cpp
Log Message:
-----------
[NFC][Pipelines] Extract buildCoroConditionalWrapper (#126860)
Helper for #126168.
`Phase` will be used in followup patches.
Commit: 3ca9238cb0d3cdf1961c81931a624b24c787ed82
https://github.com/llvm/llvm-project/commit/3ca9238cb0d3cdf1961c81931a624b24c787ed82
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format][NFC] Fix test case format
Commit: 7dd82805d54bab37bc0ca4731d7837d4dd5302af
https://github.com/llvm/llvm-project/commit/7dd82805d54bab37bc0ca4731d7837d4dd5302af
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Log Message:
-----------
[SelectionDAGBuilder] Remove NodeMap updates from getValueImpl. NFC (#126849)
Both callers already put the result in NodeMap immediately after the
call.
Commit: 46f1bab7930cb118c61bf5ff221790240ec07512
https://github.com/llvm/llvm-project/commit/46f1bab7930cb118c61bf5ff221790240ec07512
Author: Amit Kumar Pandey <137622562+ampandey-1995 at users.noreply.github.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/ROCm.h
M clang/test/Driver/amdgpu-openmp-sanitize-options.c
M clang/test/Driver/hip-sanitize-options.hip
Log Message:
-----------
Reapply "[Driver][ROCm][OpenMP] Fix default ockl linking for OpenMP."… (#126671)
- This reverts commit
https://github.com/llvm/llvm-project/commit/0c6c4a99936d4d39015c8d2332483f8db78f69cf.
- Add '-mcode-object-version=5' as to explicitly use code object
version 5 to match with 'FAIL' diagnostic.
- Add Requires directive to support lit test run on platforms
registered with x86_64 and amdgpu.
Commit: 0b9b014be7f5130e2ac2809cb1914441b7870a7e
https://github.com/llvm/llvm-project/commit/0b9b014be7f5130e2ac2809cb1914441b7870a7e
Author: Adam Siemieniuk <adam.siemieniuk at intel.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/DLTI/DLTI.h
M mlir/lib/Dialect/DLTI/DLTI.cpp
Log Message:
-----------
[mlir][dlti] Query by strings (#126716)
Adds DLTI utility to query using strings directly as keys.
Commit: 215fa9e175c6ef9e2fa92f77fbd4015cd4c99a67
https://github.com/llvm/llvm-project/commit/215fa9e175c6ef9e2fa92f77fbd4015cd4c99a67
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h
Log Message:
-----------
[NVPTX] Cleanup/Refactoring in NVPTX AsmPrinter and RegisterInfo (NFC) (#126800)
Commit: 0abe058d7f99c9c7bbaf4ee98308c5e78d229897
https://github.com/llvm/llvm-project/commit/0abe058d7f99c9c7bbaf4ee98308c5e78d229897
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M bolt/tools/driver/llvm-bolt.cpp
Log Message:
-----------
[BOLT] Use getMainExecutable() (#126698)
Use LLVM's getMainExecutable() helper instead of rolling our own. This
will result in standard behavior across platforms, such as making sure
that symlinks are always resolved.
Commit: 39f0f0a21b0f638f13c9440e4607151afc8437ac
https://github.com/llvm/llvm-project/commit/39f0f0a21b0f638f13c9440e4607151afc8437ac
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find/find.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find/ranges.find.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.foreach/for_each.pass.cpp
Log Message:
-----------
[libc++] Remove obsolete guards for join_view being experimental (#126697)
These TODOs were forgotten when join_view was made non-experimental. By
removing these checks, we slightly increase the coverage of the test
suite.
Commit: 65075a863bda6e0afd79dd9babc989d465040c65
https://github.com/llvm/llvm-project/commit/65075a863bda6e0afd79dd9babc989d465040c65
Author: jeanPerier <jperier at nvidia.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/test/Fir/convert-to-llvm.fir
M flang/test/Fir/fir-ops.fir
Log Message:
-----------
[flang][FIR] handle argument attributes in fir.call (#126711)
Add pretty printer/parser for fir.call argument/result attributes and
propagate them to llvm.call.
This will allow implementing the TODO about ABI relevant argument
attribute in indirect calls.
Commit: 25c055416643f3291dfaa8136cb3a17b00656779
https://github.com/llvm/llvm-project/commit/25c055416643f3291dfaa8136cb3a17b00656779
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M libclc/CMakeLists.txt
A libclc/clc/include/clc/clc_convert.h
A libclc/clc/include/clc/float/definitions.h
M libclc/generic/include/clc/convert.h
R libclc/generic/include/clc/float/definitions.h
M libclc/generic/lib/gen_convert.py
Log Message:
-----------
[libclc] Move conversion builtins to the CLC library (#124727)
This commit moves the implementations of conversion builtins to the CLC
library. It keeps the dichotomy of regular vs. clspv implementations of
the conversions. However, for the sake of a consistent interface all CLC
conversion routines are built, even the ones that clspv opts out of in
the user-facing OpenCL layer.
It simultaneously updates the python script to use f-strings for
formatting.
Commit: 20506a0a15f9c4a7dc1cd0b4fa2dec8449074ab8
https://github.com/llvm/llvm-project/commit/20506a0a15f9c4a7dc1cd0b4fa2dec8449074ab8
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/test/AST/ByteCode/new-delete.cpp
Log Message:
-----------
[clang][bytecode] Fix operator new source expression (#126870)
... for composite element types. Looks like I forgot this in
e6030d389571b3f1b0f0c5a35b7fa45937ed0f6c
Commit: 8359dbc8c08ca4206534d605dd299713dc323b67
https://github.com/llvm/llvm-project/commit/8359dbc8c08ca4206534d605dd299713dc323b67
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
Log Message:
-----------
[X86] combineEXTRACT_SUBVECTOR - fold extract_subvector(subv_broadcast_load(ptr),0) -> load(ptr) (#126523)
This is typically handled by SimplifyDemandedVectorElts, but this will
fail when there are multiple uses of the subv_broadcast_load node, but
if there's just one use of the load result (and the rest are uses of the
memory chain), we can still replace with a load and update the chain
accordingly.
Noticed on #126517
Commit: c03325cead2244ef0a89bb1cf365bddf16021daf
https://github.com/llvm/llvm-project/commit/c03325cead2244ef0a89bb1cf365bddf16021daf
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M flang/test/Fir/box.fir
M flang/test/Fir/rebox-global.fir
M flang/test/Fir/type-descriptor.fir
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-host.mlir
Log Message:
-----------
[MLIR][LLVMIR] Use TargetFolder when creating globals (#126745)
The LLVM dialect lowers globals using IRBuilder, relying on it creating
constant expressions where possible. As we remove support for more
constant expressions (per
https://discourse.llvm.org/t/rfc-remove-most-constant-expressions/63179),
this can cause issues for cases where the constant expression is no
longer supported, and the operation cannot be constant folded without
DataLayout being available. In particular, I ran into this issue with
flang and the removal of mul constant expressions.
Address this by using TargetFolder when creating globals, which will
perform DL-aware constant folding. I think it would make sense to also
do this in general, but I'm starting with globals where not doing this
can result in translation failures.
Ideally, globals with these problematic expressions would never be
generated in the first place, but there has been little movement on
fixing this (https://github.com/llvm/llvm-project/issues/96047).
Commit: c174cc48401292e2eb9317128f56fd22af2f4848
https://github.com/llvm/llvm-project/commit/c174cc48401292e2eb9317128f56fd22af2f4848
Author: Yeaseen <yeaseen.arafat96 at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/coalescer-subreg.ll
M llvm/test/CodeGen/X86/code_placement_eh.ll
M llvm/test/CodeGen/X86/codegen-prepare-cast.ll
M llvm/test/CodeGen/X86/discontiguous-loops.ll
M llvm/test/CodeGen/X86/early-ifcvt-crash.ll
M llvm/test/CodeGen/X86/fast-isel-stackcheck.ll
M llvm/test/CodeGen/X86/fp-stack-O0-crash.ll
M llvm/test/CodeGen/X86/fp-stack.ll
M llvm/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir
M llvm/test/CodeGen/X86/insert-positions.ll
M llvm/test/CodeGen/X86/legalize-sub-zero-2.ll
M llvm/test/CodeGen/X86/licm-symbol.ll
M llvm/test/CodeGen/X86/liveness-local-regalloc.ll
M llvm/test/CodeGen/X86/lsr-overflow.ll
M llvm/test/CodeGen/XCore/2010-02-25-LSR-Crash.ll
Log Message:
-----------
[llvm] Remove `br i1 undef` in some `llvm/test/CodeGen` tests (#126811)
This PR replaces some instances of `br i1 undef` with function argument
value in several tests under `llvm/test/CodeGen/` directory.
Commit: 73413bd6a30c34d37b94f4cbd604b6b1ba7184e6
https://github.com/llvm/llvm-project/commit/73413bd6a30c34d37b94f4cbd604b6b1ba7184e6
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/CMakeLists.txt
Log Message:
-----------
[mlir] Add missing dependency
After #126745, we should also depend on the Analysis component.
Commit: 37f36cbffb890a0c144211dec0c3589bd17f2a36
https://github.com/llvm/llvm-project/commit/37f36cbffb890a0c144211dec0c3589bd17f2a36
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M lldb/source/Commands/CommandObjectDisassemble.cpp
M lldb/source/Commands/CommandObjectDisassemble.h
M lldb/source/Symbol/SymbolContext.cpp
M lldb/test/Shell/Commands/command-disassemble.s
Log Message:
-----------
[lldb] Support disassembling discontinuous functions (#126505)
The command already supported disassembling multiple ranges, among other
reasons because inline functions can be discontinuous. The main thing
that was missing was being able to retrieve the function ranges from the
top level function object.
The output of the command for the case where the function entry point is
not its lowest address is somewhat confusing (we're showing negative
offsets), but it is correct.
Commit: 32faf438785ec5d7b3d2d605ae30ee6ab337a163
https://github.com/llvm/llvm-project/commit/32faf438785ec5d7b3d2d605ae30ee6ab337a163
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIRType.h
M flang/lib/Lower/OpenMP/PrivateReductionUtils.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/test/Lower/OpenMP/parallel-private-clause-str.f90
Log Message:
-----------
[flang][OpenMP] Handle fixed length `charater`s in delayed privatization (#126704)
We currently handle sequences of fixed-length arrays properly by **not**
emitting length parameters for `embox` ops inside the `omp.private` op.
However, we do not handle the scalar case. This PR extends
`getLengthParameters` defined in `PrivateReductionUtils.cpp` to handle
such cases.
Fixes issue reported in #125732.
Commit: f73ed3d4346c37292fbee99361a904e371d1d9eb
https://github.com/llvm/llvm-project/commit/f73ed3d4346c37292fbee99361a904e371d1d9eb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/CodeGen/X86/avx512fp16-mov.ll
M llvm/test/CodeGen/X86/copy-low-subvec-elt-to-high-subvec-elt.ll
M llvm/test/CodeGen/X86/expand-vp-cast-intrinsics.ll
M llvm/test/CodeGen/X86/matrix-multiply.ll
M llvm/test/CodeGen/X86/pr51615.ll
M llvm/test/CodeGen/X86/vector-half-conversions.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
Log Message:
-----------
[X86] lowerShuffleAsBroadcast - use isShuffleEquivalent to search for a hidden broadcast pattern (#126517)
lowerShuffleAsBroadcast only matches a known-splat shuffle mask, but we
can use the isShuffleEquivalent/IsElementEquivalent helpers to attempt
to find a hidden broadcast-able shuffle pattern.
This requires an extension to IsElementEquivalent to peek through
bitcasts to match against wider shuffles - these typically appear during
shuffle lowering where we've widened a preceding shuffle, often to a
vector concatenation etc.
Amazingly I hit this while yak shaving #126033 .......
Commit: 5fe37ff75ab5cdacd78933726009488068aabca5
https://github.com/llvm/llvm-project/commit/5fe37ff75ab5cdacd78933726009488068aabca5
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h
Log Message:
-----------
Revert "[NVPTX] Cleanup/Refactoring in NVPTX AsmPrinter and RegisterInfo (NFC) (#126800)"
This reverts commit 215fa9e175c6ef9e2fa92f77fbd4015cd4c99a67.
getNameOrAsOperand is only defined under DEBUG
Commit: d51750dba1c8fff8ea774a259f1263093c2ac434
https://github.com/llvm/llvm-project/commit/d51750dba1c8fff8ea774a259f1263093c2ac434
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] port c03325cead2244ef0a89bb1cf365bddf16021daf
Commit: edbc1fb228acd7746d91cd72d476c063704504b8
https://github.com/llvm/llvm-project/commit/edbc1fb228acd7746d91cd72d476c063704504b8
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.def
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/test/Analysis/analyzer-config.c
M clang/test/Analysis/loop-assumptions.c
Log Message:
-----------
[analyzer] Add option assume-at-least-one-iteration (#125494)
This commit adds the new analyzer option
`assume-at-least-one-iteration`, which is `false` by default, but can be
set to `true` to ensure that the analyzer always assumes at least one
iteration in loops.
In some situations this "loop is skipped" execution path is an important
corner case that may evade the notice of the developer and hide
significant bugs -- however, there are also many situations where it's
guaranteed that at least one iteration will happen (e.g. some data
structure is always nonempty), but the analyzer cannot realize this and
will produce false positives when it assumes that the loop is skipped.
This commit refactors some logic around the implementation of the new
feature, but the only functional change is introducing the new analyzer
option. If the new option is left in its default state (false), then the
analysis is functionally equivalent to an analysis done with a version
before this commit.
Commit: bf7af2d12e3bb8c7bc322ed1c5bf4e9904ad409c
https://github.com/llvm/llvm-project/commit/bf7af2d12e3bb8c7bc322ed1c5bf4e9904ad409c
Author: David Green <david.green at arm.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
Log Message:
-----------
[AArch64][DAG] Allow fptos/ui.sat to scalarized. (#126799)
We we previously running into problems with fp128 types and certain
integer sizes.
Fixes an issue reported on #124984
Commit: 79010e2e4d0e27ee87887bfaef2c32e908c92a8e
https://github.com/llvm/llvm-project/commit/79010e2e4d0e27ee87887bfaef2c32e908c92a8e
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/LLVMCommon/VectorPattern.cpp
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
Log Message:
-----------
[mlir] ArithToLLVM: fix memref bitcast lowering (#125148)
`arith.bitcast` is allowed on memrefs and such code can actually be
generated by IREE `ConvertBf16ArithToF32Pass`.
`LLVM::detail::vectorOneToOneRewrite` doesn't properly check its types
and will generate bitcast between structs which is illegal.
With the opaque pointers this is a no-op operation for memref so we can
just add type check in `LLVM::detail::vectorOneToOneRewrite` and add a
separate pattern which removes op if converted types are the same.
Commit: 01afa8fc0b26e6beadbc57a90ded0e1e792d8a83
https://github.com/llvm/llvm-project/commit/01afa8fc0b26e6beadbc57a90ded0e1e792d8a83
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[NFC][LLVM][LangRef] Improve documentation for partial.reduce.add. (#126728)
Commit: 0e779ad4998ef65907502101c5b82ede05ddfa4e
https://github.com/llvm/llvm-project/commit/0e779ad4998ef65907502101c5b82ede05ddfa4e
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/LLVMCommon/VectorPattern.cpp
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
Log Message:
-----------
Revert "[mlir] ArithToLLVM: fix memref bitcast lowering" (#126895)
Reverts llvm/llvm-project#125148
bot failures
Commit: 0fd50ec9a3d6669b8fb835d125a0494ebeb558f0
https://github.com/llvm/llvm-project/commit/0fd50ec9a3d6669b8fb835d125a0494ebeb558f0
Author: Frank Schlimbach <frank.schlimbach at intel.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
A mlir/include/mlir/Dialect/Arith/Transforms/ShardingInterfaceImpl.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td
M mlir/include/mlir/Dialect/Mesh/Interfaces/ShardingInterface.h
M mlir/include/mlir/InitAllDialects.h
M mlir/lib/Dialect/Arith/Transforms/CMakeLists.txt
A mlir/lib/Dialect/Arith/Transforms/ShardingInterfaceImpl.cpp
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Interfaces/ShardingInterface.cpp
M mlir/lib/Dialect/Mesh/Transforms/ShardingPropagation.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
M mlir/lib/Dialect/Tensor/Extensions/MeshShardingExtensions.cpp
A mlir/test/Dialect/Arith/mesh-spmdize.mlir
A mlir/test/Dialect/Arith/sharding-propagation.mlir
M mlir/test/Dialect/Mesh/canonicalization.mlir
M mlir/test/Dialect/Mesh/ops.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
Log Message:
-----------
[MLIR][mesh] Mesh fixes (#124724)
A collection of fixes to the mesh dialect
- allow constants in sharding propagation/spmdization
- fixes to tensor replication (e.g. 0d tensors)
- improved canonicalization
- sharding propagation incorrectly generated too many ShardOps
New operation `mesh.GetShardOp` enables exchanging sharding information
(like on function boundaries)
Commit: 036f543952570831a8c1ab41ec3f29c5eeea3919
https://github.com/llvm/llvm-project/commit/036f543952570831a8c1ab41ec3f29c5eeea3919
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
A llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
A llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
A llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lsfe.ll
A llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a_fp.ll
M llvm/test/CodeGen/AArch64/Atomics/generate-tests.py
Log Message:
-----------
[AArch64] Pre-commit tests for #125686 (NFC) (#126643)
Update the `generate-tests.py` script to create new tests for `atomicrmw
{fadd,fmin,fmax}` and test these with `half`, `float`, `bfloat` and
`double`.
Generate fp auto-tests to check both with and without `+lsfe`, so that when
#125686 is merged, `+lsfe` will use a single atomic floating-point
instruction.
Commit: 563d54569e416228d0229a20a48b50d434f5bf70
https://github.com/llvm/llvm-project/commit/563d54569e416228d0229a20a48b50d434f5bf70
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[NFC][LLVM][LangRef] Fix typos within partial.reduce.add documentation.
Commit: 085bdb1e4c0b584aba84d90bf72997f6476881bc
https://github.com/llvm/llvm-project/commit/085bdb1e4c0b584aba84d90bf72997f6476881bc
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] canonicalizeShuffleWithOp - don't bother trying to move shuffles across binops to fold the load. (#126894)
Its not currently used, but is likely to just introduce additional shuffles, resulting in higher Port5 pressure etc. in future patches.
Commit: 324e27e8bad83ca23a3cd276d7e2e729b1b0b8c7
https://github.com/llvm/llvm-project/commit/324e27e8bad83ca23a3cd276d7e2e729b1b0b8c7
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Analysis/BasicAA/fallback-mayalias.ll
M llvm/test/Transforms/InstCombine/icmp-dom.ll
Log Message:
-----------
[ValueTracking] Infer NonEqual from dominating conditions/assumptions (#117442)
This patch adds context-sensitive analysis support for
`isKnownNonEqual`. It is required for
https://github.com/llvm/llvm-project/issues/117436.
Commit: b101c35bc76b569793028dadd4e7faf08bee6952
https://github.com/llvm/llvm-project/commit/b101c35bc76b569793028dadd4e7faf08bee6952
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M libcxx/include/__config
Log Message:
-----------
[libc++] Remove conditional for attributes that are always available (#126879)
These attributes are available in all supported compilers, so the
`#else` case of the conditional is dead code.
Commit: 7647f478c3244f39e92b99ec07667595f86b84ff
https://github.com/llvm/llvm-project/commit/7647f478c3244f39e92b99ec07667595f86b84ff
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
M llvm/test/CodeGen/X86/vselect-avx.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
Log Message:
-----------
[X86] isShuffleFoldableLoad - only check that the SDValue has one use (#126900)
We don't need the entire load node to have oneuse, just the loaded value - prevents load chains from interfering with shuffle commutation
Commit: 75dd4119b2798a53241089f77922a2e13ead6b94
https://github.com/llvm/llvm-project/commit/75dd4119b2798a53241089f77922a2e13ead6b94
Author: Takuto Ikuta <tikuta at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M libcxxabi/src/cxa_default_handlers.cpp
Log Message:
-----------
[libc++abi] Add a missing include for abort() (#126865)
This is to fix a build error when we use Clang modules in Chromium.
Commit: 7b60e03d739166d5ad63719ebf772272f2d91781
https://github.com/llvm/llvm-project/commit/7b60e03d739166d5ad63719ebf772272f2d91781
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/RegAllocBasic.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AArch64/a55-fuse-address.mir
M llvm/test/CodeGen/AArch64/ampere1-sched-add.mir
M llvm/test/CodeGen/AArch64/cluster-frame-index.mir
M llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir
M llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
M llvm/test/CodeGen/AArch64/force-enable-intervals.mir
M llvm/test/CodeGen/AArch64/machine-scheduler.mir
M llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir
M llvm/test/CodeGen/AArch64/macro-fusion-last.mir
M llvm/test/CodeGen/AArch64/misched-branch-targets.mir
M llvm/test/CodeGen/AArch64/misched-bundle.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir
M llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir
M llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir
M llvm/test/CodeGen/AArch64/misched-move-imm.mir
M llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
M llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
M llvm/test/CodeGen/AArch64/sched-postidxalias.mir
M llvm/test/CodeGen/AArch64/sched-print-cycle.mir
M llvm/test/CodeGen/AArch64/scheduledag-constreg.mir
M llvm/test/CodeGen/AArch64/sve-aliasing.mir
M llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
M llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir
M llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
M llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
M llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
M llvm/test/CodeGen/ARM/misched-branch-targets.mir
M llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir
M llvm/test/CodeGen/RISCV/misched-postra-direction.mir
Log Message:
-----------
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
`RegisterClassInfo` was supposed to be kept alive between pass runs,
which wasn't being done leading to recomputations increasing the compile
time.
Now the Impl class is a member of the legacy and new passes so that it
is not reconstructed on every pass run.
---------
Co-authored-by: Christudasan Devadasan <christudasan.devadasan at amd.com>
Commit: 238563653fbb903e82f2aa1caa807187406250b6
https://github.com/llvm/llvm-project/commit/238563653fbb903e82f2aa1caa807187406250b6
Author: Christian Sigg <csigg at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Fix after https://github.com/llvm/llvm-project/commit/0fd50ec9a3d6669b8fb835d125a0494ebeb558f0
Commit: f3a1d558116904b793ff8ece7dae9605b741b178
https://github.com/llvm/llvm-project/commit/f3a1d558116904b793ff8ece7dae9605b741b178
Author: Christian Sigg <csigg at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Fix after https://github.com/llvm/llvm-project/commit/0fd50ec9a3d6669b8fb835d125a0494ebeb558f0
Second attempt.
Commit: a1826b4d2603a2018ca348d430159ec59e0b72bd
https://github.com/llvm/llvm-project/commit/a1826b4d2603a2018ca348d430159ec59e0b72bd
Author: Matt <MattPD at users.noreply.github.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/test/OpenMP/ordered_codegen.cpp
A openmp/runtime/test/misc_bugs/simd_conservative_ordered.c
Log Message:
-----------
[OpenMP][SIMD][FIX] Use conservative "omp simd ordered" lowering (#126172)
A proposed fix for the issue #95611, [OpenMP][SIMD] ordered has no
effect in a loop SIMD region as of LLVM 18.1.0
Changes:
- Implement new lowering behavior: Conservatively serialize "omp simd"
loops that have `omp simd ordered` directive to prevent incorrect
vectorization (which results in incorrect execution behavior of the
miscompiled program).
Implementation outline:
- We start with the optimistic default initial value of
`LoopStack.setParallel(/Enable=/true);` in
`CodeGenFunction::EmitOMPSimdInit(const OMPLoopDirective &D)`.
- We only disable the loop parallel memory access assumption with `if
(HasOrderedDirective) LoopStack.setParallel(/Enable=/false);` using the
`HasOrderedDirective` (which tests for the presence of an
`OMPOrderedDirective`).
- This results in no longer incorrectly vectorizing the loop when the
`omp simd ordered` directive is present.
Motivation: We'd like to prevent incorrect vectorization of the loops
marked with the `#pragma omp ordered simd` directive which has
previously resulted in miscompiled code.
At the same time, we'd like the usage outside of the `#pragma omp
ordered simd` context to remain unaffected: Note that in the test
"clang/test/OpenMP/ordered_codegen.cpp" we only "lose" the
`!llvm.access.group` metadata in `foo_simd` alone.
This is conservative, in that it's possible some of the loops would be
possible to vectorize, but we prefer to avoid miscompilation of the
loops that are currently illegal to vectorize.
A concrete example follows:
```cpp
// "test.c"
#include <float.h>
#include <math.h>
#include <omp.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
int compare_float(float x1, float x2, float scalar) {
const float diff = fabsf(x1 - x2);
x1 = fabsf(x1);
x2 = fabsf(x2);
const float l = (x2 > x1) ? x2 : x1;
if (diff <= l * scalar * FLT_EPSILON)
return 1;
else
return 0;
}
#define ARRAY_SIZE 256
__attribute__((noinline)) void initialization_loop(
float X[ARRAY_SIZE][ARRAY_SIZE], float Y[ARRAY_SIZE][ARRAY_SIZE]) {
const float max = 1000.0;
srand(time(NULL));
for (int r = 0; r < ARRAY_SIZE; r++) {
for (int c = 0; c < ARRAY_SIZE; c++) {
X[r][c] = ((float)rand() / (float)(RAND_MAX)) * max;
Y[r][c] = X[r][c];
}
}
}
__attribute__((noinline)) void omp_simd_loop(float X[ARRAY_SIZE][ARRAY_SIZE]) {
for (int r = 1; r < ARRAY_SIZE; ++r) {
for (int c = 1; c < ARRAY_SIZE; ++c) {
#pragma omp simd
for (int k = 2; k < ARRAY_SIZE; ++k) {
#pragma omp ordered simd
X[r][k] = X[r][k - 2] + sinf((float)(r / c));
}
}
}
}
__attribute__((noinline)) int comparison_loop(float X[ARRAY_SIZE][ARRAY_SIZE],
float Y[ARRAY_SIZE][ARRAY_SIZE]) {
int totalErrors_simd = 0;
const float scalar = 1.0;
for (int r = 1; r < ARRAY_SIZE; ++r) {
for (int c = 1; c < ARRAY_SIZE; ++c) {
for (int k = 2; k < ARRAY_SIZE; ++k) {
Y[r][k] = Y[r][k - 2] + sinf((float)(r / c));
}
}
// check row for simd update
for (int k = 0; k < ARRAY_SIZE; ++k) {
if (!compare_float(X[r][k], Y[r][k], scalar)) {
++totalErrors_simd;
}
}
}
return totalErrors_simd;
}
int main(void) {
float X[ARRAY_SIZE][ARRAY_SIZE];
float Y[ARRAY_SIZE][ARRAY_SIZE];
initialization_loop(X, Y);
omp_simd_loop(X);
const int totalErrors_simd = comparison_loop(X, Y);
if (totalErrors_simd) {
fprintf(stdout, "totalErrors_simd: %d \n", totalErrors_simd);
fprintf(stdout, "%s : %d - FAIL: error in ordered simd computation.\n",
__FILE__, __LINE__);
} else {
fprintf(stdout, "Success!\n");
}
return totalErrors_simd;
}
```
Before:
```
$ clang -fopenmp-simd -O3 -ffast-math -lm test.c -o test && ./test
totalErrors_simd: 15408
test.c : 76 - FAIL: error in ordered simd computation.
```
clang 19.1.0: https://godbolt.org/z/6EvhxqEhe
After:
```
$ clang -fopenmp-simd -O3 -ffast-math test.c -o test && ./test
Success!
```
Co-authored-by: Matt P. Dziubinski <matt-p.dziubinski at hpe.com>
Commit: acce3b808d69b6a75b0b7c7d5eea5a81e416dc6c
https://github.com/llvm/llvm-project/commit/acce3b808d69b6a75b0b7c7d5eea5a81e416dc6c
Author: Christian Sigg <csigg at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
Log Message:
-----------
[mlir] Mark variable as maybe_unused.
Commit: 3e62321ed9bb4f94c901d9c4286b15e5619206e6
https://github.com/llvm/llvm-project/commit/3e62321ed9bb4f94c901d9c4286b15e5619206e6
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LoopVectorize] Make collectInLoopReductions more efficient (#126769)
We call collectInLoopReductions in multiple places asking
the same question with exactly the same answer. For
example, this was being called from a loop in
calculateRegisterUsage and this patch hoists the call out
to above the loop. In addition I've changed
collectInLoopReductions so that it bails out if we've
already built up a list.
Commit: cbe879d6858fe2962261181818d694b8367fe804
https://github.com/llvm/llvm-project/commit/cbe879d6858fe2962261181818d694b8367fe804
Author: Scott Manley <rscottmanley at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.td
Log Message:
-----------
[Flang] Fix options for FunctionAttr pass (#126819)
For non-basic types GenericOptionParser::findArgStrForValue will return
null, ultimately an llvm_unreachable, when the specific values are not
found. Add the enum, much like the debug-level option in AddDebugInfo to
resolve this problem. Also change tuneCPU to be std::string or it will
also fail.
Commit: 767b15f9d57cf31fd6ba2aed8c17a8c30d5b5e6e
https://github.com/llvm/llvm-project/commit/767b15f9d57cf31fd6ba2aed8c17a8c30d5b5e6e
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
A clang/test/SemaHLSL/use-cxx-alt-operator-names.hlsl
Log Message:
-----------
[HLSL] Change clang Driver Options to not set CXXOperatorNames (#126758)
- Disable `CXXOperatorNames` for HLSL
- Add tests to confirm we can use the alt names as functions
Commit: 108e6bca693e5f44d2d17da5a6e06203a0290de7
https://github.com/llvm/llvm-project/commit/108e6bca693e5f44d2d17da5a6e06203a0290de7
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Improve dump of the ScheduleData, NFC
Commit: f085261b59a782ebd602ae1e590242ab70ddf8a4
https://github.com/llvm/llvm-project/commit/f085261b59a782ebd602ae1e590242ab70ddf8a4
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/include/llvm/IR/IRBuilder.h
Log Message:
-----------
[IRBuilder] Add additional overload with in-place Inserter construction (NFC)
Currently, for IRBuilders that require an explicitly constructed
Folder, we also force Inserter to be constructed and then copied.
Provide a variant where the Inserter uses in-place default
construction, to support cases where it is self-referential.
Commit: 96ce8cadf9181db8b155a4f4374d7fff861303b3
https://github.com/llvm/llvm-project/commit/96ce8cadf9181db8b155a4f4374d7fff861303b3
Author: Jason Eckhardt <jeckhardt at nvidia.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonLoopAlign.cpp
M llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp
M llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.h
Log Message:
-----------
[NFC][Lanai][Hexagon] Define DEBUG_TYPE after including Debug.h. (#125440)
This patch fixes some warnings/errors that occur with certain
compilers-- due to existing code not following the idiom mentioned in
`Debug.h`:
```
// LLVM_DEBUG() requires the DEBUG_TYPE macro to be defined. Set it to "foo"
// specify that your debug code belongs to class "foo". **Be careful that you only
// do this after including Debug.h and not around any #include of headers.**
```
Commit: fc4d87100a01f08dbdf78b68e1a6a5c2584d840d
https://github.com/llvm/llvm-project/commit/fc4d87100a01f08dbdf78b68e1a6a5c2584d840d
Author: Vy Nguyen <vyng at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M lldb/source/Core/CMakeLists.txt
M lldb/source/Core/Telemetry.cpp
M llvm/include/llvm/Config/llvm-config.h.cmake
Log Message:
-----------
Define -DLLVM_BUILD_TELEMETRY to be used in ifdef (#126746)
Background:
Telemetry code isn't always built (controlled by this
LLVM_BUILD_TELEMETRY cmake flag)
This means users of the library may not have the library. So we're
definding the `-DLLVM_BUILD_TELEMETRY` to be used in ifdef.
Commit: e1935a2b1573655dc96fec6bd1158b7eeb881b81
https://github.com/llvm/llvm-project/commit/e1935a2b1573655dc96fec6bd1158b7eeb881b81
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
Revert "[SLP][NFC]Improve dump of the ScheduleData, NFC"
This reverts commit 108e6bca693e5f44d2d17da5a6e06203a0290de7 to fix
error revealed by buildbots https://lab.llvm.org/buildbot/#/builders/159/builds/15888.
Commit: e5268191e6bf79186bad1408312f3520c47c40a6
https://github.com/llvm/llvm-project/commit/e5268191e6bf79186bad1408312f3520c47c40a6
Author: Nico Weber <thakis at chromium.org>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn
Log Message:
-----------
[gn] port fc4d87100a0
Commit: bb3d789dfef4631d06cd31441a8e431702872a03
https://github.com/llvm/llvm-project/commit/bb3d789dfef4631d06cd31441a8e431702872a03
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Improve dump of the ScheduleData, NFC
Commit: 830a2911ee164e32a5459e2991233afb7168c812
https://github.com/llvm/llvm-project/commit/830a2911ee164e32a5459e2991233afb7168c812
Author: Scott Manley <rscottmanley at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M flang/lib/Optimizer/Passes/Pipelines.cpp
Log Message:
-----------
[Flang] fix initializer with empty string to fix aarch64 build (#126918)
After tuneCPU was changed to std::string in
c8376a93bb9853cbcedeb22d80a9b200060eaf85 the flang builds broke, due to
a missing initializer.
If we want to add tuneCPU to the MLIRToLLVMPassPipelineConfig, we might
want to tackle that separately after the build is restored. This should
be no different than the previous behaviour.
Commit: be25d618320d136faffd9dc450b406557e07634e
https://github.com/llvm/llvm-project/commit/be25d618320d136faffd9dc450b406557e07634e
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/lib/Analysis/LiveVariables.cpp
M clang/test/Analysis/live-stmts.cpp
Log Message:
-----------
[clang][analysis] Fix flaky clang/test/Analysis/live-stmts.cpp test (#126913)
Multiple people reported flaky bot failures tied to
`clang/test/Analysis/live-stmts.cpp` I tried reproducing the flaky
behavior on my Linux x86_64 system, but the tests appears to be stable
in my context.
Only by looking at the failures reported, I could formulate a potential
diagnosis.
The output always looked almost the same, except that the Exprs dumped
per Basic block were shuffled compared to my expectation. This suggests
to me some ordering issue.
If you look at the backing storage of
`blocksEndToLiveness[B].liveExprs`,
it uses `llvm::ImmutableSet<const Expr *>`.
That container likely uses the pointer values as keys, thus the runtime
values of the addresses influence the iteration order.
To fix this, before dumping, I sort the expressions by their
"beginLocs". It should be efficient enough for a debug checker, where
there is no performance constraint.
This should hopefully fix the flaky behavior on systems where ASLR works
differently than (my) Linux system.
Hopefully fixes #126619
Hopefully fixes #126804
Commit: 34534442a822738861ead3677ab11cf20ae34dce
https://github.com/llvm/llvm-project/commit/34534442a822738861ead3677ab11cf20ae34dce
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[Docs][LangRef] Fix broken ref to pointer capture. NFC (#126910)
Commit: 257754011c741d96a9adbcd4858706a59bdca085
https://github.com/llvm/llvm-project/commit/257754011c741d96a9adbcd4858706a59bdca085
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/test/Analysis/out-of-bounds-constraint-check.c
M clang/test/Analysis/out-of-bounds.c
Log Message:
-----------
[NFC][analyzer] OOB test consolidation II: constraint checking (#126748)
This commit heavily refactors `out-of-bounds-constraint-check.c`:
1. The complex combinations of several `clang_analyzer_eval` calls were
replaced by `clang_analyzer_value`, which can directly query the range
of a symbol.
2. Testcases were renamed to a (hopefully) more consistent scheme.
3. The use of `size_t` as an argument type was replaced by `unsigned
long long`, which is usually a no-op, but seems to be a better choice if
I look for `64u` in the output of `clang_analyzer_value`.
4. The single "dynamic extent" case was generalized into a full set of
tests that use `malloc`.
5. Half of the testcases (the ones that don't use `malloc`) were changed
to use an `int[5]` array instead of a string literal. After this change
the tests in this file cover every functionality that was tested by the
testcases `test_assume_after_access{,2}` in the file `out-of-bounds.c`
so I was able to delete those two testcases (and therefore consolidate
the validation of these constraints within a single test file).
This is the second commit in a series that reorganizes the tests of
`security.ArrayBound` to system that's easier to understand and
maintain. (Note that this file wasn't significantly modified by the
recent commit 6e17ed9b04e5523cc910bf171c3122dcc64b86db which renamed
`alpha.security.ArrayBoundV2` to `security.ArrayBound`; but I still felt
that this cleanup may be useful.)
Commit: 385af283cd00ef7a0114c343f50e7dca7fec2537
https://github.com/llvm/llvm-project/commit/385af283cd00ef7a0114c343f50e7dca7fec2537
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M bolt/include/bolt/Core/BinarySection.h
M bolt/unittests/Core/BinaryContext.cpp
Log Message:
-----------
[BOLT] Prevent addRelocation from adding pending relocs (#123635)
`addPendingRelocation` is the only way to add a pending
relocation. Can no longer use `addRelocation` for this.
Update the only user (`BinaryContextTester`).
Commit: f13aea1d87c83ee57234af6da07a36fc12fd08a4
https://github.com/llvm/llvm-project/commit/f13aea1d87c83ee57234af6da07a36fc12fd08a4
Author: Sergio Afonso <safonsof at amd.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M flang/include/flang/Semantics/openmp-directive-sets.h
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Semantics/OpenMP/nested-target.f90
M flang/test/Semantics/OpenMP/nested-teams.f90
Log Message:
-----------
[Flang][OpenMP] Update semantics checks for 'teams' nesting (#126922)
This patch introduces a directive set for combined constructs where
`teams` is the last leaf. This is used in a couple places to simplify
checks, which is NFC, but it also replaces two incorrect uses of
`topTeamsSet`.
Before, these checks would incorrectly skip combined constructs where
`teams` was the last leaf construct when checking for allowed nested
constructs inside of a `teams` region. Similarly, it would also
incorrectly perform these checks whenever a compound `teams` construct
where `teams` was the first leaf construct was found.
Commit: fbf46dfe3528f2b6d036671ca2fb5c4b3a0a40b5
https://github.com/llvm/llvm-project/commit/fbf46dfe3528f2b6d036671ca2fb5c4b3a0a40b5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/fp-fold.ll
Log Message:
-----------
[X86] fp-fold.ll - regenerate checks
Commit: a282b6c486c5cc6a4cbdf05195248a4cb3a18e33
https://github.com/llvm/llvm-project/commit/a282b6c486c5cc6a4cbdf05195248a4cb3a18e33
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/lib/CodeGen/Targets/NVPTX.cpp
M clang/test/CodeGenCUDA/launch-bounds.cu
M llvm/docs/NVPTXUsage.rst
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/NVPTX/NVPTXCtorDtorLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/test/Analysis/KernelInfo/launch-bounds/nvptx.ll
M llvm/test/CodeGen/NVPTX/annotations.ll
M llvm/test/CodeGen/NVPTX/lower-ctor-dtor.ll
M llvm/test/CodeGen/NVPTX/maxclusterrank.ll
M llvm/test/CodeGen/NVPTX/upgrade-nvvm-annotations.ll
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/external-func-dialect-attr.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
[NVPTX] Convert scalar function nvvm.annotations to attributes (#125908)
Replace some more nvvm.annotations with function attributes,
auto-upgrading the annotations as needed. These new attributes will be
more idiomatic and compile-time efficient than the annotations.
- !"maxclusterrank" / !"cluster_max_blocks" -> "nvvm.maxclusterrank"
- !"minctasm" -> "nvvm.minctasm"
- !"maxnreg" -> "nvvm.maxnreg"
Commit: 73509781b52486cdff8dc68c4c143ffa2f95356e
https://github.com/llvm/llvm-project/commit/73509781b52486cdff8dc68c4c143ffa2f95356e
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/X86/X86DomainReassignment.cpp
Log Message:
-----------
[X86] Avoid repeated hash lookups (NFC) (#126857)
Commit: 2dd2608105d559cc0d4e6083e13eca91bf6d9fd9
https://github.com/llvm/llvm-project/commit/2dd2608105d559cc0d4e6083e13eca91bf6d9fd9
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M utils/bazel/llvm_configs/llvm-config.h.cmake
Log Message:
-----------
[bazel] port fc4d87100a01f08dbdf78b68e1a6a5c2584d840d
Commit: ff8f6abe20a9dfbb1de8d978f865092413d3416c
https://github.com/llvm/llvm-project/commit/ff8f6abe20a9dfbb1de8d978f865092413d3416c
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
Log Message:
-----------
Reapply "[RISCV] Allow undef prefix for local repeating VLA shuffle lowering (#126097)"
(With a fix to recently added code.)
Implement the first TODO from #125735, and minorly cleanup code using
same style as the recently landed strict prefix case.
Commit: 165a3d6a9b164dc98a70596fa8117acf3de20254
https://github.com/llvm/llvm-project/commit/165a3d6a9b164dc98a70596fa8117acf3de20254
Author: Miguel A. Arroyo <miguel.arroyo at rockstargames.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/cmake/modules/AddClang.cmake
Log Message:
-----------
Revert "[Clang][CMake][MSVC] Install PDBs alongside executables" (#126934)
Reverts llvm/llvm-project#126675
Broke the following:
https://lab.llvm.org/buildbot/#/builders/107/builds/7929
Commit: bee9664970d51df3f4e1d298d1bcb95bba364e17
https://github.com/llvm/llvm-project/commit/bee9664970d51df3f4e1d298d1bcb95bba364e17
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/docs/WritingAnLLVMBackend.rst
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
M llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCTargetDesc.h
M llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
M llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
M llvm/lib/Target/AMDGPU/R600InstrInfo.h
M llvm/lib/Target/AMDGPU/R600Packetizer.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
M llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
A llvm/test/TableGen/get-named-operand-idx.td
M llvm/utils/TableGen/InstrInfoEmitter.cpp
Log Message:
-----------
[TableGen] Emit OpName as an enum class instead of a namespace (#125313)
- Change InstrInfoEmitter to emit OpName as an enum class
instead of an anonymous enum in the OpName namespace.
- This will help clearly distinguish between values that are
OpNames vs just operand indices and should help avoid
bugs due to confusion between the two.
- Rename OpName::OPERAND_LAST to NUM_OPERAND_NAMES.
- Emit declaration of getOperandIdx() along with the OpName
enum so it doesn't have to be repeated in various headers.
- Also updated AMDGPU, RISCV, and WebAssembly backends
to conform to the new definition of OpName (mostly
mechanical changes).
Commit: eff3c343b08cfc46016708b3182ac062d45b3e21
https://github.com/llvm/llvm-project/commit/eff3c343b08cfc46016708b3182ac062d45b3e21
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M lldb/include/lldb/Core/Debugger.h
M lldb/source/API/SBDebugger.cpp
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/DynamicLoader.cpp
M lldb/source/Interpreter/ScriptInterpreter.cpp
M lldb/source/Plugins/DynamicLoader/Darwin-Kernel/DynamicLoaderDarwinKernel.cpp
M lldb/source/Plugins/DynamicLoader/FreeBSD-Kernel/DynamicLoaderFreeBSDKernel.cpp
M lldb/source/Plugins/InstrumentationRuntime/TSan/InstrumentationRuntimeTSan.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTrampolineHandler.cpp
M lldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp
M lldb/source/Plugins/ScriptInterpreter/None/ScriptInterpreterNone.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/ThreadPlanTracer.cpp
Log Message:
-----------
[lldb] Remove Debugger::Get{Output,Error}Stream (NFC) (#126821)
Remove Debugger::GetOutputStream and Debugger::GetErrorStream in
preparation for replacing both with a new variant that needs to be
locked and hence can't be handed out like we do right now.
The patch replaces most uses with GetAsyncOutputStream and
GetAsyncErrorStream respectively. There methods return new StreamSP
objects that automatically get flushed on destruction.
See #126630 for more details.
Commit: 5836d918450b07886556c519a81776db9ac91eea
https://github.com/llvm/llvm-project/commit/5836d918450b07886556c519a81776db9ac91eea
Author: jeanPerier <jperier at nvidia.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
M flang/test/Fir/convert-to-llvm.fir
A flang/test/Fir/target-rewrite-indirect-calls.fir
A flang/test/Integration/abi-indirect-call.f90
Log Message:
-----------
[flang] add ABI argument attributes in indirect calls (#126896)
Last piece that implements the TODO for sret and byval setting on
indirect calls.
This includes a fix to the codegen last patch. I thought types in in
type attributes were automatically converted in dialect conversion
passes, but that is not the case. The sret and byval type needs to be
converted to llvm types in codegen (mlir FuncOp conversion is doing a
similar conversion).
Commit: c77d2027592c93ca1a2009a90b64b5cbdf8cfba3
https://github.com/llvm/llvm-project/commit/c77d2027592c93ca1a2009a90b64b5cbdf8cfba3
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
Log Message:
-----------
Revert "[RISCV] Decompose single source shuffles (without exact VLEN) (#126108)"
This reverts commit 8374d421861cd3d47e21ae7889ba0b4c498e8d85. A miscompile
was reported against the review thread, reverting while we investigate.
Commit: cb3498c6704daefc6e5221beb757126765737aa7
https://github.com/llvm/llvm-project/commit/cb3498c6704daefc6e5221beb757126765737aa7
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.h
A clang/test/OpenMP/spirv_variant_match.cpp
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
M llvm/lib/Frontend/OpenMP/OMPContext.cpp
Log Message:
-----------
[OpenMP][OpenMPIRBuilder] Support SPIR-V device variant matches (#126801)
We should be able to use `spirv64` as a device variant match and it
should be considered a GPU.
Also add the triple to an RTTI check.
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: df092904075e9a9de3c8f9dd4f2da5efc94d4712
https://github.com/llvm/llvm-project/commit/df092904075e9a9de3c8f9dd4f2da5efc94d4712
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/include/llvm/Analysis/SparsePropagation.h
Log Message:
-----------
[Analysis] Avoid repeated hash lookups (NFC) (#126851)
Commit: 71cceb1439c119385ca65c8a14af8584414831a2
https://github.com/llvm/llvm-project/commit/71cceb1439c119385ca65c8a14af8584414831a2
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachinePipeliner.h
Log Message:
-----------
[CodeGen] Avoid repeated hash lookups (NFC) (#126852)
Commit: 2e8f89f048a46afc1e9d4db98ae2932925f6499a
https://github.com/llvm/llvm-project/commit/2e8f89f048a46afc1e9d4db98ae2932925f6499a
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Object/GOFFObjectFile.cpp
Log Message:
-----------
[Object] Avoid repeated map lookups (NFC) (#126853)
Commit: c15806aa5a6d47d1920c6cab5bdcad2f9f5482c1
https://github.com/llvm/llvm-project/commit/c15806aa5a6d47d1920c6cab5bdcad2f9f5482c1
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
Log Message:
-----------
[SPIRV] Avoid repeated hash lookups (NFC) (#126854)
Commit: 99816a5af4ee4d0b1559a5b109b37ddc55ed618f
https://github.com/llvm/llvm-project/commit/99816a5af4ee4d0b1559a5b109b37ddc55ed618f
Author: Evgenii Kudriashov <evgenii.kudriashov at intel.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/Xtensa/Disassembler/CMakeLists.txt
Log Message:
-----------
[Xtensa] Add XtensaDesc dependency to LLVMXtensaDisassembler (#126904)
There is an undefined reference to checkRegister in shared lib builds
Suspecting #124656
Commit: e9e717f4053ee293d42ecaefaa04e473b0e1b469
https://github.com/llvm/llvm-project/commit/e9e717f4053ee293d42ecaefaa04e473b0e1b469
Author: Kazu Hirata <kazu at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h
Log Message:
-----------
[Utils] Avoid repeated hash lookups (NFC) (#126856)
Commit: a3e2075e5008cefc2e896f1558b46f0882321ff5
https://github.com/llvm/llvm-project/commit/a3e2075e5008cefc2e896f1558b46f0882321ff5
Author: Nick Desaulniers <nick.desaulniers at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M libc/src/__support/CPP/bit.h
M libc/test/src/__support/CPP/bit_test.cpp
Log Message:
-----------
[libc][bit_test] fix -Wimplicit-int-conversion (#126317)
Fixes:
llvm-project/libc/src/__support/CPP/bit.h:235:28: error: implicit
conversion loses integer precision: 'int' to
'cpp::enable_if_t<cpp::is_unsigned_v<unsigned short>, unsigned short>'
(aka
'unsigned short') [-Werror,-Wimplicit-int-conversion]
235 | return (value << rotate) | (value >> (N - rotate));
| ~~~~~~ ~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
llvm-project/libc/src/__support/CPP/bit.h:247:28: error: implicit
conversion loses integer precision: 'int' to
'cpp::enable_if_t<cpp::is_unsigned_v<unsigned short>, unsigned short>'
(aka
'unsigned short') [-Werror,-Wimplicit-int-conversion]
247 | return (value >> rotate) | (value << (N - rotate));
| ~~~~~~ ~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
llvm-project/libc/test/src/__support/CPP/bit_test.cpp:45:36: error:
implicit conversion loses integer precision: 'int' to 'unsigned char'
[-Werror,-Wimplicit-int-conversion]
45 | EXPECT_FALSE(has_single_bit<T>(two_bits_value));
| ~~~~~~~~~~~~~~ ^~~~~~~~~~~~~~
Via the libc-cpp-utils-tests ninja target.
Commit: b04a980b5597c61a8df2b489c4894bc0240b8e13
https://github.com/llvm/llvm-project/commit/b04a980b5597c61a8df2b489c4894bc0240b8e13
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/2011-10-27-tstore.ll
Log Message:
-----------
[X86] 2011-10-27-tstore.ll - regenerate checks
Commit: e167c31dc973b0b2c3af96f5e7e28d45736a6c6b
https://github.com/llvm/llvm-project/commit/e167c31dc973b0b2c3af96f5e7e28d45736a6c6b
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
Log Message:
-----------
Reland [mlir] ArithToLLVM: fix memref bitcast lowering (#125148) (#126939)
Reland https://github.com/llvm/llvm-project/pull/125148
Limiting vector pattern caused issues with `select` of complex lowering,
which wasn't caught as it was missing lit tests. Keep the pattern as is
for now and instead set a higher benefit to `IdentityBitcastLowering` so
it will always run before the vector pattern.
Commit: f8c7457c79eece1bd1b7f15e7679517c7c63ad89
https://github.com/llvm/llvm-project/commit/f8c7457c79eece1bd1b7f15e7679517c7c63ad89
Author: schittir <sindhu.chittireddy at intel.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/lib/Format/UnwrappedLineFormatter.cpp
Log Message:
-----------
[NFC] Avoid potential null dereference. (#126872)
Add a null check.
Commit: 3ec9f7494b31f2fe51d5ed0e07adcf4b7199def6
https://github.com/llvm/llvm-project/commit/3ec9f7494b31f2fe51d5ed0e07adcf4b7199def6
Author: Harald van Dijk <harald.vandijk at codeplay.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
M llvm/include/llvm/IR/DIBuilder.h
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
M llvm/unittests/IR/IRBuilderTest.cpp
M llvm/unittests/Transforms/Utils/CloningTest.cpp
Log Message:
-----------
[DebugInfo] Update DIBuilder insertion to take InsertPosition (#126059)
After #124287 updated several functions to return iterators rather than
Instruction *, it was no longer straightforward to pass their result to
DIBuilder. This commit updates DIBuilder methods to accept an
InsertPosition instead, so that they can be called with an iterator
(preferred), or with a deprecation warning an Instruction *, or a
BasicBlock *. This commit also updates the existing calls to the
DIBuilder methods to pass in iterators.
Commit: 23209eb1d9df57ca3419f5abc6b2edcdc0d1dead
https://github.com/llvm/llvm-project/commit/23209eb1d9df57ca3419f5abc6b2edcdc0d1dead
Author: Harald van Dijk <harald.vandijk at codeplay.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
M llvm/include/llvm/IR/DIBuilder.h
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
M llvm/unittests/IR/IRBuilderTest.cpp
M llvm/unittests/Transforms/Utils/CloningTest.cpp
Log Message:
-----------
Revert "[DebugInfo] Update DIBuilder insertion to take InsertPosition (#126059)"
This reverts commit 3ec9f7494b31f2fe51d5ed0e07adcf4b7199def6.
Commit: a684e0ea57ebb93c81506c066afb25cb496dcc11
https://github.com/llvm/llvm-project/commit/a684e0ea57ebb93c81506c066afb25cb496dcc11
Author: Tom Stellard <tstellar at redhat.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M .github/workflows/release-binaries-all.yml
Log Message:
-----------
workflows/release-binaries-all: Add missing secret input (#126921)
Since d194c6b9a7fdda7a61abcd6bfe39ab465bf0cc87 this workflow was missing
the secret input which was causing it to fail.
Commit: c6654806949f0498fdd2d009b66e62041c21de36
https://github.com/llvm/llvm-project/commit/c6654806949f0498fdd2d009b66e62041c21de36
Author: Michał Górny <mgorny at gentoo.org>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M flang/runtime/CMakeLists.txt
Log Message:
-----------
[flang] [runtime] Explicitly disable EH & RTTI (#126920)
Explicitly disable EH & RTTI when building Flang runtime library. This
fixes the runtime built when Flang is built standalone against system
LLVM that was compiled with EH & RTTI enabled.
I think this change may be sufficient to lift the top-level
`LLVM_ENABLE_EH` restriction from Flang. However, I'd prefer if somebody
more knowledgeable decided on that.
Commit: 16a5f7eb73f225544d29e613c84011f1e1ec53a4
https://github.com/llvm/llvm-project/commit/16a5f7eb73f225544d29e613c84011f1e1ec53a4
Author: Michael Jones <michaelrj at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M libc/src/time/time_utils.h
Log Message:
-----------
[libc] Fix implict cast to time_t warning (#126947)
On some systems time_t is 32 bit, causing build errors (with -Werror)
in get_epoch which attempts to implicitly convert an int64_t to a
time_t.
Fixes:
error: implicit conversion loses integer precision: 'int64_t' (aka 'long
long') to 'time_t' (aka 'int') [-Werror,-Wshorten-64-to-32]
332 | return mktime_internal(timeptr);
| ~~~~~~ ^~~~~~~~~~~~~~~~~~~~~~~~
Commit: d200caa5216e8e65fe16455e9858f45926fdd79c
https://github.com/llvm/llvm-project/commit/d200caa5216e8e65fe16455e9858f45926fdd79c
Author: Pavel Labath <pavel at labath.sk>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel
Log Message:
-----------
Revert "[bazel] Temporarily disable a broken LookupAddressRangeWithSt… (#126944)
…mtSequenceOffset debug info test"
This reverts commit 247430e9c41c61b66e2ee95c29a05de3e24c19b9.
The breakage has been fixed by 343bbda140d5a15cd7d7fbfc6041a7506da5cdae.
Commit: 67cde37f3c89c22a51d1c20f75965c64c79b1bce
https://github.com/llvm/llvm-project/commit/67cde37f3c89c22a51d1c20f75965c64c79b1bce
Author: Max191 <44243577+Max191 at users.noreply.github.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/DataLayoutPropagation.cpp
M mlir/test/Dialect/Linalg/data-layout-propagation.mlir
Log Message:
-----------
[mlir] Match before rewrite in BubbleUpPackOpThroughGenericOp (#126946)
The BubbleUpPackOpThroughGenericOp pattern had some unsafe rewrites
happening before matching was fully complete, which causes the pattern
rewriter to fail to converge. This PR fixes the bug by moving all
matching logic to before the rewrite logic.
Signed-off-by: Max Dawkins <max.dawkins at gmail.com>
Commit: a6a4252a15669a2d89ad9134e42b87fb0f56c103
https://github.com/llvm/llvm-project/commit/a6a4252a15669a2d89ad9134e42b87fb0f56c103
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll
M llvm/test/CodeGen/X86/vec-strict-fptoint-256.ll
M llvm/test/CodeGen/X86/vec-strict-fptoint-512.ll
Log Message:
-----------
[X86] vec-strict-fptoint - regenerate VPTERNLOG comments
Commit: 689f79d0f86a6965c0a9c4bc73bc0417c7972b7f
https://github.com/llvm/llvm-project/commit/689f79d0f86a6965c0a9c4bc73bc0417c7972b7f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll
Log Message:
-----------
[X86] vec-strict-cmp-512-skx.ll - regenerate checks
Appears to have been manually edited at some point
Commit: f719d8ac1ccd08a9e8def796ecb9b1cd517c86af
https://github.com/llvm/llvm-project/commit/f719d8ac1ccd08a9e8def796ecb9b1cd517c86af
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/test/CodeGen/X86/vec-strict-cmp-128-fp16.ll
Log Message:
-----------
[X86] vec-strict-cmp-128-fp16.ll - regenerate VMOVSH comments
Commit: 1f51038036b4bc216eddcc620dcb9eca5df2bfef
https://github.com/llvm/llvm-project/commit/1f51038036b4bc216eddcc620dcb9eca5df2bfef
Author: Krishna Pandey <47917477+krishna2803 at users.noreply.github.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/headers/math/stdfix.rst
M libc/include/stdfix.yaml
M libc/src/__support/fixed_point/CMakeLists.txt
M libc/src/__support/fixed_point/fx_bits.h
M libc/src/__support/fixed_point/fx_rep.h
M libc/src/stdfix/CMakeLists.txt
A libc/src/stdfix/countlshk.cpp
A libc/src/stdfix/countlshk.h
A libc/src/stdfix/countlshr.cpp
A libc/src/stdfix/countlshr.h
A libc/src/stdfix/countlsk.cpp
A libc/src/stdfix/countlsk.h
A libc/src/stdfix/countlslk.cpp
A libc/src/stdfix/countlslk.h
A libc/src/stdfix/countlslr.cpp
A libc/src/stdfix/countlslr.h
A libc/src/stdfix/countlsr.cpp
A libc/src/stdfix/countlsr.h
A libc/src/stdfix/countlsuhk.cpp
A libc/src/stdfix/countlsuhk.h
A libc/src/stdfix/countlsuhr.cpp
A libc/src/stdfix/countlsuhr.h
A libc/src/stdfix/countlsuk.cpp
A libc/src/stdfix/countlsuk.h
A libc/src/stdfix/countlsulk.cpp
A libc/src/stdfix/countlsulk.h
A libc/src/stdfix/countlsulr.cpp
A libc/src/stdfix/countlsulr.h
A libc/src/stdfix/countlsur.cpp
A libc/src/stdfix/countlsur.h
M libc/test/src/stdfix/CMakeLists.txt
A libc/test/src/stdfix/CountlsTest.h
A libc/test/src/stdfix/countlshk_test.cpp
A libc/test/src/stdfix/countlshr_test.cpp
A libc/test/src/stdfix/countlsk_test.cpp
A libc/test/src/stdfix/countlslk_test.cpp
A libc/test/src/stdfix/countlslr_test.cpp
A libc/test/src/stdfix/countlsr_test.cpp
A libc/test/src/stdfix/countlsuhk_test.cpp
A libc/test/src/stdfix/countlsuhr_test.cpp
A libc/test/src/stdfix/countlsuk_test.cpp
A libc/test/src/stdfix/countlsulk_test.cpp
A libc/test/src/stdfix/countlsulr_test.cpp
A libc/test/src/stdfix/countlsur_test.cpp
Log Message:
-----------
[libc][stdfix] Implement `countlsfx` functions in libc. (#126597)
fixes #113357
---------
Signed-off-by: krishna2803 <kpandey81930 at gmail.com>
Commit: 562c0c611a3bee6b7766043bfdeb5c6f47d7d2fd
https://github.com/llvm/llvm-project/commit/562c0c611a3bee6b7766043bfdeb5c6f47d7d2fd
Author: Chris B <chris.bieneman at me.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/docs/HLSL/FunctionCalls.rst
Log Message:
-----------
[HLSL][Docs] Update function calls docs (#106860)
Update the function calls documentation to match the newly landed
implementation.
Commit: b0d782080529cf5d422847e1f91f29bd7c62f691
https://github.com/llvm/llvm-project/commit/b0d782080529cf5d422847e1f91f29bd7c62f691
Author: Petr Hosek <phosek at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M libc/include/__llvm-libc-common.h
M libc/include/llvm-libc-macros/features-macros.h
Log Message:
-----------
[libc] Move __LLVM_LIBC__ define to __llvm-libc-common.h (#126877)
Relying on features.h is problematic since codebases are free to have
such a header on their search path, which breaks compilation. libc
should instead provide a more standard way of getting __LLVM_LIBC__.
Since __llvm-libc-common.h is included from all libc headers, defining
__LLVM_LIBC__ there ensures that this define is available whenever any
of the standard header is included.
Commit: 6d7a84d72bf7f7be2a401e80a5339e1ae8f7c0f5
https://github.com/llvm/llvm-project/commit/6d7a84d72bf7f7be2a401e80a5339e1ae8f7c0f5
Author: vporpo <vporpodas at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Scheduler.cpp
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
M llvm/test/Transforms/SandboxVectorizer/bottomup_seed_slice_pow2.ll
M llvm/test/Transforms/SandboxVectorizer/repeated_instrs.ll
M llvm/test/Transforms/SandboxVectorizer/scheduler.ll
Log Message:
-----------
[SandboxVec][Scheduler] Fix top of schedule (#126820)
This patch fixes the way the top-of-schedule variable gets set and
updated. Before this patch it used to get updated whenever we scheduled
a bundle, which is wrong, as the top-of-schedule needs to be maintained
across scheduling attempts.
It should get reset only when we clear the schedule or when we destroy
the current schedule and re-schedule.
Commit: 53c618c07154f8a99762fb5222aa9c05f6c434f7
https://github.com/llvm/llvm-project/commit/53c618c07154f8a99762fb5222aa9c05f6c434f7
Author: Peter Rong <peterrong96 at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/include/clang/AST/Mangle.h
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/lib/CodeGen/CGObjCRuntime.h
M clang/lib/CodeGen/CodeGenFunction.h
Log Message:
-----------
[clang] run clang-format on some CGObjC files (#126644)
These files are relatively old and don't confront our formatting rules.
It's hard to change them without massive clang-format changes.
---------
Signed-off-by: Peter Rong <PeterRong at meta.com>
Commit: 9478822f4f63aa2e5f7bc120406688298911fa24
https://github.com/llvm/llvm-project/commit/9478822f4f63aa2e5f7bc120406688298911fa24
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
Log Message:
-----------
[RISCV] Decompose single source shuffles (without exact VLEN) (#126951)
(This is a re-apply for what was 8374d42. The bug there was fairly
major - despite the comments and review description, the code was
using each register in the source register group, not only the first
register. This was completely wrong.)
This is a continuation of the work started in
https://github.com/llvm/llvm-project/pull/125735 to lower selected VLA
shuffles in linear m1 components instead of generating O(LMUL^2) or
O(LMUL*Log2(LMUL) high LMUL shuffles.
This pattern focuses on shuffles where all the elements being used
across the entire destination register group come from a single register
in the source register group. Such cases come up fairly frequently via
e.g. spread(N), and repeat(N) idioms.
One subtlety to this patch is the handling of the index vector for
vrgatherei16.vv. Because the index and source registers can have
different EEW, the index vector for the Nth chunk of the destination is
not guaranteed to be register aligned. In fact, it is common for e.g. an
EEW=64 shuffle to have EEW=16 indices which are four chunks per source
register. Given this, we have to pay a cost for extracting these chunks
into the low position before performing each shuffle.
I'd initially expressed this as a naive extract sub-vector for each data
parallel piece. However, at high LMUL, this quickly caused register
pressure problems since we could at worst need 4x the temporary
registers for the index. Instead, this patch uses a repeating slidedown
chained from previous iterations. This increases critical path by at
worst 3 slides (SEW=64 is the worst case), but reduces register pressure
to at worst 2x - and only if the original index vector is reused
elsewhere. I view this as arguably a bit of a workaround (since our
scheduling should have done better with the plain extract variant), but
a probably necessary one.
Commit: 7a7f9190d03e12dc5b57d3eb33a84d078de43104
https://github.com/llvm/llvm-project/commit/7a7f9190d03e12dc5b57d3eb33a84d078de43104
Author: vporpo <vporpodas at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/InstrMaps.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/InstrMapsTest.cpp
Log Message:
-----------
[SandboxVec][Legality] Fix mask on diamond reuse with shuffle (#126963)
This patch fixes a bug in the creation of shuffle masks when vectorizing
vectors in case of a diamond reuse with shuffle. The mask needs to
enumerate all elements of a vector, not treat the original vector value
as a single element. That is: if vectorizing two <2 x float> vectors
into a <4 x float> the mask needs to have 4 indices, not just 2.
Commit: 859c871184bdfdebb47b5c7ec5e59348e0534e0b
https://github.com/llvm/llvm-project/commit/859c871184bdfdebb47b5c7ec5e59348e0534e0b
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll
M llvm/test/CodeGen/RISCV/GlobalISel/combine-neg-abs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll
M llvm/test/CodeGen/RISCV/GlobalISel/stacksave-stackrestore.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abds.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
M llvm/test/CodeGen/RISCV/abdu.ll
M llvm/test/CodeGen/RISCV/add-before-shl.ll
M llvm/test/CodeGen/RISCV/add-imm.ll
M llvm/test/CodeGen/RISCV/alloca.ll
M llvm/test/CodeGen/RISCV/alu64.ll
M llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
M llvm/test/CodeGen/RISCV/atomic-rmw.ll
M llvm/test/CodeGen/RISCV/atomic-signext.ll
M llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/RISCV/bf16-promote.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/bfloat-mem.ll
M llvm/test/CodeGen/RISCV/bfloat.ll
M llvm/test/CodeGen/RISCV/bittest.ll
M llvm/test/CodeGen/RISCV/branch-on-zero.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/calling-conv-half.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32e.ll
M llvm/test/CodeGen/RISCV/calls.ll
M llvm/test/CodeGen/RISCV/codemodel-lowering.ll
M llvm/test/CodeGen/RISCV/condbinops.ll
M llvm/test/CodeGen/RISCV/condops.ll
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/double-calling-conv.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/double-imm.ll
M llvm/test/CodeGen/RISCV/double-mem.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
M llvm/test/CodeGen/RISCV/fastcc-bf16.ll
M llvm/test/CodeGen/RISCV/fastcc-float.ll
M llvm/test/CodeGen/RISCV/fastcc-half.ll
M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/float-select-fcmp.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
M llvm/test/CodeGen/RISCV/forced-atomics.ll
M llvm/test/CodeGen/RISCV/fp-fcanonicalize.ll
M llvm/test/CodeGen/RISCV/fp128.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/get-setcc-result-type.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-mem.ll
M llvm/test/CodeGen/RISCV/half-select-fcmp.ll
M llvm/test/CodeGen/RISCV/iabs.ll
M llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
M llvm/test/CodeGen/RISCV/inline-asm-d-modifier-N.ll
M llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
M llvm/test/CodeGen/RISCV/inline-asm-f-modifier-N.ll
M llvm/test/CodeGen/RISCV/inline-asm-zfinx-constraint-r.ll
M llvm/test/CodeGen/RISCV/inline-asm-zhinx-constraint-r.ll
M llvm/test/CodeGen/RISCV/inline-asm.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
M llvm/test/CodeGen/RISCV/legalize-fneg.ll
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
M llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll
M llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
M llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
M llvm/test/CodeGen/RISCV/mem.ll
M llvm/test/CodeGen/RISCV/mem64.ll
M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
M llvm/test/CodeGen/RISCV/memcmp.ll
M llvm/test/CodeGen/RISCV/memmove.ll
M llvm/test/CodeGen/RISCV/memset-pattern.ll
M llvm/test/CodeGen/RISCV/mul.ll
M llvm/test/CodeGen/RISCV/neg-abs.ll
M llvm/test/CodeGen/RISCV/orc-b-patterns.ll
M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
M llvm/test/CodeGen/RISCV/pr51206.ll
M llvm/test/CodeGen/RISCV/pr58511.ll
M llvm/test/CodeGen/RISCV/pr63816.ll
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
M llvm/test/CodeGen/RISCV/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/rv32-inline-asm-pairs.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv32zbs.ll
M llvm/test/CodeGen/RISCV/rv64-double-convert.ll
M llvm/test/CodeGen/RISCV/rv64-half-convert.ll
M llvm/test/CodeGen/RISCV/rv64-inline-asm-pairs.ll
M llvm/test/CodeGen/RISCV/rv64-trampoline.ll
M llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
M llvm/test/CodeGen/RISCV/rv64zbkb.ll
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll
M llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll
M llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
M llvm/test/CodeGen/RISCV/rvv/copyprop.mir
M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/expandload.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpowi.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-addsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store-merge-crash.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll
M llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/localvar.ll
M llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll
M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
M llvm/test/CodeGen/RISCV/rvv/pr125306.ll
M llvm/test/CodeGen/RISCV/rvv/pr63596.ll
M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/shrinkwrap.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.s.x.ll
M llvm/test/CodeGen/RISCV/rvv/vmv0-elimination.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-mask-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub-mask-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/wrong-chain-fixed-load.ll
M llvm/test/CodeGen/RISCV/scmp.ll
M llvm/test/CodeGen/RISCV/select-and.ll
M llvm/test/CodeGen/RISCV/select-bare.ll
M llvm/test/CodeGen/RISCV/select-cc.ll
M llvm/test/CodeGen/RISCV/select-constant-xor.ll
M llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
M llvm/test/CodeGen/RISCV/select-or.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/shift-amount-mod.ll
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/shl-cttz.ll
M llvm/test/CodeGen/RISCV/split-offsets.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/stack-slot-size.ll
M llvm/test/CodeGen/RISCV/stack-store-check.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/RISCV/ucmp.ll
M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
M llvm/test/CodeGen/RISCV/xtheadmempair.ll
M llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
M llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
M llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
Log Message:
-----------
[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)
This change introduces a default schedule model for the RISCV target
which leaves everything unchanged except the MicroOpBufferSize. The
default value of this flag in NoSched is 0. Both configurations
represent in order cores (i.e. no reorder window), the difference
between them comes down to whether heuristics other than latency are
allowed to apply. (Implementation details below)
I left the processor models which explicitly set MicroOpBufferSize=0
unchanged in this patch, but strongly suspect we should change those
too. Honestly, I think the LLVM wide default for this flag should be
changed, but don't have the energy to manage the updates for all
targets.
Implementation wise, the effect of this change is that schedule units
which are ready to run *except that* one of their predecessors may not
have completed yet are added to the Available list, not the Pending one.
The result of this is that it becomes possible to chose to schedule a
node before it's ready cycle if the heuristics prefer. This is
essentially chosing to insert a resource stall instead of e.g.
increasing register pressure.
Note that I was initially concerned there might be a correctness aspect
(as in some kind of exposed pipeline design), but the generic scheduler
doesn't seem to know how to insert noop instructions. Without that, a
program wouldn't be guaranteed to schedule on an exposed pipeline
depending on the program and schedule model in question.
The effect of this is that we sometimes prefer register pressure in
codegen results. This is mostly churn (or small wins) on scalar because
we have many more registers, but is of major importance on vector -
particularly high LMUL - because we effectively have many fewer
registers and the relative cost of spilling is much higher. This is a
significant improvement on high LMUL code quality for default rva23u
configurations - or any non -mcpu vector configuration for that matter.
Fixes #107532
Commit: e75e61728e201f1941c794a12ea22789b6f24c75
https://github.com/llvm/llvm-project/commit/e75e61728e201f1941c794a12ea22789b6f24c75
Author: Vasileios Porpodas <vporpodas at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
Log Message:
-----------
[SandboxVec] Fix warnings introduced by 7a7f9190d03e
Commit: 82605285b8c647f4248bb22f2c9d19945cfcba8c
https://github.com/llvm/llvm-project/commit/82605285b8c647f4248bb22f2c9d19945cfcba8c
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
A llvm/test/Analysis/LoopAccessAnalysis/retry-runtime-checks-after-dependence-analysis.ll
Log Message:
-----------
[LAA] Also clear CheckingGroups in RuntimePointerChecking::reset.
This fixes a crash when trying to print access-info in the newly added
test cases.
Commit: e9e6ba6a5e2a4ca7386861136196903febb9968b
https://github.com/llvm/llvm-project/commit/e9e6ba6a5e2a4ca7386861136196903febb9968b
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-cvt.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt.ll
Log Message:
-----------
[msan] Handle single-parameter Arm NEON vector convert intrinsics (#126136)
This handles the following llvm.aarch64.neon intrinsics, which were suboptimally handled by visitInstruction:
- fcvtas, fcvtau
- fcvtms, fcvtmu
- fcvtns, fcvtnu
- fcvtps, fcvtpu
- fcvtzs, fcvtzu
The old instrumentation checked that the shadow of every element of the input vector was fully initialized, and aborted otherwise. The new instrumentation propagates the shadow: for each element of the output, the shadow is initialized iff the corresponding element of the input is *fully* initialized (since these are floating-point to integer conversions).
Updates the tests from https://github.com/llvm/llvm-project/pull/126095
Commit: 0d95631a3adbc4343e6bfbcecc53ac8f1f0739d1
https://github.com/llvm/llvm-project/commit/0d95631a3adbc4343e6bfbcecc53ac8f1f0739d1
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/scmp.ll
M llvm/test/Instrumentation/MemorySanitizer/ucmp.ll
Log Message:
-----------
[msan] Handle llvm.[us]cmp (starship operator) (#125804)
Apply handleShadowOr to llvm.[us]cmp. Previously, llvm.[su]cmp was correctly handled heuristically when each parameter type is the same as the return type (e.g., `call i8 @llvm.ucmp.i8.i8(i8 %x, i8 %y)`) but handled incorrectly by visitInstruction when the return type is different e.g., (`call i8 @llvm.ucmp.i8.i62(i62 %x, i62 %y)`, `call <4 x i8> @llvm.ucmp.v4i8.v4i32(<4 x i32> %x, <4 x i32> %y)`).
Updates the tests from https://github.com/llvm/llvm-project/pull/125790
Commit: f2650c54c9a6caf021415ed57a0a430fbb032094
https://github.com/llvm/llvm-project/commit/f2650c54c9a6caf021415ed57a0a430fbb032094
Author: S. Bharadwaj Yadavalli <Bharadwaj.Yadavalli at microsoft.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
R clang/test/CodeGenHLSL/disable_opt.hlsl
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.h
A llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-cs.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-lib.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/lib-entry-attr-error.ll
M llvm/test/CodeGen/DirectX/llc-pipeline.ll
Log Message:
-----------
[DirectX] Set Shader Flag DisableOptimizations (#126813)
- Set the shader flag `DisableOptimizations` based on `optnone`
attribute of shader entry functions.
- Add DXIL Metadata Analysis pass as pre-requisite for Shader Flags pass
to obtain entry function information collected therein.
- Named module metadata `dx.disable_optimizations` is intended to
indicate disabling optimizations (`-O0`) via commandline flag. However,
its intent is fulfilled by `optnone` attribute of shader entry functions as
implemented in a recent change, and thus not needed. Delete
generation of named metadata and corresponding test file
`disable_opt.ll`.
- Add tests to verify correctness of setting shader flag.
Closes #112263
Commit: cbb4e99f3613549c2168f52d6f348e3a7ee3cf55
https://github.com/llvm/llvm-project/commit/cbb4e99f3613549c2168f52d6f348e3a7ee3cf55
Author: Jason Molenda <jmolenda at apple.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M lldb/source/Target/ThreadPlanStepOut.cpp
A lldb/test/API/functionalities/thread/finish-from-empty-func/Makefile
A lldb/test/API/functionalities/thread/finish-from-empty-func/TestEmptyFuncThreadStepOut.py
A lldb/test/API/functionalities/thread/finish-from-empty-func/main.c
Log Message:
-----------
[lldb] Update ThreadPlanStepOut to handle new breakpoint behavior (#126838)
I will be changing breakpoint hitting behavior soon, where currently
lldb reports a breakpoint as being hit when a thread is *at* a
BreakpointSite, but possibly has not executed the breakpoint instruction
and trapped yet, to having lldb only report a breakpoint hit when the
breakpoint instruction has actually been executed.
One corner case bug with this change is that when you are stopped at a
breakpoint (that has been hit) on the last instruction of a function,
and you do `finish`, a ThreadPlanStepOut is pushed to the thread's plan
stack to put a breakpoint on the return address and resume execution.
And when the thread is asked to resume, it sees that it is at a
BreakpointSite that has been hit, and pushes a
ThreadPlanStepOverBreakpoint on the thread. The StepOverBreakpoint
plan sees that the thread's state is eStateRunning (not eStateStepping),
so it marks itself as "auto continue" -- so once the breakpoint has
been stepped over, we will execution on the thread.
With current lldb stepping behavior ("a thread *at* a BreakpointSite is
said to have stopped with a breakpoint-hit stop reason, even if the
breakpoint hasn't been executed yet"),
`ThreadPlanStepOverBreakpoint::DoPlanExplainsStop` has a special bit of
code which detects when the thread stops with a eStopReasonBreakpoint.
It first checks if the pc is the same as when we started -- did our
"step instruction" not actually step? -- says the stop reason is
explained. Otherwise it sets auto-continue to false (because we've hit
an *unexpected* breakpoint, and we have advanced past our original pc,
and returns false - the stop reason is not explained.
So we do the "finish", lldb instruction steps, we stop *at* the
return-address breakpoint and lldb sets the thread's stop reason to
breakpoint-hit. ThreadPlanStepOverBreakpoint sees an
eStopReasonBreakpoint, sets its auto-continue to false, and says we
stopped for osme reason other than this plan. (and it will also report
`IsPlanStale()==true` so it will remove itself) Meanwhile the
ThreadPlanStepOut sees that it has stopped in the StackID it wanted to
run to, and return success.
This all changes when stopping at a breakpoint site doesn't report
breakpoint-hit until we actually execute the instruction. Now the
ThraedPlanStepOverBreakpoint looks at the thread's stop reason, it's
eStopReasonTrace (we've instruction stepped), and so it leaves its
auto-continue to `true`. ThreadPlanStepOut sees that it has reached its
goal StackID, removes its breakpoint, and says it is done.
Thread::ShouldStop thinks the auto-continue == yes vote from
ThreadPlanStepOverBreakpoint wins, and we lose control of the process.
This patch changes ThreadPlanStepOut to require that *both* (1) we are
at the StackID of the caller function, where we wanted to end up, and
(2) we have actually hit the breakpoint that we inserted.
This in effect means that now lldb instruction-steps over the breakpoint
in the callee function, stops at the return address of the caller
function. StepOverBreakpoint has completed. StepOut is still running,
and we continue the thread again. We immediatley hit the breakpoint
(that we're sitting at), and now ThreadPlanStepOut marks itself as
completed, and we return control to the user.
Jim suggests that ThreadPlanStepOverBreakpoint is a bit unusual because
it's not something pushed on the stack by a higher-order thread plan
that "owns" it, it is inserted by the Thread as it is about to resume,
if we're at a BreakpointSite. It has no connection to the thread plans
above it, but tries to set the auto-continue mode based on the state of
the thread when it is inserted (and tries to detect an unexpected
breakpoint and unset that auto-continue it previously decided on,
because it now realizes it should not influence execution control any
more). Instead maybe the
ThreadPlanStepOverBreakpoint should be inserted as a child plan of
whatever the lowest plan is on the stack at the point it is added.
I added an API test that will catch this bug in the new thread
breakpoint algorithm.
Commit: fa71238da800f3a818ec0e0649462389dc577890
https://github.com/llvm/llvm-project/commit/fa71238da800f3a818ec0e0649462389dc577890
Author: Jason Molenda <jmolenda at apple.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M lldb/source/Target/ThreadPlanStepOut.cpp
Log Message:
-----------
[lldb] inserted a typeo when checking in a suggested fix
Commit: 65ed4fa57e6293f8e059a368ac52e2a57b1f78e4
https://github.com/llvm/llvm-project/commit/65ed4fa57e6293f8e059a368ac52e2a57b1f78e4
Author: Nikhil Kalra <nkalra at apple.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/include/mlir-c/IR.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/python/ir/module.py
Log Message:
-----------
[mlir] Python: Parse ModuleOp from file path (#126572)
For extremely large models, it may be inefficient to load the model into
memory in Python prior to passing it to the MLIR C APIs for
deserialization. This change adds an API to parse a ModuleOp directly
from a file path.
Re-lands
[4e14b8a](https://github.com/llvm/llvm-project/commit/4e14b8afb44af58ab7073bb8c0b52875599b0ae1).
Commit: 92f916faba13e5cf575f6aef64405b51eaccfe9a
https://github.com/llvm/llvm-project/commit/92f916faba13e5cf575f6aef64405b51eaccfe9a
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
A llvm/include/llvm/CodeGen/DroppedVariableStatsMIR.h
A llvm/include/llvm/IR/DroppedVariableStats.h
A llvm/include/llvm/IR/DroppedVariableStatsIR.h
R llvm/include/llvm/Passes/DroppedVariableStats.h
R llvm/include/llvm/Passes/DroppedVariableStatsIR.h
M llvm/include/llvm/Passes/StandardInstrumentations.h
M llvm/lib/CodeGen/CMakeLists.txt
A llvm/lib/CodeGen/DroppedVariableStatsMIR.cpp
M llvm/lib/CodeGen/MachineFunctionPass.cpp
M llvm/lib/IR/CMakeLists.txt
A llvm/lib/IR/DroppedVariableStats.cpp
A llvm/lib/IR/DroppedVariableStatsIR.cpp
M llvm/lib/Passes/CMakeLists.txt
R llvm/lib/Passes/DroppedVariableStatsIR.cpp
M llvm/unittests/CodeGen/CMakeLists.txt
A llvm/unittests/CodeGen/DroppedVariableStatsMIRTest.cpp
Log Message:
-----------
Add a pass to collect dropped var statistics for MIR (#126686)
This patch attempts to reland
https://github.com/llvm/llvm-project/pull/120780 while addressing the
issues that caused the patch to be reverted.
Namely:
1. The patch had included code from the llvm/Passes directory in the
llvm/CodeGen directory.
2. The patch increased the backend compile time by 2% due to adding a
very expensive include in MachineFunctionPass.h
The patch has been re-structured so that there is no dependency between
the llvm/Passes and llvm/CodeGen directory, by moving the base class,
`class DroppedVariableStats` to the llvm/IR directory.
The expensive include in MachineFunctionPass.h has been changed to
contain forward declarations instead of other header includes which was
pulling a ton of code into MachineFunctionPass.h and should resolve any
issues when it comes to compile time increase.
Commit: c5a4512d853d7d2deef2080b1acb6272fa683bc3
https://github.com/llvm/llvm-project/commit/c5a4512d853d7d2deef2080b1acb6272fa683bc3
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
A llvm/test/CodeGen/AMDGPU/iglp-no-clobber.ll
Log Message:
-----------
[AMDGPU] iglp.opt does not clobber memory operands (#126976)
I think it was an accident that this wasn't included.
Commit: ceb00c07028491506bcf8e334bb12cab7792098f
https://github.com/llvm/llvm-project/commit/ceb00c07028491506bcf8e334bb12cab7792098f
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
Log Message:
-----------
[mlir][acc] Clean up TypedValue builders (#126968)
When MappableType was introduced alongside PointerLikeType, the data
clause operation builders were duplicated to accept a `TypedValue` of
one of the two type options. However, the underlying builder takes a
`Value` and this difference is not relevant for it. The only difference
is that `varType` is set differently depending on the type.
Having two duplicated builders can lead to clunky building since a
`Value` must always be cast to one of the two options. Thus, simply
clean this up - the verifier already checks that it is a type that
implements one of the two interfaces.
Commit: f3a29906aa07d08bbde7ec02b93d02e25d805110
https://github.com/llvm/llvm-project/commit/f3a29906aa07d08bbde7ec02b93d02e25d805110
Author: Nikhil Kalra <nkalra at apple.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/lib/Bytecode/Writer/BytecodeWriter.cpp
M mlir/unittests/Bytecode/BytecodeTest.cpp
Log Message:
-----------
[mlir] BytecodeWriter: invoke `reserveExtraSpace` (#126953)
Update `BytecodeWriter` to invoke `reserveExtraSpace` on the stream
before writing to it. This will give clients implementing custom output
streams the opportunity to allocate an appropriately sized buffer for
the write.
Commit: c6a39697a9334c5e159d75e45094d691a8f9db90
https://github.com/llvm/llvm-project/commit/c6a39697a9334c5e159d75e45094d691a8f9db90
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out.ll
Log Message:
-----------
[hwasan][NFCI] Add more test cases to llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out.ll (#126980)
Add more combinations of parameters to test that the skip conditions are
OR'ed together
Commit: 37952ef75f47440bc629e1a25571190f70bca09d
https://github.com/llvm/llvm-project/commit/37952ef75f47440bc629e1a25571190f70bca09d
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Passes/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
Log Message:
-----------
[gn build] Port 92f916faba13
Commit: 3e02069afe39a3c314476141b9dd90daad5803f2
https://github.com/llvm/llvm-project/commit/3e02069afe39a3c314476141b9dd90daad5803f2
Author: Nick Desaulniers <nick.desaulniers at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M libc/include/llvm-libc-macros/CMakeLists.txt
M libc/include/llvm-libc-macros/pthread-macros.h
M libc/test/integration/src/pthread/pthread_mutex_test.cpp
Log Message:
-----------
[libc][pthread] fix -Wmissing-field-initializers (#126314)
Fixes:
llvm-project/libc/test/integration/src/pthread/pthread_rwlock_test.cpp:59:29:
warning: missing field '__preference' initializer
[-Wmissing-field-initializers]
59 | pthread_rwlock_t rwlock = PTHREAD_RWLOCK_INITIALIZER;
| ^
Also, add a test that demonstrates the same issue for
PTHREAD_MUTEX_INITIALIZER, and fix that, too.
PTHREAD_ONCE_INIT does not have this issue and does have test coverage.
Commit: 31cb807537fa09b3f452ac9f93388ef202f6b4a8
https://github.com/llvm/llvm-project/commit/31cb807537fa09b3f452ac9f93388ef202f6b4a8
Author: vporpo <vporpodas at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
Log Message:
-----------
[SanbdoxVec][BottomUpVec] Fix diamond shuffle with multiple vector inputs (#126965)
When the operand comes from multiple inputs then we need additional
packing code. When the operands are scalar then we can use a single
InsertElementInst. But when the operands are vectors then we need a
chain of ExtractElementInst and InsertElementInst instructions to insert
the vector value into the destination vector. This is what this patch
implements.
Commit: dbfb29fd45a2a655e3e89b108f9a31fd764bd293
https://github.com/llvm/llvm-project/commit/dbfb29fd45a2a655e3e89b108f9a31fd764bd293
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M libcxx/docs/Hardening.rst
Log Message:
-----------
[libc++] Add a link to __builtin_verbose_trap from the hardening docs (#126930)
Commit: 5953e5a3c6e7c0d35f8b6282ba214eedd3228c40
https://github.com/llvm/llvm-project/commit/5953e5a3c6e7c0d35f8b6282ba214eedd3228c40
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M libcxx/utils/ci/run-buildbot
Log Message:
-----------
[libc++] Simplify the apple-system-hardened CI configuration (#126911)
It was basically a copy-paste of the non-hardened version of the same
job, and it's easy to remove the duplication.
Commit: 51c847d8f3d073c6d99a3dd4e6008645a8020b09
https://github.com/llvm/llvm-project/commit/51c847d8f3d073c6d99a3dd4e6008645a8020b09
Author: Amir Bishara <139038766+amirBish at users.noreply.github.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/invalid.mlir
Log Message:
-----------
[mlir][tosa]-Edit the verifier of tosa constShapeOp (#126962)
Add verification for rank 1 for the elements' attribute of the tosa
const_shape operation.
Commit: 1c207f1b6e8bba69dfbbcbd72704b4d720e363d0
https://github.com/llvm/llvm-project/commit/1c207f1b6e8bba69dfbbcbd72704b4d720e363d0
Author: vporpo <vporpodas at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/DependencyGraphTest.cpp
Log Message:
-----------
[SandboxVec][DAG] Fix DAG when old interval is mem free (#126983)
This patch fixes a bug in `DependencyGraph::extend()` when the old
interval contains no memory instructions. When this is the case we
should do a full dependency scan of the new interval.
Commit: 5586541d220ebbe27d8dea039d0165c3b2694b06
https://github.com/llvm/llvm-project/commit/5586541d220ebbe27d8dea039d0165c3b2694b06
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tensor/IR/Tensor.h
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
Log Message:
-----------
[mlir][tensor] Make useful Tensor utilities public (#126802)
1. Extract the main logic from `foldTensorCastPrecondition` into a
dedicated helper hook: `hasFoldableTensorCastOperand`. This allows
for reusing the corresponding checks.
2. Rename `getNewOperands` to `getUpdatedOperandsAfterCastOpFolding` for
better clarity and documentation of its functionality.
3. These updated hooks will be reused in:
* https://github.com/llvm/llvm-project/pull/123902. This PR makes
them public.
**Note:** Moving these hooks to `Tensor/Utils` is not feasible because
`MLIRTensorUtils` depends on `MLIRTensorDialect` (CMake targets). If
these hooks were moved to `Utils`, it would create a dependency of
`MLIRTensorDialect` on `MLIRTensorUtils`, leading to a circular
dependency.
Commit: bcba3117c057158472af83b36a38e0df0f57f4fc
https://github.com/llvm/llvm-project/commit/bcba3117c057158472af83b36a38e0df0f57f4fc
Author: Robert Imschweiler <50044286+ro-i at users.noreply.github.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id-unsupported-calling-convention.ll
Log Message:
-----------
[AMDGPU] SelDAG: fix lowering of undefined workitem intrinsics (#126058)
GlobalISel already handles undefined workitem.id.{x,y,z} intrinsics,
SelDAG failed in AMDGPUISelLowering.cpp due to a failed assertion in
`AMDGPUTargetLowering::loadInputValue`: `Arg && "Attempting to load
missing argument"`. This commit changes the behavior of SelDAG to
instead use a zero constant.
This LLVM defect was identified via the AMD Fuzzing project.
Commit: 105b3a92a72b9acdb01a9ce280a456bc4d5dce78
https://github.com/llvm/llvm-project/commit/105b3a92a72b9acdb01a9ce280a456bc4d5dce78
Author: Matthew Bastien <matthew_bastien at apple.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/package.json
M lldb/tools/lldb-dap/src-ts/debug-adapter-factory.ts
Log Message:
-----------
[lldb-dap] add `debugAdapterExecutable` property to launch configuration (#126803)
The Swift extension for VS Code requires that the `lldb-dap` executable
come from the Swift toolchain which may or may not be configured in
`PATH`. At the moment, this can be configured via LLDB DAP's extension
settings, but experience has shown that modifying other extensions'
settings on behalf of the user (especially those subject to change
whenever a new toolchain is selected) causes issues. Instead, it would
be easier to have this configurable in the launch configuration and let
the Swift extension (or any other extension that wanted to, really)
configure the path to `lldb-dap` that way. This allows the Swift
extension to have its own launch configuration type that delegates to
the LLDB DAP extension in order to provide a more seamless debugging
experience for Swift executables.
This PR adds a new property to the launch configuration object called
`debugAdapterExecutable` which allows overriding the `lldb-dap`
executable path for a specific debug session.
Commit: 6936fadfc32023a029ac7ff757bf8f40092ee2b1
https://github.com/llvm/llvm-project/commit/6936fadfc32023a029ac7ff757bf8f40092ee2b1
Author: Florian Mayer <fmayer at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_allocator_local_cache.h
Log Message:
-----------
[compiler-rt] [sanitizer] avoid UB in allocator (#126977)
Commit: 4078b11daa5b4902f59fa79c1647a20532b16c55
https://github.com/llvm/llvm-project/commit/4078b11daa5b4902f59fa79c1647a20532b16c55
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/test/Dialect/Affine/loop-fusion-4.mlir
Log Message:
-----------
[MLIR][Affine] Fix fusion crash for non-int/fp memref elt types (#126829)
Fix assumption on memref elt types being int or float during private
memref creation in affine fusion.
Fixes: https://github.com/llvm/llvm-project/issues/121020
Commit: 42382386843244cbbac0e23029e07969048e62c7
https://github.com/llvm/llvm-project/commit/42382386843244cbbac0e23029e07969048e62c7
Author: Da-Viper <57949090+Da-Viper at users.noreply.github.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/src-ts/debug-adapter-factory.ts
Log Message:
-----------
[lldb-dap] Fix: Could not find DAP in path (#126903)
Fixes #120839
Commit: 1b582ef3c0a887409b513aae282682b23c7a1a41
https://github.com/llvm/llvm-project/commit/1b582ef3c0a887409b513aae282682b23c7a1a41
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/package.json
Log Message:
-----------
[lldb-dap] Bump the version number for publishing in the Marketplace
Commit: 51d82552037290f9368a43ef7a6e4e642b8c28f4
https://github.com/llvm/llvm-project/commit/51d82552037290f9368a43ef7a6e4e642b8c28f4
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmovn.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/qshrn.ll
Log Message:
-----------
[msan] Handle Arm NEON saturating extract and narrow (#125742)
This handles NEON saturating extract and narrow (Intrinsic::aarch64_neon_{sqxtn, sqxtun, uqxtn}) by (ab)using handleShadowOr() to perform the shadow cast. Previously, these were unknown intrinsics handled suboptimally by visitInstruction.
Updates the tests from https://github.com/llvm/llvm-project/pull/125288 and https://github.com/llvm/llvm-project/pull/125140
Commit: a6f7cb54d3c268ea4748a0ff783b4b030c3195d9
https://github.com/llvm/llvm-project/commit/a6f7cb54d3c268ea4748a0ff783b4b030c3195d9
Author: Tristan Ross <tristan.ross at midstall.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/cmake/config-ix.cmake
M llvm/include/llvm/Config/config.h.cmake
M llvm/lib/Support/Unix/Process.inc
Log Message:
-----------
[Support] Prefer AUX vector for page size (#126863)
Prefers the page size to come from the AUX vector, `getpagesize` is
removed from POSIX.1-2001. Also throws in a couple asserts to ensure the
page size is a valid value.
Commit: 8421ad7f4515653001c3927734fc6204367478a0
https://github.com/llvm/llvm-project/commit/8421ad7f4515653001c3927734fc6204367478a0
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/test/Dialect/Affine/loop-fusion-2.mlir
M mlir/test/Dialect/Affine/loop-fusion-4.mlir
M mlir/test/Dialect/Affine/loop-fusion.mlir
Log Message:
-----------
[MLIR][Affine] Fix sibling fusion - missing check (#126626)
Fix sibling fusion for slice maximality check. Producer-consumer fusion
had this check but not sibling fusion. Sibling fusion shouldn't be
performed if the slice isn't "maximal" (i.e., if it isn't the whole of
the source).
Fixes: https://github.com/llvm/llvm-project/issues/48703
Commit: 3e223e3a202c046b6553aac91d79b6abd089ee8d
https://github.com/llvm/llvm-project/commit/3e223e3a202c046b6553aac91d79b6abd089ee8d
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][vector] Fix out-of-bounds access (#126734)
This PR fixes an out-of-bounds bug that occurs when there are no overlap
dimensions between the `sizes` and source of
`vector.extract_strided_slice`, causing access to `sizes` to go out of
bounds. Fixes #126196.
Commit: 8ed36373a2227c7d39fb1a520ec8dde476dc5603
https://github.com/llvm/llvm-project/commit/8ed36373a2227c7d39fb1a520ec8dde476dc5603
Author: Florian Mayer <fmayer at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M compiler-rt/lib/sanitizer_common/symbolizer/scripts/global_symbols.txt
Log Message:
-----------
[NFC] [sanitizer] allow getauxval in symbolizer
Commit: df07121d54432175ffc211d4165bfe7090c58c5e
https://github.com/llvm/llvm-project/commit/df07121d54432175ffc211d4165bfe7090c58c5e
Author: Thurston Dang <thurston at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
Log Message:
-----------
[hwasan][NFCI] Rename ClRandomSkipRate to ClRandomKeepRate (#126990)
The meaning of ClRandomSkipRate was inverted in
https://github.com/llvm/llvm-project/pull/88070 but the variable name
was not changed. This patch fixes it to avoid confusion.
Additionally, it elaborates the flag description to mention the
interaction between the random keep rate and hotness cutoff.
Commit: 73ab0c076215125a249eee117f51f2ce4f5f9b50
https://github.com/llvm/llvm-project/commit/73ab0c076215125a249eee117f51f2ce4f5f9b50
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M lldb/tools/lldb-dap/package-lock.json
M lldb/tools/lldb-dap/package.json
Log Message:
-----------
[lldb-dap] Upgrade @types/node to fix TS2386 in node/module.d.ts (#126994)
Upgrade @types/node to work around an issue in TypeScript [1] that
caused our "publish to VSCode Marketplace" github action [2] to fail:
```
node_modules/@types/node/module.d.ts:290:13 - error TS2386: Overload signatures must all be optional or required.
290 resolve?(specified: string, parent?: string | URL): Promise<string>;
```
[1] https://github.com/microsoft/TypeScript/pull/59259#issuecomment-2228833941
[2] https://github.com/llvm/vscode-lldb/actions/runs/13298213337/job/37134713009
Commit: 30a9941624350523535bdec201c895698c171afd
https://github.com/llvm/llvm-project/commit/30a9941624350523535bdec201c895698c171afd
Author: Koakuma <koachan at protonmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/Driver/sparc-ias-Wa.s
Log Message:
-----------
[SPARC][IAS] Add IAS flag handling for ISA levels
Add IAS flag handling for ISA levels we support in LLVM.
Reviewers: MaskRay, rorth, brad0, s-barannikov
Reviewed By: MaskRay
Pull Request: https://github.com/llvm/llvm-project/pull/125151
Commit: 89d636ba91924c945d39f02f261863b709249744
https://github.com/llvm/llvm-project/commit/89d636ba91924c945d39f02f261863b709249744
Author: Brad Smith <brad at comstyle.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/cmake/config-ix.cmake
M llvm/include/llvm/Config/config.h.cmake
M llvm/lib/Support/Unix/Process.inc
Log Message:
-----------
[Support] Fix building on FreeBSD and OpenBSD (#127005)
Fix building after a6f7cb54d3c268ea4748a0ff783b4b030c3195d9.
Check for the function getauxval() instead of just the sys/auxv.h
header.
Commit: cdf45447ef7fe127848dc5e3144006a3391f46a3
https://github.com/llvm/llvm-project/commit/cdf45447ef7fe127848dc5e3144006a3391f46a3
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.cpp
Log Message:
-----------
Orc: Suppress a warning in #126691
Commit: 9bd836adbbb20246a5b0f08a019aa662d1c6dcd7
https://github.com/llvm/llvm-project/commit/9bd836adbbb20246a5b0f08a019aa662d1c6dcd7
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h
M utils/bazel/llvm_configs/config.h.cmake
Log Message:
-----------
[bazel] Introduce HAVE_SYS_AUXV_H for #126863
Commit: 9456e7fcdd8de6af6bcbc82c91e447729eb27af5
https://github.com/llvm/llvm-project/commit/9456e7fcdd8de6af6bcbc82c91e447729eb27af5
Author: Lang Hames <lhames at gmail.com>
Date: 2025-02-13 (Thu, 13 Feb 2025)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.cpp
Log Message:
-----------
[ORC] Silence unused variable warnings.
Commit: 7b473dfe84c17319930d4019ab3f6ca0cfc03416
https://github.com/llvm/llvm-project/commit/7b473dfe84c17319930d4019ab3f6ca0cfc03416
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M flang/include/flang/Optimizer/OpenACC/FIROpenACCTypeInterfaces.h
M flang/include/flang/Tools/PointerModels.h
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/OpenACC/CMakeLists.txt
M flang/lib/Optimizer/OpenACC/FIROpenACCTypeInterfaces.cpp
M flang/lib/Optimizer/OpenACC/RegisterOpenACCExtensions.cpp
M flang/test/Fir/OpenACC/openacc-mappable.fir
A flang/test/Fir/OpenACC/openacc-type-categories.f90
M flang/test/lib/OpenACC/TestOpenACCInterfaces.cpp
Log Message:
-----------
[flang][acc] Implement type categorization for FIR types (#126964)
The OpenACC type interfaces have been updated to require that a type
self-identify which type category it belongs to. Ensure that FIR types
are able to provide this self identification.
In addition to implementing the new API, the PointerLikeType interface
attachment was moved to FIROpenACCSupport library like MappableType to
ensure all type interfaces and their implementation are now in the same
spot.
Commit: 1032df6f607b6bee55b5340a878dfcfc17d12653
https://github.com/llvm/llvm-project/commit/1032df6f607b6bee55b5340a878dfcfc17d12653
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M llvm/lib/Passes/PassBuilderPipelines.cpp
A llvm/test/LTO/X86/coro.ll
M llvm/test/Other/new-pm-O0-defaults.ll
M llvm/test/Other/new-pm-lto-defaults.ll
Log Message:
-----------
[LTO][Pipelines][Coro] Handle coroutines in LTO pipeline (#126168)
ThinLTO delays handling of coroutines to ThinLTO backend.
However it's usually possible to use ThinLTO prelink objects for FullLTO.
In this case we have left-over coroutines which crash in codegen.
Issue #104525.
Commit: 3ece7bc2693a53dc1c0982573b17a4d0f9ae9366
https://github.com/llvm/llvm-project/commit/3ece7bc2693a53dc1c0982573b17a4d0f9ae9366
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M .github/CODEOWNERS
M .github/workflows/release-binaries-all.yml
M bolt/include/bolt/Core/BinarySection.h
M bolt/tools/driver/llvm-bolt.cpp
M bolt/unittests/Core/BinaryContext.cpp
M clang/docs/HLSL/FunctionCalls.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/TypeSanitizer.rst
M clang/docs/analyzer/developer-docs/PerformanceInvestigation.rst
A clang/docs/analyzer/images/flamegraph.png
A clang/docs/analyzer/images/uftrace_detailed.png
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/Mangle.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/FPOptions.def
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Basic/LangOptions.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.def
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/CallDescription.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Analysis/LiveVariables.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/lib/CodeGen/CGObjCRuntime.h
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenModule.h
M clang/lib/CodeGen/Targets/NVPTX.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/ROCm.h
M clang/lib/Format/UnwrappedLineFormatter.cpp
M clang/lib/Sema/HeuristicResolver.cpp
M clang/lib/Sema/JumpDiagnostics.cpp
M clang/lib/Sema/SemaAVR.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaMIPS.cpp
M clang/lib/Sema/SemaMSP430.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaRISCV.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/StaticAnalyzer/Checkers/StackAddrEscapeChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/cxx26.cpp
M clang/test/AST/ByteCode/new-delete.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-counted-const-member.cpp
M clang/test/Analysis/Checkers/WebKit/mock-types.h
M clang/test/Analysis/Checkers/WebKit/uncounted-obj-arg.mm
M clang/test/Analysis/analyzer-config.c
M clang/test/Analysis/copy-elision.cpp
M clang/test/Analysis/live-stmts.cpp
M clang/test/Analysis/loop-assumptions.c
R clang/test/Analysis/no-outofbounds.c
M clang/test/Analysis/out-of-bounds-constraint-check.c
M clang/test/Analysis/out-of-bounds-diagnostics.c
M clang/test/Analysis/out-of-bounds.c
M clang/test/Analysis/stack-addr-ps.cpp
M clang/test/Analysis/stackaddrleak.c
M clang/test/Analysis/stackaddrleak.cpp
M clang/test/CMakeLists.txt
A clang/test/CXX/stmt.stmt/stmt.select/stmt.switch/p4.cpp
M clang/test/CodeGenCUDA/launch-bounds.cu
R clang/test/CodeGenHLSL/disable_opt.hlsl
M clang/test/CodeGenHLSL/inline-functions.hlsl
M clang/test/Driver/amdgpu-openmp-sanitize-options.c
M clang/test/Driver/dep-file-flag-with-multiple-offload-archs.hip
M clang/test/Driver/hip-sanitize-options.hip
M clang/test/Driver/linker-wrapper.c
A clang/test/Driver/sparc-ias-Wa.s
M clang/test/Driver/sycl-offload-jit.cpp
A clang/test/Modules/pr126373.cppm
M clang/test/OpenMP/ordered_codegen.cpp
A clang/test/OpenMP/spirv_variant_match.cpp
A clang/test/Sema/avr-interript-signal-attr.c
R clang/test/Sema/avr-interrupt-attr.c
R clang/test/Sema/avr-signal-attr.c
M clang/test/SemaCXX/uninitialized.cpp
A clang/test/SemaHLSL/use-cxx-alt-operator-names.hlsl
M clang/test/Tooling/clang-linker-wrapper-spirv-elf.cpp
M clang/test/Tooling/lit.local.cfg
M clang/tools/clang-installapi/Options.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/Sema/HeuristicResolverTest.cpp
M compiler-rt/lib/builtins/cpu_model/riscv.c
M compiler-rt/lib/profile/InstrProfiling.h
M compiler-rt/lib/profile/InstrProfilingFile.c
M compiler-rt/lib/sanitizer_common/sanitizer_allocator_local_cache.h
M compiler-rt/lib/sanitizer_common/symbolizer/scripts/global_symbols.txt
M compiler-rt/lib/sanitizer_common/tests/sanitizer_libc_test.cpp
M compiler-rt/lib/scudo/standalone/chunk.h
M compiler-rt/lib/scudo/standalone/report.cpp
M compiler-rt/lib/scudo/standalone/report.h
M compiler-rt/lib/scudo/standalone/tests/report_test.cpp
M compiler-rt/test/builtins/Unit/arm/aeabi_idivmod_test.c
M compiler-rt/test/builtins/Unit/arm/aeabi_uidivmod_test.c
M compiler-rt/test/builtins/Unit/arm/aeabi_uldivmod_test.c
M flang/CMakeLists.txt
M flang/include/flang/Optimizer/Dialect/CMakeLists.txt
M flang/include/flang/Optimizer/Dialect/FIRType.h
M flang/include/flang/Optimizer/OpenACC/FIROpenACCTypeInterfaces.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/include/flang/Semantics/openmp-directive-sets.h
M flang/include/flang/Tools/PointerModels.h
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/PrivateReductionUtils.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/OpenACC/CMakeLists.txt
M flang/lib/Optimizer/OpenACC/FIROpenACCTypeInterfaces.cpp
M flang/lib/Optimizer/OpenACC/RegisterOpenACCExtensions.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/runtime/CMakeLists.txt
M flang/test/Analysis/AliasAnalysis/alias-analysis-2.fir
A flang/test/Analysis/AliasAnalysis/alias-analysis-target.fir
M flang/test/Evaluate/rewrite-out_of_range.F90
M flang/test/Fir/OpenACC/openacc-mappable.fir
A flang/test/Fir/OpenACC/openacc-type-categories.f90
M flang/test/Fir/box.fir
M flang/test/Fir/convert-to-llvm.fir
M flang/test/Fir/fir-ops.fir
M flang/test/Fir/rebox-global.fir
A flang/test/Fir/target-rewrite-indirect-calls.fir
M flang/test/Fir/type-descriptor.fir
A flang/test/Integration/abi-indirect-call.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-private-unwrap-defaultbounds.f90
M flang/test/Lower/OpenACC/acc-private.f90
M flang/test/Lower/OpenMP/parallel-private-clause-str.f90
M flang/test/Semantics/OpenMP/nested-target.f90
M flang/test/Semantics/OpenMP/nested-teams.f90
M flang/test/lib/OpenACC/TestOpenACCInterfaces.cpp
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/headers/math/stdfix.rst
M libc/include/__llvm-libc-common.h
M libc/include/llvm-libc-macros/CMakeLists.txt
M libc/include/llvm-libc-macros/endian-macros.h
M libc/include/llvm-libc-macros/features-macros.h
M libc/include/llvm-libc-macros/pthread-macros.h
M libc/include/llvm-libc-types/struct_tm.h
M libc/include/stdfix.yaml
M libc/src/__support/CPP/bit.h
M libc/src/__support/FPUtil/double_double.h
M libc/src/__support/fixed_point/CMakeLists.txt
M libc/src/__support/fixed_point/fx_bits.h
M libc/src/__support/fixed_point/fx_rep.h
M libc/src/__support/macros/optimization.h
M libc/src/complex/generic/CMakeLists.txt
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/atan2f.cpp
A libc/src/math/generic/atan2f_float.h
M libc/src/math/generic/pow.cpp
M libc/src/math/generic/range_reduction_double_common.h
M libc/src/math/generic/range_reduction_double_fma.h
M libc/src/math/generic/range_reduction_double_nofma.h
M libc/src/stdfix/CMakeLists.txt
A libc/src/stdfix/countlshk.cpp
A libc/src/stdfix/countlshk.h
A libc/src/stdfix/countlshr.cpp
A libc/src/stdfix/countlshr.h
A libc/src/stdfix/countlsk.cpp
A libc/src/stdfix/countlsk.h
A libc/src/stdfix/countlslk.cpp
A libc/src/stdfix/countlslk.h
A libc/src/stdfix/countlslr.cpp
A libc/src/stdfix/countlslr.h
A libc/src/stdfix/countlsr.cpp
A libc/src/stdfix/countlsr.h
A libc/src/stdfix/countlsuhk.cpp
A libc/src/stdfix/countlsuhk.h
A libc/src/stdfix/countlsuhr.cpp
A libc/src/stdfix/countlsuhr.h
A libc/src/stdfix/countlsuk.cpp
A libc/src/stdfix/countlsuk.h
A libc/src/stdfix/countlsulk.cpp
A libc/src/stdfix/countlsulk.h
A libc/src/stdfix/countlsulr.cpp
A libc/src/stdfix/countlsulr.h
A libc/src/stdfix/countlsur.cpp
A libc/src/stdfix/countlsur.h
M libc/src/time/CMakeLists.txt
M libc/src/time/mktime.cpp
M libc/src/time/time_constants.h
M libc/src/time/time_utils.cpp
M libc/src/time/time_utils.h
M libc/test/integration/src/pthread/pthread_mutex_test.cpp
M libc/test/src/__support/CPP/bit_test.cpp
M libc/test/src/stdbit/stdc_bit_ceil_uc_test.cpp
M libc/test/src/stdbit/stdc_bit_ceil_us_test.cpp
M libc/test/src/stdbit/stdc_first_leading_one_uc_test.cpp
M libc/test/src/stdbit/stdc_first_leading_one_us_test.cpp
M libc/test/src/stdbit/stdc_first_leading_zero_uc_test.cpp
M libc/test/src/stdbit/stdc_first_leading_zero_us_test.cpp
M libc/test/src/stdbit/stdc_first_trailing_one_uc_test.cpp
M libc/test/src/stdbit/stdc_first_trailing_one_us_test.cpp
M libc/test/src/stdbit/stdc_first_trailing_zero_uc_test.cpp
M libc/test/src/stdbit/stdc_first_trailing_zero_us_test.cpp
M libc/test/src/stdbit/stdc_has_single_bit_uc_test.cpp
M libc/test/src/stdbit/stdc_has_single_bit_us_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_uc_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_us_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_uc_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_us_test.cpp
M libc/test/src/stdbit/stdc_trailing_ones_uc_test.cpp
M libc/test/src/stdbit/stdc_trailing_ones_us_test.cpp
M libc/test/src/stdbit/stdc_trailing_zeros_uc_test.cpp
M libc/test/src/stdbit/stdc_trailing_zeros_us_test.cpp
M libc/test/src/stdfix/CMakeLists.txt
A libc/test/src/stdfix/CountlsTest.h
A libc/test/src/stdfix/countlshk_test.cpp
A libc/test/src/stdfix/countlshr_test.cpp
A libc/test/src/stdfix/countlsk_test.cpp
A libc/test/src/stdfix/countlslk_test.cpp
A libc/test/src/stdfix/countlslr_test.cpp
A libc/test/src/stdfix/countlsr_test.cpp
A libc/test/src/stdfix/countlsuhk_test.cpp
A libc/test/src/stdfix/countlsuhr_test.cpp
A libc/test/src/stdfix/countlsuk_test.cpp
A libc/test/src/stdfix/countlsulk_test.cpp
A libc/test/src/stdfix/countlsulr_test.cpp
A libc/test/src/stdfix/countlsur_test.cpp
M libc/utils/docgen/docgen.py
M libc/utils/docgen/sys/time.yaml
M libclc/CMakeLists.txt
A libclc/clc/include/clc/clc_convert.h
A libclc/clc/include/clc/common/clc_sign.h
A libclc/clc/include/clc/float/definitions.h
M libclc/clc/include/clc/math/gentype.inc
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/common/clc_sign.cl
A libclc/clc/lib/generic/common/clc_sign.inc
M libclc/generic/include/clc/convert.h
R libclc/generic/include/clc/float/definitions.h
M libclc/generic/lib/common/sign.cl
M libclc/generic/lib/gen_convert.py
M libcxx/docs/Hardening.rst
M libcxx/include/__config
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find/find.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find/ranges.find.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.foreach/for_each.pass.cpp
M libcxx/utils/ci/run-buildbot
M libcxx/utils/generate_feature_test_macro_components.py
M libcxxabi/src/cxa_default_handlers.cpp
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/UserSettingsController.h
M lldb/source/API/SBDebugger.cpp
M lldb/source/Commands/CommandObjectDisassemble.cpp
M lldb/source/Commands/CommandObjectDisassemble.h
M lldb/source/Core/CMakeLists.txt
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/DynamicLoader.cpp
M lldb/source/Core/Telemetry.cpp
M lldb/source/Core/UserSettingsController.cpp
M lldb/source/Interpreter/ScriptInterpreter.cpp
M lldb/source/Plugins/DynamicLoader/Darwin-Kernel/DynamicLoaderDarwinKernel.cpp
M lldb/source/Plugins/DynamicLoader/FreeBSD-Kernel/DynamicLoaderFreeBSDKernel.cpp
M lldb/source/Plugins/InstrumentationRuntime/TSan/InstrumentationRuntimeTSan.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTrampolineHandler.cpp
M lldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp
M lldb/source/Plugins/ScriptInterpreter/None/ScriptInterpreterNone.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Symbol/SymbolContext.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/ThreadPlanStepOut.cpp
M lldb/source/Target/ThreadPlanTracer.cpp
A lldb/test/API/functionalities/thread/finish-from-empty-func/Makefile
A lldb/test/API/functionalities/thread/finish-from-empty-func/TestEmptyFuncThreadStepOut.py
A lldb/test/API/functionalities/thread/finish-from-empty-func/main.c
M lldb/test/Shell/Commands/command-disassemble.s
M lldb/tools/lldb-dap/package-lock.json
M lldb/tools/lldb-dap/package.json
M lldb/tools/lldb-dap/src-ts/debug-adapter-factory.ts
M llvm/cmake/config-ix.cmake
M llvm/cmake/modules/LLVMConfig.cmake.in
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/LangRef.rst
M llvm/docs/NVPTXUsage.rst
M llvm/docs/WritingAnLLVMBackend.rst
M llvm/include/llvm/Analysis/DDG.h
M llvm/include/llvm/Analysis/DependenceAnalysis.h
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/include/llvm/Analysis/SparsePropagation.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
A llvm/include/llvm/CodeGen/DroppedVariableStatsMIR.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/MachinePipeliner.h
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/CodeGen/TargetFrameLowering.h
M llvm/include/llvm/Config/config.h.cmake
M llvm/include/llvm/Config/llvm-config.h.cmake
M llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
M llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.h
M llvm/include/llvm/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.h
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
A llvm/include/llvm/IR/DroppedVariableStats.h
A llvm/include/llvm/IR/DroppedVariableStatsIR.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/InstrTypes.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/MC/MCContext.h
M llvm/include/llvm/MC/MCELFStreamer.h
M llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
R llvm/include/llvm/Passes/DroppedVariableStats.h
R llvm/include/llvm/Passes/DroppedVariableStatsIR.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Passes/StandardInstrumentations.h
M llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/InstrMaps.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Scheduler.h
M llvm/lib/Analysis/DDG.cpp
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/Analysis/DependenceGraphBuilder.cpp
M llvm/lib/Analysis/LoopCacheAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/CFIFixup.cpp
M llvm/lib/CodeGen/CMakeLists.txt
M llvm/lib/CodeGen/CodeGen.cpp
A llvm/lib/CodeGen/DroppedVariableStatsMIR.cpp
M llvm/lib/CodeGen/MachineFunctionPass.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/RegAllocBasic.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/UnwindInfoManager.cpp
M llvm/lib/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.cpp
M llvm/lib/Frontend/OpenMP/OMPContext.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/CMakeLists.txt
M llvm/lib/IR/DebugInfo.cpp
A llvm/lib/IR/DroppedVariableStats.cpp
A llvm/lib/IR/DroppedVariableStatsIR.cpp
M llvm/lib/MC/MCContext.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/MC/MCParser/WasmAsmParser.cpp
M llvm/lib/Object/GOFFObjectFile.cpp
M llvm/lib/Passes/CMakeLists.txt
R llvm/lib/Passes/DroppedVariableStatsIR.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Support/Unix/Process.inc
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.h
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
A llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
M llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
M llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCTargetDesc.h
M llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
M llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
M llvm/lib/Target/AMDGPU/R600InstrInfo.h
M llvm/lib/Target/AMDGPU/R600Packetizer.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
M llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.h
M llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
M llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
M llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
M llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
M llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
M llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
M llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
M llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Hexagon/HexagonLoopAlign.cpp
M llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
M llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
M llvm/lib/Target/Hexagon/HexagonPeephole.cpp
M llvm/lib/Target/Hexagon/HexagonPseudo.td
M llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
M llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp
M llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
M llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h
M llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
M llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp
M llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.h
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
M llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp
M llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.h
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXCtorDtorLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/RISCV/CMakeLists.txt
M llvm/lib/Target/RISCV/RISCV.h
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
A llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
M llvm/lib/Target/X86/X86DomainReassignment.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/Xtensa/Disassembler/CMakeLists.txt
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Utils/CodeMoverUtils.cpp
M llvm/lib/Transforms/Utils/LoopUnrollAndJam.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Scheduler.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Analysis/BasicAA/fallback-mayalias.ll
M llvm/test/Analysis/KernelInfo/launch-bounds/nvptx.ll
A llvm/test/Analysis/LoopAccessAnalysis/retry-runtime-checks-after-dependence-analysis.ll
M llvm/test/CMakeLists.txt
A llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
A llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
A llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lsfe.ll
A llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a_fp.ll
M llvm/test/CodeGen/AArch64/Atomics/generate-tests.py
M llvm/test/CodeGen/AArch64/a55-fuse-address.mir
M llvm/test/CodeGen/AArch64/align-down.ll
M llvm/test/CodeGen/AArch64/ampere1-sched-add.mir
M llvm/test/CodeGen/AArch64/cfi-fixup-multi-section.mir
M llvm/test/CodeGen/AArch64/cluster-frame-index.mir
M llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir
M llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
M llvm/test/CodeGen/AArch64/force-enable-intervals.mir
M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
A llvm/test/CodeGen/AArch64/llvm.sincospi.ll
M llvm/test/CodeGen/AArch64/machine-scheduler.mir
M llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir
M llvm/test/CodeGen/AArch64/macro-fusion-last.mir
M llvm/test/CodeGen/AArch64/misched-branch-targets.mir
M llvm/test/CodeGen/AArch64/misched-bundle.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir
M llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir
M llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir
M llvm/test/CodeGen/AArch64/misched-move-imm.mir
M llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
M llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
M llvm/test/CodeGen/AArch64/sched-postidxalias.mir
M llvm/test/CodeGen/AArch64/sched-print-cycle.mir
M llvm/test/CodeGen/AArch64/scheduledag-constreg.mir
M llvm/test/CodeGen/AArch64/sve-aliasing.mir
A llvm/test/CodeGen/AArch64/veclib-llvm.sincospi.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-branch-weight-metadata.ll
R llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
M llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
M llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
M llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
M llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir
M llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
A llvm/test/CodeGen/AMDGPU/iglp-no-clobber.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id-unsupported-calling-convention.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-pointer-ops.ll
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx940.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-mfma-scale.gfx950.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
M llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
M llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
M llvm/test/CodeGen/ARM/misched-branch-targets.mir
A llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-cs.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-lib.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/lib-entry-attr-error.ll
M llvm/test/CodeGen/DirectX/llc-pipeline.ll
R llvm/test/CodeGen/Mips/readcyclecounter.ll
M llvm/test/CodeGen/NVPTX/addrspacecast.ll
M llvm/test/CodeGen/NVPTX/annotations.ll
M llvm/test/CodeGen/NVPTX/lower-ctor-dtor.ll
M llvm/test/CodeGen/NVPTX/maxclusterrank.ll
A llvm/test/CodeGen/NVPTX/prefetch.ll
M llvm/test/CodeGen/NVPTX/upgrade-nvvm-annotations.ll
M llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir
M llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll
M llvm/test/CodeGen/RISCV/GlobalISel/combine-neg-abs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll
M llvm/test/CodeGen/RISCV/GlobalISel/stacksave-stackrestore.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/O0-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abds.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
M llvm/test/CodeGen/RISCV/abdu.ll
M llvm/test/CodeGen/RISCV/add-before-shl.ll
M llvm/test/CodeGen/RISCV/add-imm.ll
M llvm/test/CodeGen/RISCV/alloca.ll
M llvm/test/CodeGen/RISCV/alu64.ll
M llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
M llvm/test/CodeGen/RISCV/atomic-rmw.ll
M llvm/test/CodeGen/RISCV/atomic-signext.ll
M llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/RISCV/bf16-promote.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/bfloat-mem.ll
M llvm/test/CodeGen/RISCV/bfloat.ll
M llvm/test/CodeGen/RISCV/bittest.ll
M llvm/test/CodeGen/RISCV/branch-on-zero.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/calling-conv-half.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32e.ll
M llvm/test/CodeGen/RISCV/calls.ll
M llvm/test/CodeGen/RISCV/codemodel-lowering.ll
M llvm/test/CodeGen/RISCV/condbinops.ll
M llvm/test/CodeGen/RISCV/condops.ll
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/double-calling-conv.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/double-imm.ll
M llvm/test/CodeGen/RISCV/double-mem.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
M llvm/test/CodeGen/RISCV/fastcc-bf16.ll
M llvm/test/CodeGen/RISCV/fastcc-float.ll
M llvm/test/CodeGen/RISCV/fastcc-half.ll
M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/float-select-fcmp.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
M llvm/test/CodeGen/RISCV/forced-atomics.ll
M llvm/test/CodeGen/RISCV/fp-fcanonicalize.ll
M llvm/test/CodeGen/RISCV/fp128.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/get-setcc-result-type.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-mem.ll
M llvm/test/CodeGen/RISCV/half-select-fcmp.ll
M llvm/test/CodeGen/RISCV/iabs.ll
M llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
M llvm/test/CodeGen/RISCV/inline-asm-d-modifier-N.ll
M llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
M llvm/test/CodeGen/RISCV/inline-asm-f-modifier-N.ll
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M llvm/test/CodeGen/RISCV/memset-pattern.ll
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M llvm/test/CodeGen/RISCV/neg-abs.ll
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M llvm/test/CodeGen/RISCV/split-offsets.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/stack-slot-size.ll
M llvm/test/CodeGen/RISCV/stack-store-check.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/RISCV/ucmp.ll
M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
M llvm/test/CodeGen/RISCV/xtheadmempair.ll
M llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
M llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
M llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bit_instructions/cl_khr_extended_bit_ops.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bit_instructions/cl_khr_extended_bit_ops_ocl_only.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bit_instructions/cl_khr_extended_bit_ops_spv-friendly_only.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bit_instructions/spirv-friendly_extended_bit_ops.ll
M llvm/test/CodeGen/SPIRV/lit.local.cfg
M llvm/test/CodeGen/X86/2011-10-27-tstore.ll
M llvm/test/CodeGen/X86/align-down.ll
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/CodeGen/X86/avx512fp16-mov.ll
M llvm/test/CodeGen/X86/coalescer-subreg.ll
M llvm/test/CodeGen/X86/code_placement_eh.ll
M llvm/test/CodeGen/X86/codegen-prepare-cast.ll
M llvm/test/CodeGen/X86/copy-low-subvec-elt-to-high-subvec-elt.ll
M llvm/test/CodeGen/X86/discontiguous-loops.ll
M llvm/test/CodeGen/X86/early-ifcvt-crash.ll
M llvm/test/CodeGen/X86/expand-vp-cast-intrinsics.ll
M llvm/test/CodeGen/X86/fast-isel-stackcheck.ll
M llvm/test/CodeGen/X86/fp-fold.ll
M llvm/test/CodeGen/X86/fp-stack-O0-crash.ll
M llvm/test/CodeGen/X86/fp-stack.ll
M llvm/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir
M llvm/test/CodeGen/X86/insert-positions.ll
M llvm/test/CodeGen/X86/legalize-sub-zero-2.ll
M llvm/test/CodeGen/X86/licm-symbol.ll
M llvm/test/CodeGen/X86/liveness-local-regalloc.ll
M llvm/test/CodeGen/X86/lsr-overflow.ll
M llvm/test/CodeGen/X86/matrix-multiply.ll
M llvm/test/CodeGen/X86/not-of-dec.ll
M llvm/test/CodeGen/X86/pr51615.ll
M llvm/test/CodeGen/X86/vec-strict-cmp-128-fp16.ll
M llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll
M llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll
M llvm/test/CodeGen/X86/vec-strict-fptoint-256.ll
M llvm/test/CodeGen/X86/vec-strict-fptoint-512.ll
M llvm/test/CodeGen/X86/vector-half-conversions.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
M llvm/test/CodeGen/X86/vselect-avx.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/CodeGen/XCore/2010-02-25-LSR-Crash.ll
M llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-cvt.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vadd.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmovn.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/qshrn.ll
M llvm/test/Instrumentation/MemorySanitizer/scmp.ll
M llvm/test/Instrumentation/MemorySanitizer/ucmp.ll
A llvm/test/LTO/X86/coro.ll
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
M llvm/test/MC/AMDGPU/hsa-gfx12-v4.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx11.s
M llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx12.s
M llvm/test/Other/new-pm-O0-defaults.ll
M llvm/test/Other/new-pm-lto-defaults.ll
A llvm/test/TableGen/get-named-operand-idx.td
M llvm/test/Transforms/InstCombine/icmp-dom.ll
M llvm/test/Transforms/InstCombine/known-bits.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fully-unrolled-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
A llvm/test/Transforms/LoopVectorize/X86/scev-checks-unprofitable.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
A llvm/test/Transforms/PhaseOrdering/AArch64/udotabd.ll
A llvm/test/Transforms/SLPVectorizer/SystemZ/reuse-non-power-of-2-reorder.ll
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
M llvm/test/Transforms/SandboxVectorizer/bottomup_seed_slice_pow2.ll
M llvm/test/Transforms/SandboxVectorizer/repeated_instrs.ll
M llvm/test/Transforms/SandboxVectorizer/scheduler.ll
A llvm/test/Transforms/Util/strip-nonlinetable-debuginfo-pr125116.ll
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx11.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx12.s
M llvm/tools/llvm-jitlink/llvm-jitlink-executor/llvm-jitlink-executor.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/tools/spirv-tools/CMakeLists.txt
M llvm/unittests/CodeGen/CMakeLists.txt
A llvm/unittests/CodeGen/DroppedVariableStatsMIRTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/DependencyGraphTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/InstrMapsTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/SchedulerTest.cpp
M llvm/utils/TableGen/Common/CodeGenSchedule.h
M llvm/utils/TableGen/InstrInfoEmitter.cpp
M llvm/utils/git/code-format-helper.py
M llvm/utils/git/github-automation.py
M llvm/utils/gn/secondary/lldb/source/Core/BUILD.gn
M llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Passes/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
M mlir/cmake/modules/MLIRConfig.cmake.in
M mlir/include/mlir-c/IR.h
A mlir/include/mlir/Dialect/Arith/Transforms/ShardingInterfaceImpl.h
M mlir/include/mlir/Dialect/DLTI/DLTI.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td
M mlir/include/mlir/Dialect/Mesh/Interfaces/ShardingInterface.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/Tensor/IR/Tensor.h
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/include/mlir/InitAllDialects.h
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
M mlir/lib/Analysis/DataFlow/IntegerRangeAnalysis.cpp
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Bytecode/Writer/BytecodeWriter.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopFusion.cpp
M mlir/lib/Dialect/Arith/Transforms/CMakeLists.txt
A mlir/lib/Dialect/Arith/Transforms/ShardingInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/DLTI/DLTI.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/Linalg/Transforms/DataLayoutPropagation.cpp
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Interfaces/ShardingInterface.cpp
M mlir/lib/Dialect/Mesh/Transforms/ShardingPropagation.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
M mlir/lib/Dialect/Tensor/Extensions/MeshShardingExtensions.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaReduceTransposes.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/lib/Target/LLVM/NVVM/Target.cpp
M mlir/lib/Target/LLVMIR/CMakeLists.txt
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/lib/Transforms/RemoveDeadValues.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm-interface.mlir
M mlir/test/Dialect/Affine/loop-fusion-2.mlir
M mlir/test/Dialect/Affine/loop-fusion-4.mlir
M mlir/test/Dialect/Affine/loop-fusion.mlir
A mlir/test/Dialect/Arith/mesh-spmdize.mlir
A mlir/test/Dialect/Arith/sharding-propagation.mlir
M mlir/test/Dialect/Bufferization/canonicalize.mlir
M mlir/test/Dialect/GPU/module-to-binary-nvvm.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Dialect/Linalg/data-layout-propagation.mlir
M mlir/test/Dialect/Mesh/canonicalization.mlir
M mlir/test/Dialect/Mesh/ops.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/constant-op-fold.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/tosa-reduce-transposes.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/Dialect/XeGPU/XeGPUOps.mlir
M mlir/test/Dialect/XeGPU/invalid.mlir
M mlir/test/Interfaces/InferIntRangeInterface/infer-int-range-test-ops.mlir
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer.mlir
A mlir/test/Target/LLVMIR/Import/call-argument-attributes.ll
A mlir/test/Target/LLVMIR/Import/invoke-argument-attributes.ll
A mlir/test/Target/LLVMIR/call-argument-attributes.mlir
M mlir/test/Target/LLVMIR/external-func-dialect-attr.mlir
A mlir/test/Target/LLVMIR/invoke-argument-attributes.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
M mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-host.mlir
M mlir/test/Transforms/remove-dead-values.mlir
M mlir/test/mlir-tblgen/gen-dialect-doc.td
A mlir/test/mlir-tblgen/gen-pass-doc.td
M mlir/test/python/dialects/gpu/module-to-binary-nvvm.py
M mlir/test/python/ir/module.py
M mlir/tools/mlir-tblgen/OpDocGen.cpp
M mlir/tools/mlir-tblgen/OpInterfacesGen.cpp
M mlir/tools/mlir-tblgen/PassDocGen.cpp
M mlir/unittests/Bytecode/BytecodeTest.cpp
M offload/include/Shared/Environment.h
M offload/plugins-nextgen/common/include/GlobalHandler.h
M offload/plugins-nextgen/common/include/RPC.h
M offload/plugins-nextgen/common/src/GlobalHandler.cpp
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/common/src/RPC.cpp
M offload/test/lit.cfg
M offload/test/lit.site.cfg.in
M offload/test/offloading/pgo1.c
M openmp/docs/design/Runtimes.rst
A openmp/runtime/test/misc_bugs/simd_conservative_ordered.c
M utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h
M utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/mlir-tblgen/BUILD.bazel
M utils/bazel/llvm_configs/config.h.cmake
M utils/bazel/llvm_configs/llvm-config.h.cmake
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