[all-commits] [llvm/llvm-project] 7b60e0: Reland "CodeGen][NewPM] Port MachineScheduler to N...

[Akshat Oke via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7b60e03d739166d5ad63719ebf772272f2d91781
      https://github.com/llvm/llvm-project/commit/7b60e03d739166d5ad63719ebf772272f2d91781
  Author: Akshat Oke <Akshat.Oke at amd.com>
  Date:   2025-02-12 (Wed, 12 Feb 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineScheduler.h
    M llvm/include/llvm/InitializePasses.h
    M llvm/include/llvm/Passes/CodeGenPassBuilder.h
    M llvm/include/llvm/Passes/MachinePassRegistry.def
    M llvm/lib/CodeGen/CodeGen.cpp
    M llvm/lib/CodeGen/MachineScheduler.cpp
    M llvm/lib/CodeGen/RegAllocBasic.cpp
    M llvm/lib/CodeGen/RegAllocGreedy.cpp
    M llvm/lib/Passes/PassBuilder.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/test/CodeGen/AArch64/a55-fuse-address.mir
    M llvm/test/CodeGen/AArch64/ampere1-sched-add.mir
    M llvm/test/CodeGen/AArch64/cluster-frame-index.mir
    M llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir
    M llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
    M llvm/test/CodeGen/AArch64/force-enable-intervals.mir
    M llvm/test/CodeGen/AArch64/machine-scheduler.mir
    M llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir
    M llvm/test/CodeGen/AArch64/macro-fusion-last.mir
    M llvm/test/CodeGen/AArch64/misched-branch-targets.mir
    M llvm/test/CodeGen/AArch64/misched-bundle.mir
    M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
    M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
    M llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir
    M llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir
    M llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir
    M llvm/test/CodeGen/AArch64/misched-move-imm.mir
    M llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
    M llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
    M llvm/test/CodeGen/AArch64/sched-postidxalias.mir
    M llvm/test/CodeGen/AArch64/sched-print-cycle.mir
    M llvm/test/CodeGen/AArch64/scheduledag-constreg.mir
    M llvm/test/CodeGen/AArch64/sve-aliasing.mir
    M llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
    M llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
    M llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
    M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
    M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
    M llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir
    M llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
    M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
    M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
    M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
    M llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
    M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
    M llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
    M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
    M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
    M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
    M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
    M llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
    M llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
    M llvm/test/CodeGen/ARM/misched-branch-targets.mir
    M llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir
    M llvm/test/CodeGen/RISCV/misched-postra-direction.mir

  Log Message:
  -----------
  Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)

`RegisterClassInfo` was supposed to be kept alive between pass runs,
which wasn't being done leading to recomputations increasing the compile
time.

Now the Impl class is a member of the legacy and new passes so that it
is not reconstructed on every pass run.

---------

Co-authored-by: Christudasan Devadasan <christudasan.devadasan at amd.com>



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