[all-commits] [llvm/llvm-project] ea6827: [RISCV] Improve Errors for GPRNoX0 Reg Class (#126...

[Sam Elliott via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ea6827cacfde062c7d9f03266af5298499313176
      https://github.com/llvm/llvm-project/commit/ea6827cacfde062c7d9f03266af5298499313176
  Author: Sam Elliott <quic_aelliott at quicinc.com>
  Date:   2025-02-10 (Mon, 10 Feb 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/test/MC/RISCV/rv32c-invalid.s
    M llvm/test/MC/RISCV/rv64c-invalid.s
    M llvm/test/MC/RISCV/rvc-hints-invalid.s
    M llvm/test/MC/RISCV/xqcia-invalid.s
    M llvm/test/MC/RISCV/xqciac-invalid.s
    M llvm/test/MC/RISCV/xqcicli-invalid.s
    M llvm/test/MC/RISCV/xqcicm-invalid.s
    M llvm/test/MC/RISCV/xqcics-invalid.s
    M llvm/test/MC/RISCV/xqcicsr-invalid.s
    M llvm/test/MC/RISCV/xqciint-invalid.s
    M llvm/test/MC/RISCV/xqcilsm-invalid.s
    M llvm/test/MC/RISCV/xqcisls-invalid.s
    M llvm/test/MC/RISCV/zicfiss-invalid.s

  Log Message:
  -----------
  [RISCV] Improve Errors for GPRNoX0 Reg Class (#126397)

More adoption of better diagnostics for RISC-V register classes:
- GPRNoX0 (GPRs excluding `zero`)



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